6259

Data Sheet
26186.120
ADVANCE INFORMATION 8-BIT ADDRESSABLE
(Subject to change without notice) DMOS POWER DRIVER
January 24, 2000
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
POWER
GROUND
1 20
POWER
GROUND
decoder and accompanying data latches, control circuitry, and DMOS
LOGIC 2 VDD 19 CLEAR
outputs in a multi-functional power driver capable of storing single-line
SUPPLY
data in the addressable latches or use as a decoder or demuliplexer.
S 0 (LSB) 3 18 DATA Driver applications include relays, solenoids, and other medium-current
OUT 0 4 17 OUT 7 or high-voltage peripheral power loads.
DECODER LOGIC

The CMOS inputs and latches allow direct interfacing with micro-
LATCHES

LATCHES

OUT 1 5 16 OUT 6

OUT 2 6 15 OUT 5 processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
OUT 3 7 14 OUT 4
selectable with the CLEAR and ENABLE inputs.
S1 8 EN 13 ENABLE
The addressed DMOS output inverts the DATA input with all
LOGIC
GROUND
9 12 S 2 (MSB)
unaddressed outputs remaining in their previous states. All of the output
POWER 10 11 POWER drivers are disabled (the DMOS sink drivers turned off) with the
GROUND GROUND
CLEAR input low and the ENABLE input high. The A6259KA/KLW
Dwg. PP-050-2
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
Note that the A6259KA (DIP) and the A6259KLW devices with reduced rDS(on) are available as the A6A259.
(SOIC) are electrically identical and share a
common terminal number assignment. The A6259KA is furnished in a 20-pin dual in-line plastic package.
ABSOLUTE MAXIMUM RATINGS The A6259KLW is furnished in a 20-lead wide-body, small-outline
at TA = 25°C plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
Output Voltage, VO ............................ 50 V low on-state resistance allow both devices to sink 150 mA from all
Output Drain Current, outputs continuously, to ambient temperatures over 85°C.
Continuous, IO ...................... 250 mA*
Peak, IOM ............................. 750 mA*†
Peak, IOM ................................... 2.0 A† FEATURES
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ ■ 50 V Minimum Output Clamp Voltage
Logic Supply Voltage, VDD .............. 7.0 V ■ 250 mA Output Current (all outputs simultaneously)
Input Voltage Range, ■ 1.3 Ω Typical rDS(on)
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation, ■ Low Power Consumption
PD ....................................... See Graph ■ Replacements for TPIC6259N and TPIC6259DW
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Always order by complete part number:
Caution: These CMOS devices have input static Part Number Package RθJA RθJC
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static A6259KA 20-pin DIP 55°C/W 25°C/W
electrical charges. A6259KLW 20-lead SOIC 70°C/W 17°C/W
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

LOGIC SYMBOL
2.5
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

3 0
8 8M 0/7
2.0 12 2
13 G8
SU
FF 18 Z9
IX 19
'A Z10
', R
1.5 θJ 9,0D
4
A = 10,0R
SU 55
FF °C
IX /W 9,1D
5
'LW 10,1R
', R
θJ 9,2D
1.0 A =7 10,2R
6
0°
C/ 9,3D
W 7
10,3R
9,4D
10,4R 14
0.5
9,5D
10,5R 15

9,6D 16
10,6R
0
25 50 75 100 125 150 9,7D
17
10,7R
AMBIENT TEMPERATURE IN °C
Dwg. GS-004A Dwg. FP-046

VDD
OUT
IN

Dwg. EP-063
Dwg. EP-010-15

LOGIC INPUTS DMOS POWER DRIVER OUTPUT

FUNCTION TABLE LATCH SELECTION TABLE

Inputs Addressed Other Select Inputs Addressed
CLEAR ENABLE DATA OUTPUT OUTPUTs Function S2 (MSB) S1 S0 (LSB) OUTPUT
H L H L R Addressable L L L 0
H L L H R Latch L L H 1
H H X R R Memory L H L 2
L L H L H 8-Line L H H 3
L L L H H Demultiplexer H L L 4
L H X H H Clear H L H 5
H H L 6
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State H H H 7

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

FUNCTIONAL BLOCK DIAGRAM

D
S0 OUT 0
(LSB) C1

CLR

D
OUT 1
C1

CLR
S1
D
OUT 2
C1

CLR

D
OUT 3
C1

CLR
S2
(MSB) D
OUT 4
C1

CLR

D
LOGIC OUT 5
V DD
SUPPLY C1

CLR
LOGIC
GROUND
D
OUT 6
C1

CLR

DATA D
OUT 7
ENABLE C1
(ACTIVE LOW)
CLR POWER
CLEAR GROUND
(ACTIVE LOW)
Dwg. FP-047-1

Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.

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 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

RECOMMENDED OPERATING CONDITIONS

over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise

specified).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Logic Supply Voltage VDD Operating 4.5 5.0 5.5 V
Output Breakdown V(BR)DSX IO = 1 mA 50 — — V
Voltage
Off-State Output IDSX VO = 40 V — 0.05 1.0 µA
Current
VO = 40 V, TA = 125°C — 0.15 5.0 µA
Static Drain-Source rDS(on) IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω
On-State Resistance
IO = 250 mA, VDD = 4.5 V, TA = 125°C — 2.0 3.2 Ω
IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω
Nominal Output IO(nom) VDS(on) = 0.5 V, TA = 85°C — 250 — mA
Current
Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 µA
IIL VI = 0, VDD = 5.5 V — — -1.0 µA
Prop. Delay Time tPLH IO = 250 mA, CL = 30 pF — 625 — ns
tPHL IO = 250 mA, CL = 30 pF — 140 — ns
Output Rise Time tr IO = 250 mA, CL = 30 pF — 650 — ns
Output Fall Time tf IO = 250 mA, CL = 30 pF — 400 — ns
Supply Current IDD(off) VDD = 5.5 V, Outputs OFF — 15 100 µA
IDD(on) VDD = 5.5 V, Outputs ON — 150 300 µA
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤ 100 µs, duty cycle ≤ 2%.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS

Four modes of operation are selectable by controlling

ENABLE
the CLEAR and ENABLE inputs as shown above.

DATA 50% In the addressable-latch mode, data at the DATA input

t PLH t PHL
is written into the addressed transparent latch. The
ADDRESSED
90% addressed output inverts the data input with all other
OUTPUT 10% outputs remaining in their previous states.
tr tf

Dwg. WP-036 In the memory mode, all outputs remain in their

OUTPUT SWITCHING TIME previous states and are unaffected by the DATA or
address (Sn) inputs. To prevent entering erroneus data in
the latches, ENABLE should be held HIGH while the
address lines are changing.
ENABLE 50% In the demultiplexing/decoding mode, the addressed
t su(D) t h(D) output inverts the data input and all other outputs are OFF.
DATA 50%
In the clear mode, all outputs are OFF and are unaf-
t w(D) fected by the DATA or address (SN) inputs.
Dwg. WP-037

Given the appropriate inputs, when DATA is LOW

DATA INPUT REQUIREMENTS for a given address, the output is OFF; when DATA is
Data Active Time Before Enable HIGH, the output is ON and can sink current.
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD

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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

TEST CIRCUITS
+15 V
INPUT

0.11 Ω
tav

100 mH
IAS = 1.0 A
IO

DUT
OUT

VO V(BR)DSX

VO(ON)
Dwg. EP-066-1

EAS = IAS x V(BR)DSX x tAV/2

Single-Pulse Avalanche Energy Test Circuit

and Waveforms

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

TERMINAL DESCRIPTIONS

Terminal No. Terminal Name Function

1 POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
3 S0 Binary-coded output-select input, least-significant bit.
4 OUT0 Current-sinking, open-drain DMOS output, address 000.
5 OUT1 Current-sinking, open-drain DMOS output, address 001.
6 OUT2 Current-sinking, open-drain DMOS output, address 010.
7 OUT3 Current-sinking, open-drain DMOS output, address 011.
8 S1 Binary-coded output-select input.
9 LOGIC GROUND Reference terminal for input voltage measurements.
10 POWER GROUND Reference terminal for output voltage measurements (OUT0-3).
11 POWER GROUND Reference terminal for output voltage measurements (OUT4-7).
12 S2 Binary-coded output-select input, most-significant bit.
13 ENABLE Mode control input; see Function Table.
14 OUT4 Current-sinking, open-drain DMOS output, address 100.
15 OUT5 Current-sinking, open-drain DMOS output, address 101.
16 OUT6 Current-sinking, open-drain DMOS output, address 110.
17 OUT7 Current-sinking, open-drain DMOS output, address 111.
18 DATA CMOS data input to the addressed output latch. When enabled, the
addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).
19 CLEAR Mode control input; see Function Table.
20 POWER GROUND Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.

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 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

A6259KA
Dimensions in Inches
(controlling dimensions)

0.014
0.008
20 11

0.430
MAX
0.280
0.240 0.300
BSC

1 10
0.070 0.100 0.005
0.045 BSC MIN
1.060
0.980

0.210
MAX

0.015 0.150
MIN 0.115

0.022
0.014 Dwg. MA-001-20 in

Dimensions in Millimeters
(for reference only)

0.355
0.204
20 11

10.92
MAX
7.11
6.10 7.62
BSC

1 10
1.77 2.54 0.13
1.15 BSC MIN
26.92
24.89

5.33
MAX

0.39 3.81
MIN 2.93

0.558
0.356 Dwg. MA-001-20 mm

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

A6259KLW
Dimensions in Inches
(for reference only)
20 11
0.0125
0.0091

0.2992 0.419
0.2914 0.394

0.050
0.016

0.020 1 2 3 0.050
0.013 0.5118 BSC 0° TO 8°
0.4961

0.0926
0.1043

0.0040 MIN. Dwg. MA-008-20 in

Dimensions in Millimeters
(controlling dimensions)
20 11
0.32
0.23

7.60 10.65
7.40 10.00

1.27
0.40

0.51 1 2 3 1.27
0.33 13.00 BSC 0° TO 8°
12.60

2.65
2.35

0.10 MIN. Dwg. MA-008-20 mm

NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.

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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
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