Assignment

1. Explain the working of a multiplexer. What are its uses?

2. Discuss the method of implementing the Boolean expressions using
Multiplexers.
3. Implement a full subtractor circuit using MUXs.
4. How can two 8:1MUXs be cascaded to use it a 16:1 MUX?
5. What is a Demultiplexer? Draw the logic circuit of 1: 4 demultiplexer
and discuss it working.

6. What is a decoder? Discuss 3 to 8 line decoder having an enable

terminal (active high). Also show that a decoder and Demultiplexer are same.
7. Implement SUM and Carry of a full adder with 3 to 8 line decoder and
two OR gates.
8. What is BCD to decimal decoder? Draw its logic diagram and explain
its working.

9. How can two 3 to 8 line decoder be used as a 4 to 16 line decoder?

10. Design a decoder that displays 4 bit BCD input to seven segment
form. Realize the circuit using
(i) 4 : 1 MUXs
(ii) NAND gates alone
(iii) NOR gates alone
11. Repeat the problem 10 if the inputs are in 4 bit excess – 3 code.
12. What is a code converter? Design an 8421 to 2421 code converter. Draw its logic
diagram using
(i) NAND gates
(ii) NOR gates
(iii) MUXs
(iv) 4 X 16 PROM
13. What is an encoder? Draw the logic diagram of octal to binary
encoder.
14. Draw and explain the logic diagram of Decimal to BCD encoder.
15. What is priority encoder? Draw the logic diagram of decimal to BCD
priority encoder.
16. Discuss octal to Binary priority encoder.
17. What is magnitude comparator? Draw the logic diagram of 4 – bit magnitude comparator
and explain its working.
18. How two 4 – bit magnitude comparators be used as a 8 –bit comparator.
19. What are programmable logic devices? Name popularly known PLDs. Explain any one of
them in detail.
20. Discuss 4 – bit parity bit generator cum checker.
21. Realize the following function of four variables using 8:1 MUXs.
(0,2,4,6,7,13 ,15 ) 1 F A B C D(i) ( , , , )
(0,1,3,4,5,8,9,10 ,14 ,15 ) 2 F A B C D(ii) ( , , , )
(0,4,6,7,8,9,10 ,12 ,13 ,14 ,15 ) 3 F A B C D(iii) ( , , , )
(0,1,2,3,5,8,9,12 ,13 ,14 ,15 ) 4 F A B C D(iv) ( , , , )
22. Repeat the problem 21 using 4 to 16 line decoder and 4 OR gates.
23. What is Field Programmable Logic Array (FPLA)? Explain how the programming
of AND and OR arrays in FPLA is done.
24. What are Programmable array logic (PAL) devices? What is the difference
between FPLA and PAL devices?
25. Explain Programmable Read only Memory (PROM). How does the architecture of a
FPLA differ from those of PROM and PAL?
26. Implement a excess – 3 to seven segment decoder using FLA of proper specification.
27. Using the PAL shown in figure 6.47, implement the following SOP functions of 4
variables.
D 0C AD C B AD B AD C AX
D 1C B AX
C 2AD C A X
D 3B D AB AC B X
28. Using 16 X 4 PROM, implement the 4 –bit binary– to– Excess 3 conversion