EPROMS Progr

Instructions for Programming TUTOR EPROMs
The TUTOR code will be programmed into two 2764 EPROM chips from files which reside in the
EPROM directory of the hard disk on the PC nearest the TA office door. The files are named
TUTOR.EVN and TUTOR.ODD, and contain the even and odd bytes respectively of the TUTOR
code.
The procedure for preparing the chips is as follows:
1. Obtain two blank 2764 devices from the TA. If you are not certain the devices are blank,
have the TA show you how to use the EPROM eraser (if you don't already know), and erase
the devices for 15 minutes.
2. Boot up the PC in the lab, which has the EPROM programming system, installed in it
(closest one to the door to the TA office). Change directories to the EPROM directory.
3. Enter the command UPP512. This is the program, which you will use to program the
EPROM's. A menu will appear on the screen.
4. Select the 12.5 Volt level.
5. Select the Load (L) menu option. You will be prompted for a buffer start address (enter
0000) and a file name (enter TUTOR.EVN or TUTOR.ODD).
6. Select the Blank Check and Copy (4) option. A "Ready?” prompt will appear. Insert a
blank 2764 in the EPROM programmer socket and enter Y. The program will then proceed
to blank check, program, and verify the device.
7. Repeat steps 5 and 6 for the other file. When you are finished, select menu option Q (quit).
CEG 453/653 EPROM Handout 1/3

Using the Logic Analyzer to Verify Bootstrap Action
The file "bootstrap.la" in the logic analyzer can be used to verify that the circuit functions
correctly for the first 8 bus cycles after reset. The following 8 bytes should appear on the data bus
after RESET* has been asserted:
HEX 00 04 00 81 from ROM0

HEX 00 44 00 46 from ROM1
HEX 00 01 02 03 04 05 06 07 from 68008 address
The reset vectors are SP = $0000 0444

PC = $0000 8146
1. Make sure that both Logic Analyzer and your circuit are turned off.
2. Make the following connections to POD1 and POD2 on your Logic Analyzer:
SIGNAL LEAD COLOR SIGNAL LEAD COLOR

D0 0 BLACK AS* 8 BLACK
D1 1 BROWN A0 9 BROWN
D2 2 RED A1 10 RED
POD1A
POD2A
D3 3 ORANGE A2 11 ORANGE
D4 4 YELLOW A3 12 YELLOW
D5 5 GREEN ROMEN0* 13 GREEN
D6 6 BLUE ROMEN1* 14 BLUE
D7 7 MAGENTA RESET*a 15 MAGENTA
a
BOOT-CLR*
3. Connect the GND pin of each Logic POD to your circuit’s ground (i.e., with a GRAY wire)
4. Open the Logic Analyzer.
5. On the Logic Analyzer, select the "bootstrap" setting and load it.
6. Power up your circuit. Your circuit should be in single step mode
7. Set the trigger condition for the assertion of AS*. The trigger mode is set to single step.
8. Check the valid data at the appropriate addresses. Take few more samples to check your
bootstrap action is working fine.
NOTES:
1. There should be 4 distinct signals from the reset module: HALT*, RESET*, SLAVE-CLR*
(to PIA & baud-Generator) and BOOT-CLR*(to DDVM).
2. Addresses A01-A13 from the CPU should be connected to A00-A12 on the ROM.

2764 EPROM Pinout
2764 EPROM
Vpp 1 28 Vcc
A12 2 27 PGM*
A7 3 26 N.C.
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 OE*
A2 8 21 A10
A1 9 20 CE*
A0 10 19 D7
D0 11 18 D6
D1 12 17 D5
D2 13 16 D4
GND 14 15 D3
NOTES:
•= Vpp: Programming Voltage. Connect to Vcc for reading

•= CE*: Chip Enable
•= OE*: Output Enable
•= PGM*: Program/Read Mode: Connect to Vcc for Reading

NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
January 1999
NMC27C64
65,536-Bit (8192 x 8) CMOS EPROM
General Description suited for high volume production applications where cost is an
important factor and programming only needs to be done once.
The NMC27C64 is a 64K UV erasable, electrically reprogrammable
and one-time programmable (OTP) CMOS EPROM ideally suited This family of EPROMs are fabricated with Fairchild’s proprietary,
for applications where fast turnaround, pattern experimentation time proven CMOS double-poly silicon gate technology which
and low power consumption are important requirements. combines high performance and high density with low power
consumption and excellent reliability.
The NMC27C64 is designed to operate with a single +5V power
supply with ±10% tolerance. The CMOS design allows the part to Features
operate over extended and military temperature ranges.
■ High performance CMOS
The NMC27C64Q is packaged in a 28-pin dual-in-line package — 150 ns access time
with a quartz window. The quartz window allows the user to
■ JEDEC standard pin configuration
expose the chip to ultraviolet light to erase the bit pattern. A new
— 28-pin Plastic DIP package
pattern can then be written electrically into the device by following
— 28-pin CERDIP package
the programming procedure.
■ Drop-in replacement for 27C64 or 2764
The NMC27C64N is packaged in a 28-pin dual-in-line plastic
■ Manufacturers identification code
molded package without a transparent lid. This part is ideally
Block Diagram
VCC
GND Data Outputs O0 - O7
VPP
OE Output Enable,
PGM Chip Enable, and
Program Logic Output
CE
Buffers
..
Y Decoder
A0 - A12 65,536-Bit
Address Cell Matrix
Inputs
.......
X Decoder
DS008634-1
© 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

NMC27C64 Rev. C
Connection Diagram
27C512 27C256 27C128 27C32 27C16 27C16 27C32 27C128 27C256 27C512
27512 27256 27128 2732 2716 NMC27C64 2716 2732 27128 27256 27512
A15 VPP VPP VPP 1 28 VCC VCC VCC VCC

A12 A12 A12 A12 2 27 PGM PGM A14 A14
A7 A7 A7 A7 A7 A7 3 26 NC VCC VCC A13 A13 A13
A6 A6 A6 A6 A6 A6 4 25 A8 A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 A5 5 24 A9 A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 A4 6 23 A11 VPP A11 A11 A11 A11
A3 A3 A3 A3 A3 A3 7 22 OE OE OE/VPP OE OE OE/VPP
A2 A2 A2 A2 A2 A2 8 21 A10 A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 A1 9 20 CE CE/PGM CE CE CE/PGM CE
A0 A0 A0 A0 A0 A0 10 19 O7 O7 O7 O7 O7 O7
O0 O0 O0 O0 O0 O0 11 18 O6 O6 O6 O6 O6 O6
O1 O1 O1 O1 O1 O1 12 17 O5 O5 O5 O5 O5 O5
O2 O2 O2 O2 O2 O2 13 16 O4 O4 O4 O4 O4 O4
GND GND GND GND GND GND 14 15 O3 O3 O3 O3 O3 O3
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64 pins. DS008634-2
Pin Names
A0–A12 Addresses
CE Chip Enable
OE Output Enable
O0 –O7 Outputs
PGM Program
NC No Connect
VPP Programming
Voltage
VCC Power Supply
GND Ground
Commercial Temperature Range VCC = 5V ±10%

Parameter/Order Number Access Time (ns)
NMC27C64Q, N 150 150
NMC27C64Q, N 200 200
Extended Temp Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number Access Time (ns)
NMC27C64QE, NE200 200
2 www.fairchildsemi.com
NMC27C64 Rev. C
Absolute Maximum Ratings (Note 1) Power Dissipation 1.0W
Temperature Under Bias -55°C to +125°C Lead Temperature

(Soldering, 10 sec.) 300°C
Storage Temperature -65°C to +150°C
ESD Rating
All Input Voltages except A9 (Mil Spec 883C,
with Respect to Ground (Note 10) +6.5V to -0.6V Method 3015.2) 2000V
All Output Voltages
with Respect to Ground (Note 10)VCC +1.0V to GND -0.6V
Operating Conditions (Note 7)
Temperature Range
VPP Supply Voltage and A9
NMC27C64Q 150, 200 0°C to +70°C
with Respect to Ground
NMC27C64N 150, 200
During Programming +14.0V to -0.6V
NMC27C64QE 200 -40°C to +85°C
VCC Supply Voltage with NMC27C64NE 200
Respect to Ground +7.0V to -0.6V
VCC Power Supply +5V ±10%
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILI Input Load Current VIN = VCC or GND 10 µA
ILO Output Leakage Current VOUT = VCC or GND, CE = VIH 10 µA
ICC1 VCC Current (Active) CE = VIL ,f=5 MHz 5 20 mA
(Note 9) TTL Inputs Inputs = VIH or VIL, I/O = 0 mA
ICC2 VCC Current (Active) CE = GND, f = 5 MHz 3 10 mA
(Note 9) CMOS Inputs Inputs = VCC or GND, I/O = 0 mA
ICCSB1 VCC Current (Standby) CE = VIH 0.1 1 mA
TTL Inputs
ICCSB2 VCC Current (Standby) CE = VCC 0.5 100 µA
CMOS Inputs
IPP VPP Load Current VPP = VCC 10 µA
VIL Input Low Voltage -0.1 0.8 V
VIH Input High Voltage 2.0 VCC +1 V
VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOL2 Output Low Voltage IOL = 0 µA 0.1 V
VOH2 Output High Voltage IOH = 0 µA VCC - 0.1 V
AC Electrical Characteristics
NMC27C64
Symbol Parameter Conditions 150 200, E200 Units
Min Max Min Max
tACC Address to CE = OE = VIL 150 200 ns
Output Delay PGM = VIH
tCE CE to Output Delay OE = VIL, PGM = VIH 150 200 ns
tOE OE to Output Delay CE = VIL, PGM = VIH 60 60 ns
tDF OE High to Output Float CE = VIL, PGM = VIH 0 60 0 60 ns
tCF CE High to Output Float OE = VIL, PGM = VIH 0 60 0 60 ns
tOH Output Hold from CE = OE = VIL
Addresses, CE or OE , PGM = VIH 0 0 ns
Whichever Occurred First
NMC27C64 Rev. C
Capacitance TA = +25˚C, f = 1 MHz (Note 2) NMC27C64Q
Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN = 0V 6 8 pF
COUT Output Capacitance VOUT = 0V 9 12 pF
Capacitance TA = +25˚C, f = 1 MHz (Note 2) NMC27C64N

Symbol Parameter Conditions Typ Max Units
CIN Input Capacitance VIN = 0V 5 10 pF
COUT Output Capacitance VOUT = 0V 8 10 pF
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Note 6) (Note 9)
2V
ADDRESS 0.8V Address Valid
2V
CE
0.8V t CF
(Notes 4, 5)
t CE
2V
OE 0.8V
t OE t DF
(Note 3) (Notes 4, 5)
2V Hi-Z Hi-Z
OUTPUT Valid Output
0.8V
t ACC
t OH
(Note 3)
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE ® , the measured VOH1 (DC) ˛ 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL: 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
NMC27C64 Rev. C
Programming Characteristics (Note 11) (Note 12) (Note 13) (Note 14)
Symbol Parameter Conditions Min Typ Max Units
tAS Address Setup Time 2 µs
tOES OE Setup Time 2 µs
tCES CE Setup Time 2 µs
tDS Data Setup Time 2 µs
tVPS VPP Setup Time 2 µs
tVCS VCC Setup Time 2 µs
tAH Address Hold Time 0 µs
tDH Data Hold Time 2 µs
tDF Output Enable to CE = VIL 0 130 ns
Output Float Delay
tPW Program Pulse Width 0.45 0.5 0.55 ms
tOE Data Valid from OE CE = VIL 150 ns
IPP VPP Supply Current During CE = VIL 30 mA
Programming Pulse PGM = VIL
ICC VCC Supply Current 10 mA
TA Temperature Ambient 20 25 30 ˚C
VCC Power Supply Voltage 5.75 6.0 6.25 V
VPP Programming Supply Voltage 12.2 13.0 13.3 V
tFR Input Rise, Fall Time 5 ns
VIL Input Low Voltage 0.0 0.45 V
VIH Input High Voltage 2.4 4.0 V
tIN Input Timing Reference Voltage 0.8 1.5 2.0 V
tOUT Output Timing Reference Voltage 0.8 1.5 2.0 V
NMC27C64 Rev. C
Programming Waveforms (Note 13)
Program
Program Verify
2V
ADDRESS 0.8V Address N
t AS t AH
2V Data In Stable
Hi-Z Data Out Valid
DATA Add N
0.8V Add N
t DS t DH t DF
6.0V
VCC tVCS
VPP 13.0V t VPS
CE 0.8V
t CES
2V
PGM 0.8V
t PW t OES t OE
2V
OE 0.8V
Note 11: Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.
NMC27C64 Rev. C
Fast Programming Algorithm Flow Chart
Start
ADDR = First Location
VCC = 6.25 V
VPP = 12.75V
X=0
Program one 100 µs Pulse
Increment X
Yes
X = 20 ?
No
Fail Verify Verify Fail Device

Byte Byte Failed
Pass Pass
No Last
Increment ADDR Address
Yes
1st VCC = VPP =5.5V Fail Device

2nd VCC = VPP =4.5V Failed
Pass
Device Passed
FIGURE 1.
NMC27C64 Rev. C
Functional Description To most efficiently use these two control lines, it is recomended
that CE (pin 20) be decoded and used as the primary device
DEVICE OPERATION selecting function, while OE (pin 22) be made a common connec-
tion to all devices in the array and connected to the READ line from
The six modes of operation of the NMC27C64 are listed in Table
the system control bus. This assures that all deselected memory
1. It should be noted that all inputs for the six modes are at TTL
devices are in their low power standby modes and that the output
levels. The power supplies required are VCC and VPP. The VPP
pins are active only when data is desired from a particular memory
power supply must be at 12.75V during the three programming
device.
modes, and must be at 5V in the other three modes. The VCC
power supply must be at 6V during the three programming modes, Programming
and at 5V in the other three modes.
CAUTION: Exceeding 14V on pin 1 (VPP) will damage the
Read Mode NMC27C64.
The NMC27C64 has two control functions, both of which must be Initially, all bits of the NMC27C64 are in the “1” state. Data is
logically active in order to obtain data at the outputs. Chip Enable introduced by selectively programming “0s” into the desired bit
(CE) is the power control and should be used for device selection. locations. Although only “0s” will be programmed, both “1s” and
Output Enable (OE) is the output control and should be used to “0s” can be presented in the data word. A “0” cannot be changed
gate data to the output pins, independent of device selection. The to a “1” once the bit has been programmed.
programming pin (PGM) should be at VIH except during program-
ming. Assuming that addresses are stable, address access time The NMC27C64 is in the programming mode when the VPP power
(tACC) is equal to the delay from CE to output (tCE). Data is available supply is at 12.75V and OE is at VIH. It is required that at least a
at the outputs tOE after the falling edge of OE , assuming that CE 0.1 µF capacitor be placed across VPP, VCC to ground to suppress
has been low and addresses have been stable for at least tACC – spurious voltage transients which may damage the device. The
tOE. data to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data inputs
The sense amps are clocked for fast access time. VCC should are TTL.
therefore be maintained at operating voltage during read and
verify. If VCC temporarily drops below the spec. voltage (but not to For programming, CE should be kept TTL low at all times while VPP
ground) an address transition must be performed after the drop to is kept at 12.75V.
insure proper output data. When the address and data are stable, an active low, TTL program
pulse is applied to the PGM input. A program pulse must be
Standby Mode
applied at each address location to be programmed. The
The NMC27C64 has a standby mode which reduces the active NMC27C64 is programmed with the Fast Programming Algorithm
power dissipation by 99%, from 55 mW to 0.55 mW. The shown in Figure 1. Each address is programmed with a series of
NMC27C64 is placed in the standby mode by applying a CMOS 100 µs pulses until it verfies good, up to a maximum of 25 pulses.
high signal to the CE input. When in standby mode, the outputs are Most memory cells will program with a single 100 µs pulse. The
in a high impedance state, independent of the OE input. NMC27C64 must not be programmed with a DC signal applied to
Output OR-Tying the PGM input.
Because NMC27C64s are usually used in larger memory arrays, Programming multiple NMC27C64s in parallel with the same data
Fairchild has provided a 2-line control function that accommo- can be easily accomplished due to the simplicity of the program-
dates this use of multiple memory connections. The 2-line control ming requirements. Like inputs of the paralleled NMC27C64s may
function allows for: be connected together when they are programmed with the same
1. the lowest possible memory power dissipation, and data. A low level TTL pulse applied to the PGM input programs the
paralleled NMC27C64s. If an application requires erasing and
2. complete assurance that output bus contention will not reprogramming, the NMC27C64Q UV erasable PROM in a win-
occur. dowed package should be used.
TABLE 1. Mode Selection

Pins CE OE PGM VPP VCC Outputs
Mode (20) (22) (27) (1) (28) (11–13, 15–19)
Read VIL VIL VIH 5V 5V DOUT
Standby VIH Don’t Care Don’t Care 5V 5V Hi-Z
Output Disable Don’t Care VIH VIH 5V 5V Hi-Z
Program VIL VIH 13V 6V DIN
Program Verify VIL VIL VIH 13V 6V DOUT
Program Inhibit VIH Don’t Care Don’t Care 13V 6V Hi-Z
NMC27C64 Rev. C
Functional Description (Continued) After programming, opaque labels should be placed over the
NMC27C64’s window to prevent unintentional erasure. Covering
Program Inhibit the window will also prevent temporary functional failure due to the
generation of photo currents.
Programming multiple NMC27C64s in parallel with different data
is also easily accomplished. Except for CE all like inputs (including The recommended erasure procedure for the NMC27C64 is
OE and PGM) of the parallel NMC27C64 may be common. A TTL exposure to short wave ultraviolet light which has a wavelength of
low level program pulse applied to an NMC27C64’s PGM input 2537 Angstroms (Å). The integrated dose (i.e., UV intensity x
with CE at VIL and VPP at 13.0V will program that NMC27C64. A exposure time) for erasure should be a minimum of 15W-sec/cm2.
TTL high level CE input inhibits the other NMC27C64s from being
programmed. The NMC27C64 should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
Program Verify should be removed before erasure.
A verify should be performed on the programmed bits to determine An erasure system should be calibrated periodically. The distance
whether they were correctly programmed. The verify may be from lamp to unit should be maintained at one inch. The erasure
performed with VPP at 13.0V. VPP must be at VCC, except during time increases as the square of the distance. (If distance is
programming and program verify. doubled the erasure time increases by a factor of 4.) Lamps lose
intensity as they age. When a lamp is changed, the distance has
MANUFACTURER’S IDENTIFICATION CODE changed or the lamp has aged, the system should be checked to
The NMC27C64 has a manufacturer’s identification code to aid in make certain full erasure is occurring. Incomplete erasure will
programming. The code, shown in Table 2, is two bytes wide and cause symptoms that can be misleading. Programmers, compo-
is stored in a ROM configuration on the chip. It identifies the nents, and even system designs have been erroneously sus-
manufacturer and the device type. The code for the NMC27C64 pected when incomplete erasure was the problem.
is “8FC2”, where “8F” designates that it is made by Fairchild
Semiconductor, and “C2” designates a 64k part.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
The code is accessed by applying 12V ± 0.5V to address pin A9.
decoupling of the devices. The supply current, ICC, has three
Addresses A1–A8, A10–A12, CE, and OE are held at VIL. Address
segments that are of interest to the system designer—the standby
A0 is held at VIL for the manufacturer’s code, and at VIH for the
current level, the active current level, and the transient current
device code. The code is read out on the 8 data pins. Proper code
peaks that are produced by voltage transitions on input pins. The
access is only guaranteed at 25°C ± 5°C.
magnitude of these transient current peaks is dependent on the
The primary purpose of the manufacturer’s identification code is output capacitance loading of the device. The associated VCC
automatic programming control. When the device is inserted in a transient voltage peaks can be suppressed by properly selected
EPROM programmer socket, the programmer reads the code and decoupling capacitors. It is recommended that at least a 0.1 µF
then automatically calls up the specific programming algorithm for ceramic capacitor be used on every device between VCC and
the part. This automatic programming control is only possible with GND. This should be a high frequency capacitor of low inherent
programmers which have the capability of reading the code. inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
ERASURE CHARACTERISTICS bulk capacitor should be located near where the power supply is
The erasure characteristics of the NMC27C64 are such that connected to the array. The purpose of the bulk capacitor is to
erasure begins to occur when exposed to light with wavelengths overcome the voltage drop caused by the inductive effects of the
shorter than approximately 4000 Angstroms (Å). It should be PC board traces.
noted that sunlight and certain types of fluorescent lamps have
wavelengths in the 3000Å – 4000Å range.
TABLE 2. Manufacturer’s Identification Code

Pins A0 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code VIL 1 0 0 0 1 1 1 1 8F
Device Code VIH 1 1 0 0 0 0 1 0 C2
NMC27C64 Rev. C
Physical Dimensions inches (millimeters) unless otherwise noted
1.260 MAX
(32.00)
24 13
R 0.025
(0.64)
0.514 - 0.526
(13.06 - 13.21)
1 12
0.270 - 0.290
R 0.030-0.055 TYP (6.88 - 7.39)
(0.76 - 1.4) UV WINDOW
0.050-0.060 TYP
(1.27 - 1.53) 0.10 0.590-0.620
Glass Sealant (2.5) (15.03 - 15.79)
MAX
0.225 0.180
MAX TYP (4.59)
(5.73)
MAX
0.125 MIN 0.020 -0.070
(3.18) (0.51 - 1.78) 90° - 100°
TYP TYP
TYP 0.008-0.015
(0.20 - 0.38)
0.090-0.110 TYP
0.060-0.100 0.015-0.021
(1.53 - 2.55) (2.29 - 2.80) (0.38 - 0.53) 0.685 +0.025
TYP TYP TYP (17.40) (0.64)
-0.060
(-1.523)
Dual-In-Line Package (Q)

Order Number NMC27C64Q
Package Number J28AQ
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.030
Max
(0.762) 0.600 - 0.620 0.062 RAD
(15.24 - 15.75) 0.510 ±0.005 (1.575)
(12.95 ±0.127)
95° ±5°
0.008-0.015 Pin #1 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.580 (0.229-0.381) IDENT
(14.73) 1.393 - 1.420
(35.38 - 36.07)
+0.025
0.625 -0.015
(15.88 +0.635
-0.381 ( 0.050
(1.270)
Typ
0.053 - 0.069
0.125-0.165
(1.346 - 1.753)
(3.175-4.191) 0.20 Min
(0.508)
88° 94°
0.108 ±0.010 Typ 0.125-0.145
0.050 ±0.015
(2.540 ±0.254) (3.175-3.583)
(1.270 ±0.381) 0.018 ±0.003
(0.457 ±0.076)
Dual-In-Line Package (N)

Order Number NMC27C64N
Package Number N28B
Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) support or system whose failure to perform can be reasonably ex-
or sustain life, and whose failure to perform, when properly pected to cause the failure of the life support device or system,
used in accordance with instructions for use provided in the or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant
injury to the user.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
NMC27C64 Rev. C
HM6264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-454B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil SOP
(foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density mounting.
Features
• High speed
Fast access time: 85/100 ns (max)
• Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Battery backup operation capability
HM6264B Series
Ordering Information
Type No. Access time Package
HM6264BLP-8L 85 ns 600-mil, 28-pin plastic DIP (DP-28)
HM6264BLP-10L 100 ns
HM6264BLSP-8L 85 ns 300-mil, 28-pin plastic DIP(DP-28N)
HM6264BLSP-10L 100 ns
HM6264BLFP-8LT 85 ns 450-mil, 28-pin plastic SOP(FP-28DA)
HM6264BLFP-10LT 100 ns
Pin Arrangement
HM6264BLP/BLSP/BLFP Series
NC 1 28 VCC
A12 2 27 WE
A7 3 26 CS2
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 OE
A2 8 21 A10
A1 9 20 CS1
A0 10 19 I/O8
I/O1 11 18 I/O7
I/O2 12 17 I/O6
I/O3 13 16 I/O5
VSS 14 15 I/O4
(Top view)
Pin Description
Pin name Function Pin name Function
A0 to A12 Address input WE Write enable
I/O1 to I/O8 Data input/output OE Output enable
CS1 Chip select 1 NC No connection
CS2 Chip select 2 VCC Power supply
VSS Ground
2
HM6264B Series
Block Diagram
A11
A8 VCC
A9 Row Memory array
A7 VSS
A12 decoder 256 × 256
A5
A6
A4
I/O1
Column I/O
Input Column decoder
data
control
I/O8
A1 A2 A0 A10 A3
CS2
Timing pulse generator
CS1
Read, Write control
WE
OE
3
HM6264B Series
Function Table
WE CS1 CS2 OE Mode VCC current I/O pin Ref. cycle
× H × × Not selected (power down) I SB , I SB1 High-Z —
× × L × Not selected (power down) I SB , I SB1 High-Z —
H L H H Output disable I CC High-Z —
H L H L Read I CC Dout Read cycle (1)–(3)
L L H H Write I CC Din Write cycle (1)
L L H L Write I CC Din Write cycle (2)
Note: ×: H or L
Absolute Maximum Ratings

Parameter Symbol Value Unit
*1
Power supply voltage VCC –0.5 to +7.0 V
*1 *2 *3
Terminal voltage VT –0.5 to V CC + 0.3 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to + 70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. Relative to VSS
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 0 0 0 V
Input high voltage VIH 2.2 — VCC + 0.3 V
*1
Input low voltage VIL –0.3 — 0.8 V
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns
4
HM6264B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)

Parameter Symbol Min Typ*1 Max Unit Test conditions
Input leakage current |ILI| — — 2 µA Vin = VSS to V CC
Output leakage current |ILO | — — 2 µA CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to V CC
Operating power supply I CCDC — 7 15 mA CS1 = VIL, CS2 = VIH, I I/O = 0 mA
current others = VIH/VIL
Average operating power I CC1 — 30 45 mA Min cycle, duty = 100%,
supply current CS1 = VIL, CS2 = VIH, I I/O = 0 mA
others = VIH/VIL
I CC2 — 3 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA
CS1 ≤ 0.2 V, CS2 ≥ VCC – 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby power supply I SB — 1 3 mA CS1 = VIH, CS2 = VIL
current
I SB1 — 2 50 µA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
Output low voltage VOL — — 0.4 V I OL = 2.1 mA
Output high voltage VOH 2.4 — — V I OH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = 25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions
*1
Input capacitance Cin — — 5 pF Vin = 0 V
*1
Input/output capacitance CI/O — — 7 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM6264B Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V

• Input and output timing reference level: 1.5 V
• Input rise and fall time: 10 ns
• Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)
Read Cycle
HM6264B-8L HM6264B-10L
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time t RC 85 — 100 — ns
Address access time t AA — 85 — 100 ns
Chip select access time CS1 t CO1 — 85 — 100 ns
CS2 t CO2 — 85 — 100 ns
Output enable to output valid t OE — 45 — 50 ns
Chip selection to output in low-Z CS1 t LZ1 10 — 10 — ns 2
CS2 t LZ2 10 — 10 — ns 2
Output enable to output in low-Z t OLZ 5 — 5 — ns 2
Chip deselection in to output in high-Z CS1 t HZ1 0 30 0 35 ns 1, 2
CS2 t HZ2 0 30 0 35 ns 1, 2
Output disable to output in high-Z t OHZ 0 30 0 35 ns 1, 2
Output hold from address change t OH 10 — 10 — ns
Notes: 1. t HZ is defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. At any given temperature and voltage condition, t HZ maximum is less than tLZ minimum both for a
given device and from device to device.
6
HM6264B Series
Read Timing Waveform (1) (WE = VIH)
tRC
Address Valid address

tAA
tCO1
CS1
tLZ1
tCO2 tHZ1
CS2 tLZ2
tOE tHZ2
tOLZ
OE
tOHZ
High Impedance
Dout Valid data
tOH
Read Timing Waveform (2) (WE = VIH, OE = VIL )

t AA
t OH
t OH
Dout Valid data
7
HM6264B Series
Read Timing Waveform (3) (WE = VIH, OE = VIL )*1
t CO1
CS1
t HZ1
t LZ1
t HZ2
CS2
t CO2
t LZ2
Dout Valid data
Note: 1. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.
8
HM6264B Series
Write Cycle
HM6264B-8L HM6264B-10L
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time t WC 85 — 100 — ns
Chip selection to end of write t CW 75 — 80 — ns 2
Address setup time t AS 0 — 0 — ns 3
Address valid to end of write t AW 75 — 80 — ns
Write pulse width t WP 55 — 60 — ns 1, 6
Write recovery time t WR 0 — 0 — ns 4
WE to output in high-Z t WHZ 0 30 0 35 ns 5
Data to write time overlap t DW 40 — 40 — ns
Data hold from write time t DH 0 — 0 — ns
Output active from end of write t OW 5 — 5 — ns
Output disable to output in high-Z t OHZ 0 30 0 35 ns 5
Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write begins at
the latest transition among CS1 going low,CS2 going high and WE going low. A write ends at
the earliest transition among CS1 going high CS2 going low and WE going high. Time tWP is
measured from the beginning of write to the end of write.
2. t CW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. t AS is measured from the address valid to the beginning of write.
4. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite
phase to the outputs must not be applied.
6. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention
t WP ≥ tWHZ max + tDW min.
9
HM6264B Series
Write Timing Waveform (1) (OE Clock)
tWC
OE tCW tWR
CS1
*1
CS2
tAW
tAS tWP
WE
tOHZ
High Impedance
Dout tDW tDH
High Impedance
Din Valid data
Note: 1. If CS1 goes low or CS2 goes high simultaneously with WE going low or after WE going low,
the outputs remain in the high impedance.state.
10
HM6264B Series
Write Timing Waveform (2) (OE Low Fixed) (OE = VIL )
tWC

tAW
tWR
tCW
CS1
*1
CS2
tWP
WE tAS tOH
tWHZ tOW
*2 *3
Dout
tDW tDH
*4
High Impedance
Din Valid data
Notes: 1. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs remain
in high impedance state.
2. Dout is the same phase of the written data in this write cycle.
3. Dout is the read data of the next address.
4. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input
signals of opposite phase to the outputs must not be applied to I/O pins.
11
HM6264B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter Symbol Min Typ*1 Max Unit Test conditions*4
VCC for data retention VDR 2.0 — — V CS1 ≥ VCC –0.2 V,
CS2 ≥ VCC –0.2 V or CS2 ≤ 0.2 V
Data retention current I CCDR — 1*1 25*2 µA VCC = 3.0 V, 0 V ≤ Vin ≤ VCC
CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V
or 0 V ≤ CS2 ≤ 0.2 V
Chip deselect to data t CDR 0 — — ns See retention waveform
retention time
Operation recovery time tR t RC*3 — — ns
Notes: 1. Reference data at Ta = 25°C.
2. 10 µA max at Ta = 0 to + 40°C.
3. t RC = read cycle time.
4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
tCDR Data retention mode tR

VCC
4.5 V
2.2 V
VDR
CS1
CS1 ≥ VCC – 0.2 V
0V
12
HM6264B Series
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
VCC Data retention mode
4.5 V
tCDR tR
CS2
VDR
0.4 V
CS2 ≤ 0.2 V
0V
13
HM6264B Series
Package Dimensions
HM6264BLP Series (DP-28)
Unit: mm
35.6
36.5 Max
28 15
14.6 Max
13.4
1 1.2 14
15.24
2.54 Min 5.70 Max

1.9 Max 0.51 Min
+ 0.11
0.25 – 0.05
2.54 ± 0.25 0.48 ± 0.10
0° – 15°
Hitachi Code DP-28
JEDEC —
EIAJ Conforms
Weight (reference value) 4.6 g
14
HM6264B Series
Package Dimensions (cont)
HM6264BLSP Series (DP-28N)
Unit: mm
36.00
37.32 Max
28 15
7.0 Max
6.60
1 14
1.30
7.62
5.08 Max
2.20 Max
2.54 Min
0.51 Min
+ 0.11
0.25 – 0.05
2.54 ± 0.25 0.48 ± 0.10
0° – 15°
Hitachi Code DP-28N
JEDEC —
EIAJ Conforms
Weight (reference value) 2.04 g
15
HM6264B Series
Package Dimensions (cont)
HM6264BLFP Series (FP-28DA)
Unit: mm
18.00
18.75 Max
28 15
8.40
3.00 Max
1 14 11.80 ± 0.30
0.15 ± 0.04
0.17 ± 0.05
1.12 Max
1.70
0° – 8°
0.15
0.20 +– 0.10
1.27
1.00 ± 0.20
0.15
0.40 ± 0.08
0.20 M
0.38 ± 0.06 Hitachi Code FP-28DA
JEDEC Conforms
Dimension including the plating thickness EIAJ Conforms
Base material dimension Weight (reference value) 0.82 g
16
HM6264B Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:

Hitachi Semiconductor Hitachi Europe GmbH Hitachi Europe Ltd. Hitachi Asia Pte. Ltd.
(America) Inc. Continental Europe Electronic Components Div. 16 Collyer Quay #20-00
2000 Sierra Point Parkway Dornacher Straße 3 Northern Europe Headquarters Hitachi Tower
Brisbane, CA. 94005-1897 D-85622 Feldkirchen Whitebrook Park Singapore 049318
USA München Lower Cookham Road Tel: 535-2100
Tel: 800-285-1601 Tel: 089-9 91 80-0 Maidenhead Fax: 535-1533
Fax:303-297-0447 Fax: 089-9 29 30-00 Berkshire SL6 8YA
United Kingdom Hitachi Asia (Hong Kong) Ltd.
Tel: 01628-585000 Unit 706, North Tower,
Fax: 01628-585160 World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
17
HM6264B Series
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Sep. 5, 1995 Initial issue I. Ogiwara K. Yoshizaki
1.0 Dec. 6, 1995 Deletion of Preliminary I. Ogiwara K. Yoshizaki
2.0 Nov. 1997 Change of Subtitle
Change of FP-28DA
18
Integrated Circuit Engineering Corporation
E/EEPROM
We’ve tried to include a broader category of products in this section this year to try to
illustrate the wide range of products available (and finding market acceptance), and the
corresponding range of technologies used. We thus have die sizes from 13 microns2 to
130 microns2, gate lengths from 0.2 micron to 1.3 micron and cell sizes from 1.4
micron2 to 117 microns2.
3-1
H O RI ZO NTAL DIM ENS IO NS ( DES IG N RULES)
E/EEPROMs

†
Table 3-1
VE RTIC AL DIM ENS IO N S
E/EEPROMs

Table 3-2
DI E MATERI ALS
Table 3-3
E/EEPROMs
Sharp LH28F032SUTD-70 Integrated Circuit Engineering Corporation
TECHNOLOGY DESCRIPTION
SHARP LH28F032SUTD-70
32Mbit CMOS FLASH EEPROM
Introduction Ref. report SCA 9708-548
These devices were packaged in 56-pin, plastic, TSOP packages. They were in fact two
16Mb dice in one package. They operate from a single 5V supply voltage (or 3.3V Vcc
and 5V Vpp), offer an access time of 70nsec, and can be user configured for x 8 or x 16
operation. Devices were date coded 9652 (week 52 of 1996).
See tables for specific dimensions and materials identification and see figures for
examples of physical structures.
Important/Unique Features
- Two 16Mb dice in one package.
- Intel type Flash EEPROM design (2 poly).
Quality
Quality of the process implementation was good. We found no items of serious concern.
In the area of layer patterning, etch definition was good and control was normal.
Alignment and registration were also good.
Technology
These devices were manufactured by a recessed oxide (LOCOS), twin-well CMOS

process in a P-epi on a P substrate. Two levels of metal and two levels of poly were
employed.
Passivation consisted of a thick layer of multi-layered glass over a thick layer of nitride.
It had not been planarized and did not use a die coat.
3-2
Two levels of metal interconnect were used. They were defined by standard dry-etch
techniques (no damascene). Metal 2 consisted of aluminum with a titanium-nitride cap
and titanium barrier. Metal 1 was aluminum with titanium-nitride cap and barrier on a
titanium adhesion layer.
Standard vias were used to connect metal 2 to metal 1, but tungsten plugs were used for
all vertical interconnects between metal 1 and silicon. Plugs were lined with titanium-
nitride liners, and covered with the titanium-nitride metal 1 barrier. The via cuts
penetrated the metal 1 cap so connection here is between the titanium metal 2 barrier
and the metal 1 aluminum underneath.
The intermetal dielectric consisted of 2 layers of silicon-dioxide (TEOS?) with a

sacrificial layer between. The sacrificial layer had been subjected to a planarizing
sputter etch but overall planarization was minimal. CMP was not used and no evidence
of an SOG was found.
Pre-metal dielectric was a single layer of reflow glass (BPSG) over deposited densified
oxides. This layer was reflowed prior to contact cuts.
Two levels of polysilicon were used. Poly 2 provided all standard gates on the die. It
was also employed for the word/program lines in the array and in a few locations to
form UPROM (?) gates (floating poly 2 on connected poly 1). Poly 1 was primarily
used for floating gates. The interpoly dielectric was an oxide-nitride-oxide (ONO).
Direct poly to diffusion (buried) contacts were not used. Oxide sidewall spacers were
present and were left in place.
Standard implanted source/drain diffusions were used. A deeper source diffusion was
present in the array for programming.
Three thin dielectric layers were employed. They were: gate oxide under poly 1, ONO
under poly 2 in the array, and gate oxide under poly 2 in the periphery.
Field oxide isolation consisted of a standard recessed oxide (LOCOS) that was
backetched to be almost planar with the silicon surface. No step in this oxide was
present at well boundaries but we believe twin-wells were used. An epi layer was also
present.
Redundancy fuses were not used.
Overall minimum feature sizes measured anywhere on these dice were the 0.75 micron
gates and 0.65 diameter contacts.
3-3
Memory Cell Structures
The Flash cell design employed two levels of poly, a deep (program) diffusion, and an
ONO for the thin dielectrics. It was noted that the thick recessed field oxide was quite
deep and in fact the process looked pretty much identical to Intel’s process. Polycide
(poly 2) formed word/program lines and used metal 2 as “piggyback” lines. Metal 1
provided the bit lines. Cell size was 3.4 microns2.
In addition to the Flash cells, two small SRAM arrays were present on the die. They
used a special 10 transistor design but standard processing.
Packaging/Assembly
The similarity to Intel’s 32Mb Flash device was present here also. As mentioned, these
devices achieved 32Mb capacity by assembling two 16Mb dice in one 56-pin plastic
TSOP package. Dice were mounted on both sides of the paddle/flag and attached with
silver epoxy.
Standard thermosonic wirebonds were made from both sides of the leadframe to the two
dice. Pads on the die had a pitch of 190 microns with 60 micron spacing, and were all
placed along two opposing sides of each die. Pads were 130 microns wide with 100
micron windows.
No die coat was present.
3-4
Die photograph of the Sharp LH28F032SUTD-70 32Mbit FLASH EEPROM. Mag. 16x.
PASSIVATION 2
PASSIVATION 1
METAL 1 glass etch,

METAL 2
Mag. 8400x
W PLUG POLY 2 GATE
PASSIVATION 2
PASSIVATION 1
METAL 2
Mag. 11,000x
POLY 2 GATES
METAL 1
P+ S/D
PASSIVATION 1
METAL 2
Mag. 13,000x
POLY 2 GATE
METAL 1
N+ S/D
SEM views illustrating general device structures.

Mag. 6500x
METAL 1
POLY
Mag. 3500x
POLY 2
POLY 2
POLY 1
DIFFUSION
Mag. 8000x
POLY 2
POLY 1
POLY 2 STRINGER
SEM views of metal interconnect and dual poly gates.

A B
BIT
C
metal 1
GND VCC
BIT
GND
VCC
9
7
1
BIT
3 5
poly 2
GND
4 6
2
BIT 10
8
GND
WORD
9 10
BIT 2 1 BIT
7 8
C D
A 3 B 4
5 6
Topological SEM views of an SRAM cell with schematic. Mag. 4400x, 0°.
PASSIVATION 1
METAL 2
POLY 2 WORD LINES

Mag. 13,000x
METAL 1 BIT LINE
N+ S/D
METAL 1 BIT LINE
POLY 2
Mag. 26,000x
POLY 1
W PLUG
N+ S/D
N+ S/D
METAL 1 METAL 1
POLY 2
PRE-METAL DIELECTRIC
Mag. 26,000x
POLY 1
SEM views of Flash EEPROM cells.

Macronix 27C8100PC-10 Integrated Circuit Engineering Corporation
MACRONIX 27C8100PC-10
8Mbit NAND CMOS EPROM (OTP)
These parts were packages in 42-pin Plastic Dual In-Line Packages (PDIPs). They were
fully functional production devices organized in a 1M x 8 design. They offer an access
time of 100nsec and static operation. They operate from a 5V power source but require
a 12.5V programming voltage. These parts were coded 9717 (week 17 of 1997).
See tables for specific dimension and materials identification and see figures for
- Relatively complex process including etch equalization patterns.
- Unique cell design using three levels of poly.
Quality
Quality of the process implementation was less than desirable. Metal thinning
consumed 100 percent of the aluminum in some areas, leaving only the barrier to
provide continuity.
In the area of layer patterning, etch definition and control were both good.
Technology
These devices were manufactured by an N-well, recessed oxidation CMOS process on a

P substrate (no epi). A single level of metal and three levels of poly were used.
Passivation consisted of four layers of nitride and glass and was planarized using a spin-
on-glass (SOG) between the two nitride layers. Passivation layer 4 was a thick silicon-
dioxide. Layers 3 and 1 appeared to be nitrides, while layer 2 was the SOG.
3-5
They incorporated a single level of metal defined by a standard dry-etch technique. The
metal consisted of aluminum with a titanium-nitride cap and barrier. A thin titanium
adhesion layer was used under the barrier. Of special note was the presence of etch
equalization patterns in the open areas on the die.
Standard contacts (no plugs) were used for all vertical interconnect.
oxides. This layer was reflowed after contact cuts to provide the planarization. This
was adequate in most areas except at a few contacts to polycide (near the edge of the
polycide), where excessive metal thinning was present.
Three levels of polysilicon were used. Poly 3 (poly with tungsten silicide) was used to
form all peripheral gates and the program lines in the EPROM cell array. All gates used
oxide sidewall spacers that were left in place. Poly 1 and 2 (no silicide) were used
exclusively in the memory cells to form the floating gates (see below).
Standard implanted source/drain diffusions were used in the peripheral circuits. Lighter
implants were employed in the array. Salicide was not used.
Interpoly and buried contacts were used only in the cell array but there they were
present between poly 2 and poly 1 and between polycide (poly 3) and poly 1 (see
below).
Two thin oxide and one oxide-nitride dielectrics were used. One gate oxide under poly
1 in the memory array, one gate oxide under all gates in the peripheral circuits, and an
oxide-nitride dielectric between poly 3 and poly 2 in the array.
Redundancy fuses were employed and used polycide (poly 3). Cutouts in the
passivation were present and several fuses had been activated.
Overall minimum feature size measured anywhere on these dice was the 0.6 micron poly
3, and poly 2 on poly 1 memory cell gates.
Memory cells employed a unique stacked EPROM design. Metal was used for the dual
bit lines and GND. Poly 1 was used as part of the floating gates and for the control
gates. At control gates polycide 3 contacted poly 1 directly (through poly 2?) thus
guarantying identical gate oxide at these gates as in the NAND cells where pieces of
poly 2 (floating gates) were laid directly on small squares of poly 1 which were laid on
the actual gate oxide. The resulting cell size was 2.76 microns2. This is quite small for
a complex cell such as this.
3-6
Packaging/Assembly
As mentioned, the parts were packages in 42-pin Plastic Dual In-Line Packages (PDIPs).
The die was mounted to the paddle/flag with silver epoxy die attach.
Standard thermosonic wirebonding was employed using gold wire. Wirebond pads on
the die had a pitch of 120 microns with 20 micron spacing. Pads were 100 microns
wide with 90 micron windows.
3-7
Die photograph of the Macronix 27C8100PC-10, 8Mbit EPROM. Mag. 25x.

METAL
Mag. 4200x
PASSIVATION 4
SOG
POLY 3 GATE
METAL Mag. 6500x
LOCOS
N+ S/D
SOG
METAL
Mag. 26,000x
100% THINNING
POLY 3
LOCOS
SEM views illustrating general structures.

POLY 3
Mag. 4000x
POLY 3 GATE Mag. 52,000x
N+ S/D
N+ S/D
GATE OXIDE
SHALLOW S/D
DENSIFIED OXIDE
POLY 3 GATE
Mag. 52,000x
P+ S/D P+ S/D
GATE OXIDE
SEM views of poly 3 gates.

POLY 2
Mag. 20,000x
POLY 1/POLY 2
FLOATING GATE
PASSIVATION 4
METAL BIT LINES
POLY 3 PROGRAM LINE

Mag. 13,000x
N+
POLY 3 PROGRAM LINE
Mag. 26,000x
N+ S/D
POLY 2
GATE OXIDE
SEM views of the NAND EPROM cells.

PASSIVATION 4
METAL BIT LINE Mag. 6500x
POLY 3 CONTROL GATE
Mag. 52,000x
POLY 3 CONTROL GATE
(POLY 1
REMNANT)
N+ S/D N+ S/D
GATE OXIDE
INTERPOLY DIELECTRIC
POLY 3 Mag. 52,000x
POLY 1/POLY 2 FLOATING GATE

GATE OXIDE
SEM section views of the NAND EPROM cells.

Toshiba TC58A040F Integrated Circuit Engineering Corporation
TOSHIBA TC58A040F
4Mbit CMOS FLASH AUDIO NAND EEPROM
This part was packaged in a 28-pin plastic Thin Small Outline Package (TSOP). It was
a fully functional production part. It is a serial audio device capable of storing up to 15
minutes of audio data. It is organized as 4Mb x 1 with 4Kbyte block size. It operates
from a single 5V power source. The package was date coded 9610 (week 10 of 1996).
examples of physical features.
- Unusual contact structures.
- National Semiconductor mask set.
- Large percentage of die area devoted to logic circuitry.
Quality
Quality of the process implementation was poor due to excessive metal thinning at
contacts where aluminum thinning greater that 95 percent was noted.
Technology
These devices were manufactured by a twin-well, recessed oxidation CMOS process

employing a P substrate (no epi), one level of metal, and three levels of poly.
Passivation consisted of a layer of nitride over a layer of glass. It was not planarized
and varied greatly in thickness due to the large metal steps. The first layer had large
voids due to cusping at these locations. It was not covered by a die coat.
3-8
The single level of metal interconnect was defined by a standard dry-etch technique (no
damascene) and consisted of aluminum with a titanium-nitride barrier (no cap was
visible). It should be noted that poly 3 (tungsten polycide) functioned as a metal
interconnect.
Standard contacts were employed throughout (no plugs), and represent the primary
cause for the quality concern noted. This device used some unique contact structures
(see photos). Contact cuts are in some cases made to cover both poly 3 and poly 2 so
that metal contacts both. Typically the metal is incapable of covering these steps, but
adequate metal surround of the contacts should prevent problems in these areas.
Pre-metal dielectric 2 (between metal and poly 3) appeared to be a layer of BPSG

reflow glass and was used for planarization. A first thick layer of BPSG reflow glass
(pre-metal dielectric 1) was used for planarization under poly 3. No spin-on-glass
(SOG) was used anywhere. Reflow was done prior to contact patterning.
Three levels of polysilicon were used. Polycide 3 ( poly and tungsten silicide) was used
as a metal substitute in both the array and peripheral circuit areas. Poly 2 formed all
gates for the peripheral circuits and the word (control) lines in the cell array. Poly 1 was
employed only in the cell array for all floating gates. A separate (third) gate oxide was
used under all poly 2 gates in the periphery. Sidewall spacers had been used throughout
and removed. Direct poly to diffusion (buried) contacts were used only in the cell array
for the polycide (poly 3) bit line contacts.
Implanted source/drain diffusions appeared normal. Diffusions were not silicided.
At least three separate gate oxides plus the interpoly ONO were used. The gate oxides
are: under poly 1 storage cells, under poly 1 edge cells (of NAND string), and under
poly 2 in the peripheral circuits.
Standard recessed field oxide isolation (LOCOS) was used and backetched normally. A
small step was present at the top of the LOCOS only so it is probable only nested wells
were used.
Poly 3 redundancy fuses were also present. Passivation cutouts were located over the
fuses. No activated fuses were found.
Overall minimum feature size measured anywhere on the die was the 0.5 micron poly 1
and 2 (gates in memory cells).
3-9
The EEPROM array used the standard dual gate stacked cell implemented in a NAND
configuration. Separate program lines were present at the edge of each word string (for
“Flash” programming?). These program gates used a continuous poly 1 line under the
poly 2 program lines, a different gate oxide under the poly 1, the same ONO between
poly 1 and 2, and wider poly 1 and 2 (gate length) than the memory gates. Polycide
(poly 3) was used for all bit lines. The memory cell gates themselves were arranged in
strings of 16 cells, use a different gate oxide than either the control cells or the
peripheral circuit gates, use an ONO between poly 1 and poly 2 and are the shortest
gates anywhere on the die. The EEPROM cell size was 2.8 micron2.
Packaging/Assembly
As mentioned, the part was packaged in a 28-pin plastic Thin Small Outline Package
(TSOP) date coded 9610. It used a hollow center leadframe paddle/flag, silver epoxy
die attach, and standard thermosonic wirebonding employing gold wire. Only six pins
were connected to the die!
Wirebond pads on the die had a minimum pitch of 195 microns with 95 micron spacing.
Pads were 100 microns wide with 90 micron windows.
3-10
PIN 1
Die photograph of the Toshiba TC58A040F 4Mbit NAND EEPROM. Mag. 31x.
PASSIVATION
METAL
POLY 3
Mag. 6500x
LOCOS N+
PASSIVATION
POLY 3
METAL POLY 2
Mag. 10,000x
ALUMINUM
BARRIER
THINNING POLY 2 Mag. 26,000x
N+
GATE OXIDE

ALUMINUM
Mag. 20,000x, 60°
POLY 3
BARRIER POLY 2
POLY 2
POLY 3
Mag. 14,000x, 60°
PASSIVATION 2
PASSIVATION 1
POLY 3
METAL metal-to-poly 3 and N+,

Mag. 13,000x
THINNING
N+
SEM views of metal-to-poly contacts.

Toshiba TC58A040F
EDGE CELLS
POLY 2
POLY 3 BIT LINE

CONTACTS
Mag. 15,000x, 60° Mag. 15,000x, 60°
POLY 3 BITLINE
EDGE (CONTROL) CELL

STANDARD (MEMORY) CELL

POLY 2
POLY 1
N+
EDGE CELL
DIFFERENT GATE OXIDES
Mag. 40,000x
SEM views of the memory cells.

Winbond W27E512 Integrated Circuit Engineering Corporation
WINBOND W27E512-12
512Kbit CMOS EEPROM
These devices were packaged in 28-pin Plastic Dual In-line (PDIP) packages date coded
9647. They are high speed devices organized as 64K x 8 and use 14V erase and 12V
program voltages. Operation is from a 5V power source.
- Unique two poly EEPROM cell design.
Quality
Quality of the process implementation was acceptable. We found no items of serious

concern, although metal thinned up to 90 percent at some contacts.
Technology
These devices were manufactured by a recessed field oxide, N-well CMOS process on a
P substrate (no epi). They employ a single level of metal interconnect and two levels of
poly.
Passivation consisted of a layer of nitride over a layer of silicon-dioxide and was not
planarized. It was not covered by a die coat.
The single level of metal was defined by a standard dry-etch technique (no damascene).
Metal consisted of aluminum with a titanium-nitride cap and barrier. A thin titanium
adhesion layer was present underneath the barrier.
Standard vias (not plugs) were used for all vertical interconnect.
3-11
oxides. This layer was reflowed prior to contact cuts, and provided the only
planarization. No SOG was used anywhere in the process.
Two layers of poly (no silicide) were used. Poly 2 was used to form all standard gates
on the die and word lines in the memory array. Poly 1 was very thin and used
exclusively for floating gates in the memory cells. Oxide sidewall spacers were present
and were left in place. Direct poly to diffusion (buried) contacts were not used.
Normal source/drain diffusions were implanted in peripheral circuits. Special source

and drain implants were used in the memory cells but could not be delineated well
enough to characterize. Diffusions were not silicided.
Field oxide isolation consisted of a standard recessed oxide (LOCOS)backetched

normally. No step was present at well boundaries and no other sign of the presence of
twin-wells was found. An epi layer was also not used.
Redundancy fuses were not present.
Overall minimum feature size measured anywhere on these dice was the 0.7 micron poly
2 and poly 1, and the 0.9 micron gates.
The unique (11⁄2 transistor) memory cell design consisted of poly 2 word lines and select
gates, and very thin poly 1 floating gates that appear to use Fowler-Nordheim tunneling
for programming. Metal formed the bit lines. Cell size was 7.8 microns2.
Packaging/Assembly
As mentioned, these devices were packaged in standard 28-pin through hole mounting
plastic DIPs. Silver epoxy die attach was used.
The standard thermosonic wirebonds on the die were made to pads on the die that had a
pitch of 290 microns with 150 micron spacing. Pads were 140 microns wide with 90
micron windows.
3-12
Die photograph of the Winbond W27E512 512Kbit EEPROM. Mag. 48x.

Mag. 4000x
METAL
PASSIVATION
METAL
POLY 2 Mag. 1000x
P+ S/D
PASSIVATION
METAL
Mag. 20,000x
PRE-METAL
90% THINNING DIELECTRIC
POLY 2 GATE
N+ DIFFUSION
SEM views illustrating general structure.

Mag. 6500x
POLY 2
POLY 2 Mag. 40,000x
N+ S/D N+ S/D
GATE OXIDE
PRE-METAL
DIELECTRIC
SIDEWALL
SPACER
glass etch,
Mag. 40,000x
POLY 2
SEM views of typical gates.

POLY 1
POLY 2
Mag. 13,000x, 0°
POLY 2
POLY 1
Mag. 20,000x, 60°
METAL BIT LINES
PRE-METAL
DIELECTRIC
Mag. 26,000x
POLY 2
N+
POLY 1
SEM views of the EEPROM cell design.

SGS-Thomson M28C64-12L Integrated Circuit Engineering Corporation
SGS-THOMSON M28C64-12l
64Kbit CMOS EEPROM
The parts were packaged in 28-pin Plastic Dual In-line Packages (PDIPs). They were
fully functional production devices organized in an 8K x 8 parallel EEPROM design.
They offer an access time of 90nsec., at 5V (120nsec. at 3V) and software data
protection. They operate from a 5V or 3V power source. The date code could not be
determined but is assumed to be early 1997.
- Unique metal structure.
- Very large cell size (117 micron2).
Quality
Quality of the process implementation was good. We found no areas of concern.
Technology
These devices were manufactured by an N-well, recessed oxidation CMOS process on a

P substrate (no epi). Single levels of metal and poly were used.
Passivation consisted of two layers of silicon-dioxide and was not planarized, and not
covered with a die coat.
3-13
They incorporated a single level of metal defined by a standard dry-etch techniques (no
damascene). Metal consisted of aluminum with a titanium-nitride cap and titanium over
titanium-nitride on titanium barrier. The presence of the titanium layer over the
titanium-nitride barrier is somewhat unique to S/T.
Standard contacts (no plugs) were used.
Pre-metal dielectric was a single layer of reflow glass (BPSG) over densified deposited
oxides. This layer was reflowed after contact cuts, and thus provided all the
planarization needed.
A single level of polysilicon (no polycide) was used to form all gates on the die and all
the elements in the EEPROM cell array. All gates used oxide sidewall spacers that were
left in place. Buried contacts were not used, nor was any other special interconnect such
as a local interconnect.
Standard implanted source/drain diffusions were used and not silicided. Other implants
were present in the memory array (see below).
The process appears to use only two different thin oxide dielectrics. One for gate oxides
and one for the tunnel-oxide windows in the cell array.
Standard LOCOS isolation was employed and etched back normally. No step was
present, confirming the absence of twin-wells.
Redundancy fuses were also not present.
Overall minimum feature sizes measured anywhere on these dice were the 0.8 micron
contacts and 1.0 micron metal.
Memory cells consisted of a tunnel oxide (window), single poly EEPROM design.
Metal was used for the bit lines. Poly was used to form the word/select lines, tunnel
oxide devices and capacitor elements. The select gates used in the memory cells were
very large, measuring 1.9 micron long. The resulting cell size was 117 microns2, which
is the largest cell size we’ve seen for many years.
3-14
Packaging/Assembly
As mentioned, the parts were packaged in 28-pin Plastic Dual In-line Packages (PDIPs).
The die was mounted to the paddle/flag with silver epoxy die attach.
Thermosonic wirebonds were employed, using standard gold wire. Wirebond pads on
the die had a pitch of 185 microns with 75 micron spacing. Pads were 110 microns
wide with 90 micron windows.
3-15
Die photograph of the S/T M28C64-12L 64Kbit EEPROM. Mag. 34x.

Mag. 6500x
METAL
PASSIVATION
Mag. 13,000x
METAL
POLY
TiN CAP
ALUMINUM
Mag. 26,000x
TiN BARRIER
POLY
P+ DIFFUSION
SEM views of general structures.

POLY
POLY GATES
Mag. 3200x
SILICIDE
Mag. 40,000x
POLY
N+ S/D N+ S/D
GATE OXIDE
SIDEWALL SPACER
SILICIDE
glass-etch,
Mag. 40,000x
POLY
GATE OXIDE
SEM views of poly gates.

POLY
Mag. 3200x, 60°
PASSIVATION
METAL BIT LINE Mag. 6500x
WORD/SELECT CAPACITOR PLATE

TUNNEL OXIDE DEVICE
DIFFUSION
METAL
PRE-METAL DIELECTRIC POLY
Mag. 26,000x
DELINEATION ARTIFACT
TUNNEL OXIDE WINDOW
SEM views of cell structures.

NEC D23C32000Av Integrated Circuit Engineering Corporation
NEC D23C32000A
32Mbit CMOS NAND MROM
These parts were packaged in 44-pin plastic Small Outline Integrated Circuit Packages
(SOICs). They were fully functional devices, offer a 120nsec. maximum access time
and are organized as 4M x 8 or 2M x 16 (selectable) serial-parallel NAND format. They
operate from a single 5V power source. They were date coded 9644 (week 44 of 1996).
- Very small gates in the cell array (0.18µm effective channel length).
Quality
Quality of the process implementation was good, except at some metal contacts where
aluminum thinning up to 90 percent was noted.
In the area of layer patterning, etch definition and control were both normal.
Alignment and registration were good.
Technology
The devices were manufactured by a twin-well, recessed oxidation CMOS process

employing a P substrate (no epi) using one level of metal and one level of poly.
Passivation consisted of a single layer of glass that was not planarized and not covered
with a die coat.
The single level of metal was defined by a standard dry-etch technique (no damascene).
Metal consisted of aluminum with a titanium-nitride cap and barrier. A thin titanium
adhesion layer was present under the barrier.
Standard contacts were employed throughout (no plugs). Contact cuts were made after
3-16
NEC D23C32000A Integrated Circuit Engineering Corporation
pre-metal glass reflow so some steep edges were present.
Pre-metal dielectric was a BPSG reflow glass and provided the only planarization. No
spin-on-glass (SOG) was used anywhere.
A single level of polycide (poly and tungsten-silicide) was used. It formed all gates on
the die. Definition of this layer was less than perfect showing what appeared to be
evidence of standing wave patterns (see photos). Sidewall spacers had been used
throughout and left in place. Direct poly to diffusion contacts (buried contacts) were not
used.
Implanted source/drain diffusions appeared to be normal. Diffusions were not silicided.
Standard recessed field oxide isolation (LOCOS) was used and was backetched in the
normal manner. A step was present in the LOCOS confirming the presence of twin-
wells.
Redundancy fuses were not present.
Overall minimum feature size measures anywhere on these dice was the 0.2 micron poly
(gates) in the cell array.
The memory cell design used standard polycide for word lines but patterned to form 0.2
micron gates. Metal formed the bit lines connecting to the dual diffusion bit lines.
Programming is achieved by (depletion) implanted diffusions.
Packaging/Assembly
As mentioned, these parts were packaged in 44-pin plastic SOICs. They used silver
epoxy die attach, and standard thermosonic wirebonding employing gold wire.
Wirebond pads on the die had a minimum pitch of 180 microns with 70 micron spacing.
Pads were 110 microns wide with 100 micron windows.
3-17
Die photograph of the NEC D23C32000A 32Mbit MROM. Mag. 26x.

METAL
Mag. 6000x
PASSIVATION
METAL
Mag. 13,000x
POLYCIDE GATE N+ S/D
ENCAPSULANT
PASSIVATION
METAL
Mag. 26,000x
Si
POLYCIDE
LOCOS

N+
POLY GATES
Mag. 4200x
P+
STAINING
ARTIFACT
SIDE WALL
SPACER
POLYCIDE Mag. 52,000x
GATE
N+ S/D
REFLOW
GLASS Mag. 52,000x
P+ S/D
GATE OXIDE
SEM views of polycide gates.

DIFFUSION
Mag. 31,000x, 40°
LOCOS
WORD LINE
PASSIVATION
Mag. 13,000x
N+ S/D
POLYCIDE GATE
Mag. 52,000x
N+ S/D
GATE
OXIDE
SEM views of the NAND ROM cells.

M27C1001
1 Mbit (128Kb x8) UV EPROM and OTP EPROM
5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
FAST ACCESS TIME: 35ns
LOW POWER CONSUMPTION:
32 32
– Active Current 30mA at 5Mhz
– Standby Current 100µA
1 1
PROGRAMMING VOLTAGE: 12.75V ± 0.25V FDIP32W (F) PDIP32 (B)
PROGRAMMING TIME: 100µs/byte (typical)
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 05h
DESCRIPTION LCCC32W (L)

The M27C1001 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and is
organized as 131,072 words of 8 bits.
PLCC32 (C) TSOP32 (N)
The FDIP32W (window ceramic frit-seal package) 8 x 20mm
and the LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the Figure 1. Logic Diagram
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the VCC VPP
M27C1001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
17 8
A0-A16 Q0-Q7
Table 1. Signal Names
A0-A16 Address Inputs P M27C1001
Q0-Q7 Data Outputs
E
E Chip Enable
G Output Enable
G
P Program
VPP Program Supply
VSS
VCC Supply Voltage AI00710B
VSS Ground
September 1998 1/16

M27C1001
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
VPP 1 32 VCC
VCC
VPP
A12
A15
A16
A16 2 31 P
NC
P
A15 3 30 NC
A12 4 29 A14 1 32
A7 5 28 A13 A7 A14
A6 A13
A6 6 27 A8
A5 7 26 A9 A5 A8
A4 8 25 A11 A4 A9
M27C1001 A3 9 M27C1001 25 A11
A3 9 24 G
A2 G
A2 10 23 A10
A1 11 22 E A1 A10
A0 12 21 Q7 A0 E
Q0 Q7
Q0 13 20 Q6
17
Q1 14 19 Q5
Q1
Q2
VSS
Q3
Q4
Q5
Q6
Q2 15 18 Q4
VSS 16 17 Q3
AI00712
AI00711
Warning: NC = Not Connected. Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections DEVICE OPERATION

The operating modes of the M27C1001 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
A11 1 32 G
Signature.
A9 A10
Read Mode
A8 E
A13 Q7 The M27C1001 has two control functions, both of
which must be logically active in order to obtain
A14 Q6 data at the outputs. Chip Enable (E) is the power
NC Q5 control and should be used for device selection.
P Q4 Output Enable (G) is the output control and should
VCC 8 M27C1001 25 Q3 be used to gate data to the output pins, inde-
VPP 9 (Normal) 24 VSS pendent of device selection. Assuming that the
addresses are stable, the address access time
A16 Q2
(tAVQV) is equalto the delay from E to output (tELQV).
A15 Q1 Data is availableat the output after a delay of tGLQV
A12 Q0 from the falling edge of G, assuming that E has
A7 A0 been low and the addresses have been stable for
A6 A1 at least t AVQV-tGLQV.
A5 A2 Standby Mode
A4 16 17 A3 The M27C1001 has a standby mode which re-
AI01151B duces the supply current from 30mA to 100µA. The
M27C1001 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
Warning: NC = Not Connected. ance state, independent of the G input.
2/16
M27C1001
Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature (3) –40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C
TSTG Storage Temperature –65 to 150 °C
VIO (2) Input or Output Voltages (except A9) –2 to 7 V
VCC Supply Voltage –2 to 7 V
VA9 (2) A9 Voltage –2 to 13.5 V
VPP Program Supply Voltage –2 to 14 V

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes

Mode E G P A9 VPP Q0 - Q7
Read VIL VIL X X VCC or VSS Data Out
Output Disable VIL VIH X X VCC or VSS Hi-Z
Program VIL VIH VIL Pulse X VPP Data In
Verify VIL VIL VIH X VPP Data Out
Program Inhibit VIH X X X VPP Hi-Z
Standby VIH X X X VCC or VSS Hi-Z
Electronic Signature VIL VIL VIH VID VCC Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V
Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 0 0 0 0 0 1 0 1 05h
Two Line Output Control For the most efficientuse of thesetwo controllines,
BecauseEPROMs are usually used in larger mem- E should be decoded and used as the primary
ory arrays, this product features a 2 line control device selecting function, while G should be made
function which accommodates the use of multiple a common connection to all devices in the array
memory connection. The two line control function and connected to the READ line from the system
allows : control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
a. the lowest possible memory power dissipation, and that the output pins are only active when data
b. complete assurance that output bus contention is required from a particular memory device.
will not occur.
3/16
M27C1001
Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V 1N914
1.5V
0V 3.3kΩ
DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V
0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
C OUT Output Capacitance VOUT = 0V 12 pF
Note: 1. Sampled only, not 100% tested.
System Considerations control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1µF ceramic
The power switching characteristics of Advanced capacitor be used on every device between VCC
CMOS EPROMs require careful decoupling of the and VSS. This should be a high frequency capacitor
devices. The supply current, ICC, has three seg- of low inherent inductance and should be placed
ments that are of interest to the system designer: as close to the device as possible. In addition, a
the standby current level, the active current level, 4.7µF bulk electrolytic capacitor should be used
and transient current peaks that are produced by between VCC and VSS for every eight devices. The
the falling and rising edges of E. The magnitude of bulk capacitor should be located near the power
the transient current peaks is dependent on the supply connection point. The purpose of the bulk
capacitiveand inductiveloading of the deviceat the capacitor is to overcome the voltage drop caused
output. by the inductive effects of PCB traces.
The associated transient voltage peaks can be
suppressed by complying with the two line output
4/16
M27C1001
Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = VIL,
ICC Supply Current 30 mA
IOUT = 0mA, f = 5MHz
ICC1 Supply Current (Standby) TTL E = VIH 1 mA
ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA
IPP Program Current VPP = VCC 10 µA
VIL Input Low Voltage –0.3 0.8 V

(2)
VIH Input High Voltage 2 VCC + 1 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
Output High Voltage TTL IOH = –400µA 2.4 V

VOH
Output High Voltage CMOS IOH = –100µA VCC – 0.7 V
Note: 1. VCC must be applied simultaneously with or before V PP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)

M27C1001
Symbol Alt Parameter Test Condition (3) Unit
-45 -60 -70
Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 45 60 70 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 45 60 70 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 25 30 35 ns
to Output Valid
(2) Chip Enable High to

tEHQZ tDF G = VIL 0 25 0 30 0 30 ns
Output Hi-Z
(2) Output Enable High

tGHQZ tDF E = VIL 0 25 0 30 0 30 ns
to Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 ns
Output Transition
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurament conditions.
5/16
M27C1001
Table 8B. Read Mode AC Characteristics (1)

M27C1001
Symbol Alt Parameter Test Condition -12/-15/ Unit

-80 -90 -10
-20/-25
Min Max Min Max Min Max Min Max
Address Valid to
tAVQV tACC E = VIL, G = VIL 80 90 100 120 ns
Output Valid
Chip Enable Low to

tELQV tCE G = VIL 80 90 100 120 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 40 45 50 60 ns
to Output Valid
(2) Chip Enable High to

tEHQZ tDF G = VIL 0 30 0 30 0 30 0 40 ns
Output Hi-Z
(2) Output Enable High

tGHQZ tDF E = VIL 0 30 0 30 0 30 0 40 ns
to Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns
Output Transition
Figure 5. Read Mode AC Waveforms
A0-A16 VALID VALID
tAVQV tAXQX
tEHQZ
tGLQV
tELQV tGHQZ
Hi-Z
Q0-Q7
AI00713B
Programming changea ’0’ to a ’1’ is by die expositionto ultraviolet

When delivered (and after each erasure for UV light (UV EPROM). The M27C1001 is in the pro-
EPROM), all bits of the M27C1001 are in the ’1’ gramming mode when Vpp input is at 12.75V, E is
state. Data is introduced by selectively program- at VIL and P is pulsed to VIL. The data to be
ming ’0’s into the desired bit locations. Although programmed is applied to 8 bits in parallel to the
only ’0’s will be programmed,both ’1’s and ’0’s can data output pins. The levels required for the ad-
be present in the data word. The only way to dress and data inputs are TTL. VCC is specified to
be 6.25V ± 0.25V.
6/16
M27C1001
Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA
ICC Supply Current 50 mA
IPP Program Current E = VIL 50 mA
VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V
VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVPL tAS Address Valid to Program Low 2 µs
tQVPL tDS Input Valid to Program Low 2 µs
tVPHPL tVPS VPP High to Program Low 2 µs
tVCHPL tVCS VCC High to Program Low 2 µs
Chip Enable Low to
tELPL tCES 2 µs
Program Low
tPLPH tPW Program Pulse Width 95 105 µs
Program High to Input
tPHQX tDH 2 µs
Transition
Input Transition to Output
tQXGL tOES 2 µs
Enable Low
Output Enable Low to
tGLQV tOE 100 ns
Output Valid
(2) Output Enable High to

tGHQZ tDFP 0 130 ns
Output Hi-Z
Output Enable High to

tGHAX tAH 0 ns
Address Transition
7/16
M27C1001
Figure 6. Programming and Verify Modes AC Waveforms
A0-A16 VALID
tAVPL
Q0-Q7 DATA IN DATA OUT
tQVPL tPHQX
VPP
tVPHPL tGLQV tGHQZ
VCC
tVCHPL tGHAX
tELPL
P
tPLPH tQXGL
PROGRAM VERIFY
AI00714
Figure 7. Programming Flowchart PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Program-
VCC = 6.25V, VPP = 12.75V ming with PRESTO II involves in applying a se-
quence of 100µs program pulses to each byte until
a correct verify occurs (see Figure 7). During pro-
n =0 gramming and verify operation, a MARGIN MODE
circuit is automaticallyactivated in order to guaran-
P = 100µs Pulse
tee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
NO verify in MARGIN MODE provides necessary mar-
NO
gin to each programmed cell.
++n
= 25 VERIFY ++ Addr Program Inhibit
YES YES Programming of multiple M27C1001s in parallel
with different data is also easily accomplished.
Last NO
Except for E, all like inputs including G of the
FAIL Addr parallel M27C1001 may be common. A TTL low
level pulse applied to a M27C1001’s P input, with
YES E low and VPP at 12.75V, will program tha t
M27C1001. A high level E input inhibits the other
CHECK ALL BYTES
1st: VCC = 6V
M27C1001s from being programmed.
2nd: VCC = 4.2V Program Verify
A verify (read) should be performed on the pro-
AI00715C grammed bits to determine that they were correctly
programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
8/16
M27C1001
On-Board Programming ERASURE OPERATION (applies to UV EPROM)

The M27C1001 can be directly programmed in the The erasure characteristics of the M27C1001 is
application circuit. See the relevant Application such that erasure begins when the cells are ex-
Note AN620. posed to light with wavelengths shorter than ap-
proximately 4000 Å. It shouldbe notedthat sunlight
Electronic Signature and some type of fluorescent lamps have wave-
The Electronic Signature (ES) mode allows the lengthsin the 3000-4000Å range. Research shows
reading out of a binary code from an EPROM that that constant exposure to room level fluorescent
will identify its manufacturer and type. This mode lighting could erase a typical M27C1001 in about 3
is intended for use by programming equipment to years, while it would take approximately 1 week to
automatically match the device to be programmed cause erasure when exposed to direct sunlight. If
with its corresponding programmingalgorithm. The the M27C1001 is to be exposed to these types of
ES mode is functional in the 25°C ± 5°C ambient lighting conditions for extended periods of time, it
temperature range that is required when program- is suggested that opaque labels be put over the
ming the M27C1001. To activate the ES mode, the M27C1001 window to prevent unintentional era-
programmingequipment must force 11.5V to 12.5V sure. The recommended erasure procedurefor the
on address line A9 of the M27C1001, with M27C1001 is exposure to short wave ultraviolet
VPP=VCC=5V. Two identifier bytes may then be light which has a wavelength of 2537 Å. The inte-
sequenced from the device outputs by toggling grated dose (i.e. UV intensity x exposure time) for
address line A0 from VIL to VIH. All other address erasure should be a minimum of 15 W-sec/cm2.
lines must be held at VIL during Electronic Signa- The erasure time with this dosage is approximately
ture mode. 15 to 20 minutes using an ultraviolet lamp with
Byte 0 (A0=VIL) represents the manufacturer code 12000 µW/cm2 power rating. The M27C1001
and byte 1 (A0=VIH) the device identifier code. For should be placed within 2.5 cm (1 inch) of the lamp
the STMicroelectronics M27C1001, these two tubes during the erasure. Some lamps have a filter
identifier bytes are given in Table 4 and can be on their tubes which should be removed before
read-out on outputs Q0 to Q7. erasure.
9/16
M27C1001
ORDERING INFORMATION SCHEME
Example: M27C1001 -35 X C 1 TR
Speed VCC Tolerance Package Temperature Range Option

-45 (1)
45 ns X ± 5% F FDIP32W 1 0 to 70 °C X Additional
Burn-in
-60 60 ns blank ± 10% B PDIP32 3 –40 to 125 °C
TR Tape & Reel
-70 70 ns L LCCC32W 6 –40 to 85 °C
Packing
-80 80 ns C PLCC32
-90 90 ns N TSOP32
8 x 20mm
-10 100 ns
-12 120 ns
-15 150 ns
-20 200 ns
-25 250 ns
Note: 1. High Speed, see AC Characteristics section for further information
For a listof availableoptions (Speed, Package,etc...) or forfurther informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/16
M27C1001
FDIP32W - 32 pin Ceramic Frit-seal DIP, with window
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N 32 32
A2 A3 A
A1 L α
B1 B e C
eA
D2
eB
D
S
N
∅ E1 E
1
FDIPW-a
Drawing is not to scale.
11/16
M27C1001
PDIP32 - 32 lead Plastic DIP, 600 mils width
mm inches
Symb
A 5.08 0.200
A1 0.38 0.015
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N 32 32
A2 A
A1 L α
B1 B e1 C
eA
D2 eB
D
S
N
E1 E
1
PDIP
12/16
M27C1001
LCCC32W - 32 lead Leadless Ceramic Chip Carrier, square window
mm inches
Symb
A 2.28 0.090
B 0.51 0.71 0.020 0.028
D 11.23 11.63 0.442 0.458
E 13.72 14.22 0.540 0.560
e 1.27 – – 0.050 – –
e1 0.39 – 0.015 –
e2 7.62 – – 0.300 – –
e3 10.16 – – 0.400 – –
h 1.02 – – 0.040 – –
j 0.51 – – 0.020 – –
L 1.14 1.40 0.045 0.055
L1 1.96 2.36 0.077 0.093
K 10.50 10.80 0.413 0.425
K1 8.03 8.23 0.316 0.324
N 32 32
e2
D e j x 45o
N
1
L1
K E e3 e1
B
K1
A h x 45o L
LCCCW-a
13/16
M27C1001
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm inches
Symb
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
D A1
D1 A2
1 N
B1
E1 E e
Ne F D2/E2
B
0.51 (.020)
1.14 (.045)
Nd A
R CP
PLCC
14/16
M27C1001
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm inches
Symb
A 1.20 0.047
A1 0.05 0.15 0.002 0.007
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 7.90 8.10 0.311 0.319
e 0.50 - - 0.020 - -
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 32 32
CP 0.10 0.004
A2
1 N
e
B
N/2
D1 A
D CP
DIE
TSOP-a A1 α L
15/16
M27C1001
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics

 1998 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
27C128
128K (16K x 8) CMOS EPROM
FEATURES PACKAGE TYPES

• High speed performance DIP/SOIC
- 120 ns access time available VPP • 1 28 VCC
A12 2 27 PGM
• CMOS Technology for low power consumption
A7 3 26 A13
- 20 mA Active current A6 4 25 A8
- 100 µA Standby current A5 5 24 A9
27C128
A4 6 23 A11
• Factory programming available A3 7 22 OE
• Auto-insertion-compatible plastic packages A2 8 21 A10
A1 9 20 CE
• Auto ID aids automated programming A0 10 19 O7
• Separate chip enable and output enable controls O0 11 18 O6
O1 12 17 O5
• High speed “express” programming algorithm O2 13 16 O4
• Organized 16K x 8: JEDEC standard pinouts VSS 14 15 O3
- 28-pin Dual-in-line package

- 32-pin PLCC Package
- 28-pin SOIC package
- Tape and reel PLCC
A12
Vcc
PGM
A13
V PP
A7
NU
• Available for the following temperature ranges:
32
31
30
4
1
- Commercial: 0˚C to +70˚C A6 5 29 A8
- Industrial: -40˚C to +85˚C A5 6 28 A9
A4 A11
27C128
7 27
- Automotive: -40˚C to +125˚C A3 8 26 NC
A2 9 25 OE
DESCRIPTION A1
A0
10
11
24
23
A10
CE
NC 12 22 O7
The Microchip Technology Inc. 27C128 is a CMOS O0 13 21 O6
128K bit (electrically) Programmable Read Only Mem-
14
15
16
17
18
19
20
VSS
O1
O2
O3
O4
O5
NU
ory. The device is organized as 16K words by 8 bits

(16K bytes). Accessing individual bytes from an
address transition or from power-up (chip enable pin
going low) is accomplished in less than 120 ns. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and high
reliability are requirements.A complete family of pack-
ages is offered to provide the most flexibility in applica-
tions. For surface mount applications, PLCC, SOIC, or
TSOP packaging is available. Tape and reel packaging
is also available for PLCC or SOIC packages. UV eras-
able versions are also available.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.
 1996 Microchip Technology Inc. DS11003K-page 1
This document was created with FrameMaker 4 0 4

27C128
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE
1.1 Maximum Ratings* Name Function
VCC and input voltages w.r.t. VSS ........ -0.6V to +7.25V A0-A13 Address Inputs
VPP voltage w.r.t. VSS during CE Chip Enable
programming .......................................... -0.6V to +14V
OE Output Enable
Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V
Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V PGM Program Enable
Storage temperature .......................... -65˚C to +150˚C VPP Programming Voltage

Ambient temp. with power applied ..... -65˚C to +125˚C O0 - O7 Data Output
*Notice: Stresses above those listed under “Maximum Ratings” VCC +5V Power Supply
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any VSS Ground
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con- NC No Connection; No Internal Connec-
ditions for extended periods may affect device reliability. tions
NU Not Used; No External Connection Is
Allowed
TABLE 1-2: READ OPERATION DC CHARACTERISTICS
VCC = +5V (±10%)

Commercial: Tamb = 0˚C to +70˚C
Industrial: Tamb = -40˚C to +85˚C
Extended (Automotive): Tamb = -40°C to +125°C
Parameter Part* Status Symbol Min. Max. Units Conditions
Input Voltages all Logic "1" VIH 2.0 VCC+1 V

Logic "0" VIL -0.5 0.8 V
Input Leakage all — ILI -10 10 µA VIN = 0 to VCC
Output Voltages all Logic "1" VOH 2.4 V IOH = -400 µA
Logic "0" VOL 0.45 V IOL = 2.1 mA
Output Leakage all — ILO -10 10 µA VOUT = 0V to VCC
Input Capacitance all — CIN — 6 pF VIN = 0V; Tamb = 25°C;
f = 1 MHz
Output Capacitance all — COUT — 12 pF VOUT = 0V; Tamb = 25°C;
f = 1 MHz
Power Supply Current, C TTL input ICC1 — 20 mA VCC = 5.5V; VPP = VCC
Active I,E TTL input ICC2 — 25 mA f = 1 MHz;
OE = CE = VIL;
IOUT = 0 mA;
VIL = -0.1 to 0.8V;
VIH = 2.0 to VCC;
Note 1
Power Supply Current, C TTL input ICC(S) — 2 mA
Standby I, E TTL input — 3 mA
all CMOS input — 100 µA CE = VCC ± 0.2V
IPP Read Current all Read Mode IPP 100 µA VPP = 5.5V
VPP Read Voltage all Read Mode VPP VCC-0.7 VCC V
* Parts: C=Commercial Temperature Range; I, E=Industrial and Extended Temperature Ranges
Note 1: Typical active current increases .75 mA per MHz up to operating frequency for all temperature ranges.
DS11003K-page 2  1996 Microchip Technology Inc.

27C128
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: VIH = 2.4V and VIL = 0.45V; VOH = 2.0V VOL = 0.8V
Output Load: 1 TTL Load + 100 pF
Input Rise and Fall Times: 10 ns
Ambient Temperature: Commercial: Tamb = 0˚C to +70˚C
27C128-12 27C128-15 27C128-17 27C128-20 27C128-25

Parameter Sym Units Conditions
Min Max Min Max Min Max Min Max Min Max
Address to Output Delay tACC — 120 — 150 — 170 — 200 — 250 ns CE=OE=VIL
CE to Output Delay tCE — 120 — 150 — 170 — 200 — 250 ns OE=VIL
OE to Output Delay tOE — 65 — 70 — 70 — 75 — 100 ns CE=VIL
CE or OE to O/P High tOFF 0 50 0 50 0 50 0 55 0 60 ns
Impedance
Output Hold from tOH 0 — 0 — 0 — 0 — 0 — ns
Address CE or OE,
whichever occurs first
FIGURE 1-1: READ WAVEFORMS
VIH
Address Address Valid
VIL
VIH
CE
VIL
t CE(2)
VIH
OE
VIL t OFF(1,3)
t OE(2)
t OH
VOH
Outputs High Z High Z
Valid Output
O0 - O7
VOL
t ACC
Notes: (1) tOFF is specified for OE or CE, whichever occurs first

(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.

27C128
TABLE 1-4: PROGRAMMING DC CHARACTERISTICS
Ambient Temperature: Tamb = 25°C ± 5°C

VCC = 6.5V ± 0.25V, VPP = 13.0V ± 0.25V
Parameter Status Symbol Min Max. Units Conditions
Input Voltages Logic”1” VIH 2.0 VCC+1 V

Logic”0” VIL -0.1 0.8 V
Input Leakage — ILI -10 10 µA VIN = 0V to VCC
Output Voltages Logic”1” VOH 2.4 V IOH = -400 µA
Logic”0” VOL 0.45 V IOL = 2.1 mA
VCC Current, program & verify — ICC2 — 20 mA Note 1
VPP Current, program — IPP2 — 25 mA Note 1
A9 Product Identification — VH 11.5 12.5 V
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
TABLE 1-5: PROGRAMMING AC CHARACTERISTICS
for Program, Program Verify AC Testing Waveform: VIH=2.4V and VIL=0.45V; VOH=2.0V; VOL=0.8V
and Program Inhibit Modes Ambient Temperature: Tamb=25°C± 5°C
VCC= 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Parameter Symbol Min Max Units Remarks
Address Set-Up Time tAS 2 — µs

Data Set-Up Time tDS 2 — µs
Data Hold Time tDH 2 — µs
Address Hold Time tAH 0 — µs
Float Delay (2) tDF 0 130 ns
VCC Set-Up Time tVCS 2 — µs
Program Pulse Width (1) tPW 95 105 µs 100 µs typical
CE Set-Up Time tCES 2 — µs
OE Set-Up Time tOES 2 — µs
VPP Set-Up Time tVPS 2 — µs
Data Valid from OE tOE — 100 ns
Note 1: For express algorithm, initial programming width tolerance is 100 µs ±5%.
2: This parameter is only sampled and not 100% tested. Output float is defined as the point where data is no
longer driven (see timing diagram).

27C128
FIGURE 1-2: PROGRAMMING WAVEFORMS (1)
Program Verify
V IH
Address Address Stable
V IL
t AS
V IH tAH
High Z
Data Data In Stable Data Out Valid
V IL
t DS t DH tDF
(2)
13.0 V (3)
V PP
5.0 V t VPS
6.5 V (3)
V CC
5.0 V t VCS
V IH
CE
V IL
t CES
V IH
PGM
V IL
t PW tOES
V IH tOE
(2)
OE t OPW
V IL
Notes: (1) The input timing reference is 0.8V for VIL and 2.0V for VIH.
(2) t DF and tOE are characteristics of the device but must be accommodated by the programmer.
(3) Vcc = 6.5V ±0.25V, V PP = VH = 13.0V ±0.25V for Express algorithm.
TABLE 1-6: MODES
Operation Mode CE OE PGM VPP A9 O0 - O7

Read VIL VIL VIH VCC X DOUT
Program VIL VIH VIL VH X DIN
Program Verify VIL VIL VIH VH X DOUT
Program Inhibit VIH X X VH X High Z
Standby VIH X X VCC X High Z
Output Disable VIL VIH VIH VCC X High Z
Identity VIL VIL VIH VCC VH Identity Code
X = Don’t Care
1.2 Read Mode For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
(See Timing Diagrams and AC Characteristics) CE to output (tCE). Data is transferred to the output
Read Mode is accessed when after a delay from the falling edge of OE (tOE).
a) the CE pin is low to power up (enable) the chip

b) the OE pin is low to gate the data to the output
pins

27C128
1.3 Standby Mode 1.7 Verify
The standby mode is defined when the CE pin is high After the array has been programmed it must be veri-
(VIH) and a program mode is not defined. fied to ensure all the bits have been correctly pro-
When these conditions are met, the supply current will grammed. This mode is entered when all the following
drop from 20 mA to 100 µA. conditions are met:
a) VCC is at the proper level,
1.4 Output Enable b) VPP is at the proper VH level,
This feature eliminates bus contention in microproces- c) the CE line is low,
sor-based systems in which multiple devices may drive d) the PGM line is high, and
the bus. The outputs go into a high impedance state e) the OE line is low.
when the following condition is true:
• The OE and PGM pins are both high. 1.8 Inhibit
When programming multiple devices in parallel with dif-
1.5 Erase Mode (U.V. Windowed Versions)
ferent data, only CE or PGM need be under separate
Windowed products offer the capability to erase the control to each device. By pulsing the CE or PGM line
memory array. The memory matrix is erased to the all low on a particular device in conjunction with the PGM
1’s state when exposed to ultraviolet light. To ensure or CE line low, that device will be programmed; all other
complete erasure, a dose of 15 watt-second/cm2 is devices with CE or PGM held high will not be pro-
required. This means that the device window must be grammed with the data, although address and data will
placed within one inch and directly underneath an ultra- be available on their input pins (i.e., when a high level
violet lamp with a wavelength of 2537 Angstroms, is present on CE or PGM); and the device is inhibited
intensity of 12,000µW/cm2 for approximately 20 min- from programming.
utes.
1.9 Identity Mode
1.6 Programming Mode
In this mode specific data is output which identifies the
The Express Algorithm has been developed to improve manufacturer as Microchip Technology Inc. and device
the programming throughput times in a production type. This mode is entered when Pin A9 is taken to VH
environment. Up to ten 100-microsecond pulses are (11.5V to 12.5V). The CE and OE lines must be at VIL.
applied until the byte is verified. No overprogramming A0 is used to access any of the two non-erasable bytes
is required. A flowchart of the express algorithm is whose data appears on O0 through O7.
shown in Figure 1-3.
Programming takes place when:
Pin Input Output
a) VCC is brought to the proper voltage,
b) VPP is brought to the proper VH level, H
Identity 0 O O O O O O O
c) the CE pin is low, A0 e
7 6 5 4 3 2 1 0
x
d) the OE pin is high, and
e) the PGM pin is low. Manufacturer VIL 0 0 1 0 1 0 0 1 29
Device Type* VIH 1 0 0 0 0 0 1 1 83
Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set * Code subject to change
via pins A0-A13 and the data to be programmed is pre-
sented to pins O0-O7. When data and address are sta-
ble, OE is high, CE is low and a low-going pulse on the
PGM line programs that location.

27C128
FIGURE 1-3: PROGRAMMING EXPRESS ALGORITHM
Conditions:
Tamb = 25˚C ±5˚C Start
VCC = 6.5 ±0.25V
VPP = 13.0 ±0.25V
VCC = 6.5V
VPP = 13.0V
X=0
Program one 100 µs pulse

Increment X
Verify Pass
Byte
Fail
No Yes Device
X = 10 ? Failed
Last Yes
Address?
No
Increment Address
VCC = VPP = 4.5V, 5.5V
All
Device Yes bytes No
Device
Passed = original Failed
data?

27C128
27C128 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
27C128 –25 I /P
Package: L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 Mil)
SO = Plastic SOIC (300 Mil)
Temperature Blank = 0˚C to +70˚C

Range: I = -40˚C to +85˚C
E = -40˚C to +125˚C
Access 12 = 120 ns
Time: 15 = 150 ns
17 = 170 ns
20 = 200 ns
25 = 250 ns
Device: 27C128 128K (16K x 8) CMOS EPROM

27C512A

TSOP
• High speed performance
OE/VPP 1 28 A10
• CMOS Technology for low power consumption A11 2 27 CE
A9 3 26 D7
- 25 mA Active current A8 4 25 D6
- 30 µA Standby current A13

A14
5
6
24
23
D5
D4
VCC 7 22 D3
• Factory programming available 27C512A
A15 8 21 VSS
• Auto-insertion-compatible plastic packages A12 9 20 D2
A7 10 19 D1
• Auto ID aids automated programming A6 11 18 D0
A5 12 17 A0
• High speed express programming algorithm A4 13 16 A1
A3 14 15 A2
• Organized 64K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package PLCC
A12
A15
A14
A13
Vcc
NU
A7
32
31
30
A6 5 29 A8
- 28-pin SOIC package A5 6 28 A9
- 28-pin TSOP package A4 7 27 A11
27C512A
A3 8 26 NC
- 28-pin VSOP package A2 9 25 OE/VPP
A1 10 24 A10
- Tape and reel A0 11 23 CE
NC 12 22 O7
• Data Retention > 200 years O0 13 21 O6
• Available for the following temperature ranges
14
15
16
17
18
19
20
O1
O2
NU
O3
O4
O5
VSS
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C DIP/SOIC
- Automotive: -40˚C to +125˚C A15 1 28 VCC
A12 2 27 A14
DESCRIPTION A7
A6
3
4
26
25
A13
A8
A5 5 24 A9
The Microchip Technology Inc. 27C512A is a CMOS
27C512A
A4 6 23 A11
512K bit electrically Programmable Read Only Memory A3 7 22 OE/VPP
(EPROM). The device is organized into 64K words by A2 8 21 A10
A1 9 20 CE
8 bits (64K bytes). Accessing individual bytes from an A0 10 19 O7
address transition or from power-up (chip enable pin O0 11 18 O6
going low) is accomplished in less than 90 ns. This O1 12 17 O5
O2 13 16 O4
very high speed device allows the most sophisticated VSS 14 15 O3
microprocessors to run at full speed without the need
for WAIT states. CMOS design and processing enables
this part to be used in systems where reduced power
consumption and high reliability are requirements. VSOP
OE/VPP 22 21 A10
most flexibility in applications. For surface mount appli- A11 23 20 CE
cations, PLCC, VSOP, TSOP or SOIC packaging is A9 24 19 O7
A8 25 18 O6
available. Tape or reel packaging is also available for A13 26 17 O5
PLCC or SOIC packages. A14 27 16 O4
15 O3
VCC
A15
28
1
27C512A 14 VSS
A12 2 13 O2
A7 3 12 O1
A6 4 11 O0
A5 5 10 A0
A4 6 9 A1
A3 7 8 A2
 1996 Microchip Technology Inc. DS11173E-page 1

27C512A
programming ......................................... -0.6V to +14V
OE/VPP Output Enable/Programming Voltage
Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V O0 - O7 Data Output
Storage temperature .......................... -65˚C to +150˚C VCC +5V Power Supply

Ambient temp. with power applied ..... -65˚C to +125˚C VSS Ground
*Notice: Stresses above those listed under “Maximum Ratings” NC No Connection; No Internal Connec-
tion
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of NU Not Used; No External Connection is
this specification is not implied. Exposure to maximum rating con-
Allowed
ditions for extended periods may affect device reliability.
VCC = +5V ±10%

Extended (Automotive): Tamb = -40˚C to +125˚C
Parameter Part* Status Symbol Min Max Units Conditions

Logic "0" VIL -0.5 0.8 V
Input Leakage all ILI -10 10 µA VIN = 0 to VCC
Output Voltages all Logic "1" VOH 2.4 V IOH = - 400 µA
f = 1 MHz
f = 1 MHz
Power Supply Current, C TTL input ICC — 25 mA VCC = 5.5V
Active I, E TTL input ICC — 35 mA f = 1 MHz;
OE/VPP = CE = VIL;
IOUT = 0 mA;
VIL = -0.1 to 0.8V;
VIH = 2.0 to VCC;
Note 1
Power Supply Current, C TTL input ICC(S)TLL — 1 mA
Standby I, E TTL input ICC(S)TLL — 2 mA
all CMOS input ICC(S)CMOS — 30 µA CE = Vcc±0.2V
DS11173E-page 2  1996 Microchip Technology Inc.

27C512A
AC Testing Waveform: VIH = 2.4V and VIL = .45V; VOH = 2.0V and VOL = 0.8V
Extended (Automotive): Tamb = -40˚C to +125˚C
27C512-90* 27C512-10* 27C512-12 27C512-15
Min Max Min Max Min Max Min Max
Address to Output tACC — 90 — 100 — 120 — 150 ns CE = OE/
Delay VPP = VIL
CE to Output Delay tCE — 90 — 100 — 120 — 150 ns OE/VPP =
VIL
OE to Output Delay tOE — 40 — 40 — 50 — 60 ns CE = VIL
OE to Output High tOFF 0 35 0 35 0 40 0 45 ns
Impedance
Output Hold from tOH 0 — 0 — 0 — 0 — ns
Address, CE or OE/
VPP, whichever
occurred first
*90/10 AC Testing Waveforms: VIH = 3.0V and VIL = 0V; VOH = 1.5V and VOL = 1.5V
VIH
VIL
VIH
CE
VIL
t CE(2)
VIH
OE
VIL t OFF(1,3)
t OE(2)
t OH
VOH
O0 - O7 Valid Output
VOL
t ACC


27C512A

VCC = 6.5V ± 0.25V, OE/VPP = VH = 13.0V ± 0.25V
Parameter Status Symbol Min. Max. Units Conditions (See Note 1)
Input Voltages Logic “1” VIH 2.0 VCC+1 V

Logic “0” VIL -0.1 0.8 V
Output Voltages Logic “1” VOH 2.4 V IOH = -400 µA
Logic “0” VOL — 0.45 V IOL = 2.1 mA
VCC Current, program & verify — ICC2 — 35 mA CE = VIL
OE/VPP Current, program — IPP2 — 25 mA
A9 Product Identification — VID 11.5 12.5 V
Note 1: VCC must be applied simultaneously or before VPP voltage on OE/VPP and removed simultaneously or after
the VPP voltage on OE/VPP.
and Program Inhibit Modes Ambient Temperature: 25°C ±5°C
VCC = 6.5V ± 0.25V, OE/VPP = VH = 13.0V ± 0.25 V
Parameter Symbol Min. Max. Units Remarks

OE Hold Time tOEH 2 — µs
OE Recovery Time tOR 2 — µs
OE /VPP Rise Time During Programming tPRT 50 — ns
2: This parameter is only sampled and not 100% teted. Output float is defined as the point where data is no

27C512A
Program Verify
VIH
Address Stable
Address VIL
VIH t AS t AH
Data VIL Data In Stable Data Out Valid
t DF
t DS t DH (2)
6.5 V (3)
VCC 5.0V t CE
t VCS (2)
VIH t PW
CE VIL
t CES t OES t OEH
t OR
13.0 V (3)
OE/V PP t OPW
VIL
t PRT
Notes: (1) The input timing reference level is 0.8V for VIL and 2.0V for VIH.
(3) VCC = 6.5V ±0.25V, V PP = VH = 13.0V ±0.5V for express programming algorithm.
TABLE 1-6: MODES
Operation Mode CE OE/VPP A9 O0 - O7
Read VIL VIL X DOUT

Program VIL VH X DIN
Program Verify VIL VIL X DOUT
Program Inhibit VIH VH X High Z
Standby VIH X X High Z
Output Disable VIL VIH X High Z
Identity VIL VIL VH Identity Code
X = Don’t Care
Read Mode is accessed when after a delay (tOE) from the falling edge of OE/VPP.
b) the OE/VPP pin is low to gate the data to the
output pins

27C512A
1.3 Standby Mode Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set
The standby mode is entered when the CE pin is high, via pins A0 - A15 and the data to be programmed is pre-
and the program mode is not identified. sented to pins O0 - O7. When data and address are
When this conditions are met, the supply current will stable, a low going pulse on the CE line programs that
drop from 25 mA to 30 µA. location.
1.4 Output Enable OE/VPP 1.7 Verify
This multifunction pin eliminates bus connection in mul- After the array has been programmed it must be verified
tiple bus microprocessor systems and the outputs go to to ensure all the bits have been correctly programmed.
high impedance when: This mode is entered when all the following conditions
are met:
• the OE/VPP pin is high (VIH).
When a VH input is applied to this pin, it supplies the
programming voltage (VPP) to the device. b) the OE/VPP pin is low, and
c) the CE line is low.
1.5 Erase Mode (UV Windowed Versions)
1.8 Inhibit
Windowed products offer the ability to erase the mem-
ory array. The memory matrix is erased to the all “1's” When programming multiple devices in parallel with dif-
state as a result of being exposed to ultraviolet light. To ferent data, only CE needs to be under separate control
ensure complete erasure, a dose of 15 watt-second/ to each device. By pulsing the CE line low on a partic-
cm2 is required. This means that the device window ular device, that device will be programmed; all other
must be placed within one inch and directly underneath devices with CE held high will not be programmed with
an ultraviolet lamp with a wavelength of 2537 Ang- the data (although address and data will be available on
stroms, intensity of 12,000 mW/cm2 for approximately their input pins).
40 minutes.
1.9 Identity Mode
In this mode specific data is output which identifies the
The Express algorithm must be used for best results. It manufacturer as Microchip Technology Inc. and the
has been developed to improve programming yields device type. This mode is entered when Pin A9 is taken
and throughput times in a production environment. Up to VH (11.5V to 12.5V). The CE and OE/VPP lines must
to 10 100-microsecond pulses are applied until the byte be at VIL. A0 is used to access any of the two non-eras-
is verified. A flowchart of the Express algorithm is able bytes whose data appears on O0 through O7.
Programming takes place when:
Pin Input Output
b) OE/VPP is brought to the proper VH level, and H
c) CE line is low. A0 e
7 6 5 4 3 2 1 0
x
Manufacturer VIL 0 0 1 0 1 0 0 1 29
Device Type* VIH 1 0 0 0 1 1 0 0 0D
* Code subject to change

27C512A
Conditions:
Start
Tamb = 25˚C ±5˚C
VCC = 6.5 ±0.25V
VPP = 13.0 ±0.25V ADDR = First Location
VCC = 6.5V
VPP = 13.0V
X=0

Increment X
Verify Pass
Byte
Fail
No Yes Device
X = 10 ? Failed
Last Yes
Address?
No
Increment Address
VCC = VPP = 4.5V, 5.5V
All
Device Yes bytes No Device
data?

27C512A
27C512A Product Identification System
To order or to obtain information (e.g., on pricing or delivery),, please use listed part numbers, and refer to factory or listed sales offices.
27C512A – 70 I /P
Package: L = Plastic Leaded Chip Carrier
TS = Thin Small Outline Package(TSOP) 8x20mm
VS = Very Small Outline Package(VSOP) 8x13.4mm

E = -40˚C to +125˚C
Access 90 = 90 ns
Time: 10 = 100 ns
12 = 120 ns
15 = 150 ns
Device: 27C512A 512K (64K x 8) CMOS EPROM

27C256

TSOP
• High speed performance
OE 1 28 A10
- 90 ns access time available A11 2 27 CE
• CMOS Technology for low power consumption A9 3 26 D7
A8 4 25 D6
- 20 mA Active current A13 5 24 D5
A14 6 23
- 100 µA Standby current
D4
27C256
VCC 7 22 D3
• Factory programming available VPP 21
8 VSS
• Auto-insertion-compatible plastic packages A12 9 20 D2
A7 10 19 D1
• Auto ID aids automated programming A6 11 18 D0
A5 12 17 A0
• Separate chip enable and output enable controls A4 13 16 A1
• High speed “express” programming algorithm A3 14 15 A2
• Organized 32K x 8: JEDEC standard pinouts PLCC
A12
A14
A13
Vcc
VPP
NU
A7
32
31
30
- 32-pin PLCC Package A6 5 29 A8
- 28-pin SOIC package A5 6 28 A9
A4 7 27 A11
- 28-pin Thin Small Outline Package (TSOP)
27C256
A3 8 26 NC
A2 9 OE
- 28-pin Very Small Outline Package (VSOP) 25
A1 10 24 A10
- Tape and reel A0 11 23 CE
NC 12 22 O7
• Data Retention > 200 years O0 13 21 O6
• Available for the following temperature ranges:
14
15
16
17
18
19
20
O1
O2
NU
O3
O4
O5
- Commercial: 0˚C to +70˚C VSS
DIP/SOIC
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
VPP 1 28 VCC
A12 2 27 A14
DESCRIPTION A7 3 26 A13
A6 4 25 A8
A5 5 24 A9
The Microchip Technology Inc. 27C256 is a CMOS A4 6 23 A11
27C256
256K bit electrically Programmable Read Only Memory A3 7 22 OE

(EPROM). The device is organized as 32K words by 8 A2 8 21 A10
A1 9 20 CE
bits (32K bytes). Accessing individual bytes from an A0 10 19 O7
address transition or from power-up (chip enable pin O0 11 18 O6
O1
going low) is accomplished in less than 90 ns. This very 12 17 O5
O2 13 16 O4
high speed device allows the most sophisticated micro- VSS 14 15 O3
processors to run at full speed without the need for
WAIT states. CMOS design and processing enables VSOP
this part to be used in systems where reduced power
consumption and reliability are requirements. OE 22 21 A10
A11 23 20 CE
A complete family of packages is offered to provide the A9 24 19 O7
most flexibility in applications. For surface mount appli- A8 25 18 O6
A13 26 17 O5
cations, PLCC, SOIC, VSOP or TSOP packaging is
27C256
A14 27 16 O4
available. Tape and reel packaging is also available for VCC 28 15 O3
VPP 1 14 VSS
PLCC or SOIC packages.
A12 2 13 O2
A7 3 12 O1
A6 4 11 O0
A5 5 10 A0
A4 6 9 A1
A3 7 8 A2
 1996 Microchip Technology Inc. DS11001L-page 1

27C256
programming ....................................... -0.6V to +14.0V
OE Output Enable
Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V VPP Programming Voltage
Storage temperature .......................... -65˚C to +150˚C O0 - O7 Data Output

Ambient temp. with power applied ..... -65˚C to +125˚C VCC +5V Power Supply
*Notice: Stresses above those listed under “Maximum Ratings” VSS Ground
ing only and functional operation of the device at those or any NC No Connection; No Internal Connec-
other conditions above those indicated in the operation listings of tion
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability. NU Not Used; No External Connection Is
Allowed
VCC = +5V (±10%)

Parameter Part* Status Symbol Min. Max. Units Conditions

Logic "0" VIL -0.5 0.8 V
f = 1 MHz
f = 1 MHz
Power Supply Current, C TTL input ICC1 — 20 mA VCC = 5.5V; VPP = VCC
Active I,E TTL input ICC2 — 25 mA f = 1 MHz;
OE = CE = VIL;
IOUT = 0 mA;
VIL = -0.1 to 0.8V;
VIH = 2.0 to VCC;
Note 1
Standby I, E TTL input 3 mA
all CMOS input 100 µA CE = VCC ± 0.2V
DS11001L-page 2  1996 Microchip Technology Inc.

27C256
Automotive: Tamb = -40°C to +125°C
27C256-90* 27C256-10* 27C256-12 27C256-15 27C256-20

Address to Output tACC — 90 — 100 — 120 — 150 — 200 ns CE=OE =VIL

Delay
CE to Output Delay tCE — 90 — 100 — 120 — 150 — 200 ns OE = VIL
OE to Output Delay tOE — 40 — 45 — 55 — 65 — 75 ns CE = VIL
CE or OE to O/P tOFF 0 30 0 30 0 35 0 50 0 55 ns
High Impedance
Address CE or OE,
whichever goes first
* -10, -90 AC Testing Waveform: VIH = 2.4V and VIL = .45V; VOH = 1.5V and VOL = 1.5V
Output Load: 1 TTL Load + 30pF
VIH
VIL
VIH
CE
VIL
t CE(2)
VIH
OE
VIL t OFF(1,3)
t OE(2)
t OH
VOH
O0 - O7 Valid Output
VOL
t ACC


27C256

VCC = 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V

Logic”0” VIL -0.1 0.8 V
Output Voltages Logic”1” VOH 2.4 V IOH = -400 µA
Logic”0” VOL 0.45 V IOL = 2.1 mA
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
and Program Inhibit Modes Output Load: 1 TTL Load + 100pF
Ambient Temperature: Tamb=25°C ± 5°C
VCC= 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Parameter Symbol Min. Max. Units Remarks


27C256
FIGURE 1-2: PROGRAMMING WAVEFORMS
Program Verify
VIH
VIL
t AS
VIH t AH
High Z
Data Data Stable Data Out Valid
VIL
t DS t DH t DF
(1)
13.0V(2)
VPP
5.0V tVPS
6.5V(2)
VCC
5.0V tVCS
VIH
CE
VIL
t PW t OES
VIH t OE
OE (1)
VIL
Notes: (1) t DF and tOE are characteristics of the device but must be accommodated by the programmer
(2) VCC = 6.5 V ±0.25V, VPP = V H = 13.0V ±0.25V for express algorithm
TABLE 1-6: MODES
Operation Mode CE OE VPP A9 O0 - O7

Read VIL VIL VCC X DOUT
Program VIL VIH VH X DIN
Program Verify VIH VIL VH X DOUT
Program Inhibit VIH VIH VH X High Z
Standby VIH X VCC X High Z
Output Disable VIL VIH VCC X High Z
Identity VIL VIL VCC VH Identity Code
X = Don’t Care
Read Mode is accessed when: after a delay from the falling edge of OE (tOE).
pins

27C256
This feature eliminates bus contention in multiple bus c) the CE line is high, and
microprocessor systems and the outputs go to a high d) the OE line is low.
impedance when the following condition is true:
1.8 Inhibit
• The OE pin is high and the program mode is not
defined. When programming multiple devices in parallel with dif-
ferent data, only CE need be under separate control to
1.5 Erase Mode (U.V. Windowed Versions) each device. By pulsing the CE line low on a particular
Windowed products offer the ability to erase the mem- device, that device will be programmed; all other
ory array. The memory matrix is erased to the all 1’s devices with CE held high will not be programmed with
state when exposed to ultraviolet light. To ensure com- the data, although address and data will be available on
plete erasure, a dose of 15 watt-second/cm2 is their input pins.
required. This means that the device window must be
1.9 Identity Mode
placed within one inch and directly underneath an ultra-
violet lamp with a wavelength of 2537 Angstroms, In this mode specific data is output which identifies the
intensity of 12,000µW/cm2 for approximately 20 min- manufacturer as Microchip Technology Inc. and device
utes. type. This mode is entered when Pin A9 is taken to VH
(11.5V to 12.5V). The CE and OE lines must be at VIL.
1.6 Programming Mode A0 is used to access any of the two non-erasable bytes
The Express Algorithm has been developed to improve whose data appears on O0 through O7.
on the programming throughput times in a production
environment. Up to ten 100-microsecond pulses are
applied until the byte is verified. No overprogramming Pin Input Output
is required. A flowchart of the express algorithm is
shown in Figure 1-3. H
A0 e
Programming takes place when: 7 6 5 4 3 2 1 0
x
Manufacturer VIL 0 0 1 0 1 0 0 1 29
b) VPP is brought to the proper VH level, Device Type* VIH 1 0 0 0 1 1 0 0 8C
c) the OE pin is high, and * Code subject to change
d) the CE pin is low.
Since the erased state is “1” in the array, programming
ble, a low going pulse on the CE line programs that
location.

27C256
Conditions:
Start
Tamb = 25˚C ±5˚C
VCC = 6.5 ±0.25V
VPP = 13.0 ±0.25V ADDR = First Location
VCC = 6.5V
VPP = 13.0V
X=0

Increment X
Verify Pass
Byte
Fail
No Yes Device
X = 10 ? Failed
Last Yes
Address?
No
Increment Address
VCC = VPP = 4.5V, 5.5V
All
Device Yes bytes No Device
data?

27C256
To order or to obtain information (e.g., on pricing or delivery), please use listed part numbers, and refer to factory or listed sales offices.
27C256 – 90 I /TS
P = Plastic DIP (Mil 600)
SO = Plastic SOIC (Mil 300)
TS = Thin Small Outline Package (TSOP) 8x20mm
VS = Very Small Outline Package (VSOP) 8x13.4mm

E = -40˚C to +125˚C
Access 90 = 90 ns
Time: 10 = 100 ns
12 = 120 ns
15 = 150 ns
20 = 200 ns
Device 27C256 256K (32K x 8) CMOS EPROM

27C64

• High speed performance DIP/SOIC
- 120 ns access time available VPP •1 28 VCC
• CMOS Technology for low power consumption A12 2 27 PGM
A7 3 26 NC
- 20 mA Active current A6 4 25 A8
- 100 µA Standby current A5 5 24 A9
A4 6 23 A11
27C64
• Factory programming available A3 7 22 OE
• Auto-insertion-compatible plastic packages A2 8 21 A10
A1 9 20 CE
• Auto ID aids automated programming A0 10 19 O7
• Separate chip enable and output enable controls O0 11 18 O6
O1 12 17 O5
• High speed “express” programming algorithm
O2 13 16 O4
• Organized 8K x 8: JEDEC standard pinouts VSS 14 15 O3

- 28-pin SOIC package PLCC
- Tape and reel
• Available for the following temperature ranges
PGM
A12
Vcc
VPP
NU
NC
A7
- Commercial: 0˚C to +70˚C
32
31
30
- Industrial: -40˚C to +85˚C A6 5 29 A8
A5 6 28 A9
27C64
A4 A11
DESCRIPTION A3
7
8
27
26 NC
A2 9 25 OE
The Microchip Technology Inc. 27C64 is a CMOS 64K A1 10 24 A10
bit (electrically) Programmable Read Only Memory. A0 11 23 CE
NC 12 22 O7
The device is organized as 8K words by 8 bits (8K O0 13 21 O6
bytes). Accessing individual bytes from an address
14
15
16
17
18
19
20
O1
O2
NU
O3
O4
O5
VSS
transition or from power-up (chip enable pin going low)

is accomplished in less than 120 ns. CMOS design and
processing enables this part to be used in systems
where reduced power consumption and high reliability
are requirements.
most flexibility in applications. For surface mount appli-
cations, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.

27C64
VCC and input voltages w.r.t. VSS ....... -0.6V to + 7.25V A0-A12 Address Inputs
programming .......................................... -0.6V to +14V
OE Output Enable
Output voltage w.r.t. VSS ............... -0.6V to VCC +1.0V PGM Program Enable
Storage temperature .......................... -65˚C to +150˚C VPP Programming Voltage

Ambient temp. with power applied ..... -65˚C to +125˚C O0 - O7 Data Output
*Notice: Stresses above those listed under “Maximum Ratings” VCC +5V Power Supply
ing only and functional operation of the device at those or any VSS Ground
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con- NC No Connection; No Internal Connec-
ditions for extended periods may affect device reliability. tions
NU Not Used; No External Connection Is
Allowed
VCC = +5V (±10%)

Parameter Part* Status Symbol Min Max Units Conditions

Logic "0" VIL -0.5 0.8 V
f = 1 MHz
f = 1 MHz
Power Supply Current, C TTL input ICC1 — 20 mA VCC = 5.5V; VPP = VCC;
Active I TTL input ICC2 — 25 mA f = 1 MHz; OE = CE = VIL;
IOUT = 0 mA; VIL = -0.1 to 0.8V;
VIH = 2.0 to VCC; Note 1
Standby I TTL input — — 3 mA
all CMOS input — — 100 µA CE = VCC ± 0.2V
* Parts: C=Commercial Temperature Range; I =Industrial Temperature Range.

27C64
27C64-12 27C64-15 27C64-17 27C64-20 27C64-25

Address to Output Delay tACC — 120 — 150 — 170 — 200 — 250 ns CE = OE = VIL
CE to Output Delay tCE — 120 — 150 — 170 — 200 — 250 ns OE = VIL
OE to Output Delay tOE — 65 — 70 — 70 — 75 — 100 ns CE = VIL
CE or OE to O/P High tOFF 0 50 0 50 0 50 0 55 0 60 ns
Impedance
Address CE or OE,
whichever occurs first
VIH
VIL
VIH
CE
VIL
tCE(2)
VIH
OE
VIL t OFF(1,3)
t OE(2)
t OH
VOH
Valid Output
O0 - O7
VOL
t ACC
Note 1: tOFF is specified for OE or CE, whichever occurs first.

2: OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3: This parameter is sampled and is not 100% tested.

27C64

VCC = 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V

Logic”0” VIL -0.1 0.8 V
Output Voltages Logic”1” VOH 2.4 — V IOH = -400 µA
Logic”0” VOL — 0.45 V IOL = 2.1 mA
Note 1: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
and Program Inhibit Modes Ambient Temperature: Tamb=25°C ±5°C
VCC= 6.5V ± 0.25V, VPP = VH = 13.0V ± 0.25V
Parameter Symbol Min Max Units Remarks


27C64
Program Verify
VIH
VIL
tAS t AH
VIH
High Z
Data Data In Stable Data Out Valid
VIL
t DS t DH t DF
(2)
13.0 V (3)
VPP
5.0 V tVPS
6.5 V (3)
VCC
5.0 V tVCS
VIH
CE
VIL
tCES
VIH
PGM
VIL
t PW t OES
t OE
VIH
OE t OPW (2)
VIL
Notes: (1) The input timing reference is 0.8 V for V IL and 2.0 V for V IH .
(3) Vcc = 6.5 V ±0.25 V, V PP = VH = 13.0 V ±0.25 V for Express algorithm.
TABLE 1-6: MODES
Operation Mode CE OE PGM VPP A9 O0 - O7

Read VIL VIL VIH VCC X DOUT
Program VIL VIH VIL VH X DIN
Program Verify VIL VIL VIH VH X DOUT
Program Inhibit VIH X X VH X High Z
Standby VIH X X VCC X High Z
Output Disable VIL VIH VIH VCC X High Z
Identity VIL VIL VIH VCC VH Identity Code
X = Don’t Care
Read Mode is accessed when after a delay from the falling edge of OE (tOE).
pins

27C64
This feature eliminates bus contention in microproces- c) the CE line is low,
sor-based systems in which multiple devices may drive d) the PGM line is high, and
the bus. The outputs go into a high impedance state e) the OE line is low.
when the following condition is true:
• The OE and PGM pins are both high. 1.8 Inhibit
When programming multiple devices in parallel with dif-
1.5 Erase Mode (U.V. Windowed
ferent data, only CE or PGM need be under separate
Versions)
control to each device. By pulsing the CE or PGM line
Windowed products offer the capability to erase the low on a particular device in conjunction with the PGM
memory array. The memory matrix is erased to the all or CE line low, that device will be programmed; all other
1’s state when exposed to ultraviolet light. To ensure devices with CE or PGM held high will not be pro-
complete erasure, a dose of 15 watt-second/cm2 is grammed with the data, although address and data will
required. This means that the device window must be be available on their input pins (i.e., when a high level
placed within one inch and directly underneath an ultra- is present on CE or PGM); and the device is inhibited
violet lamp with a wavelength of 2537 Angstroms, from programming.
intensity of 12,000µW/cm2 for approximately 20 min-
1.9 Identity Mode
utes.
In this mode, specific data is output which identifies the
manufacturer as Microchip Technology Inc. and device
The Express Algorithm has been developed to improve type. This mode is entered when Pin A9 is taken to VH
the programming throughput times in a production (11.5V to 12.5V). The CE and OE lines must be at VIL.
environment. Up to ten 100-microsecond pulses are A0 is used to access any of the two non-erasable bytes
applied until the byte is verified. No overprogramming whose data appears on O0 through O7.
is required. A flowchart of the express algorithm is
Programming takes place when: Pin Input Output
a) VCC is brought to the proper voltage, H

b) VPP is brought to the proper VH level, A0 e
7 6 5 4 3 2 1 0
c) the CE pin is low, x
d) the OE pin is high, and Manufacturer VIL 0 0 1 0 1 0 0 1 29
e) the PGM pin is low. Device Type* VIH 0 0 0 0 0 0 1 0 02
Since the erased state is “1” in the array, programming * Code subject to change
ble, OE is high, CE is low and a low-going pulse on the
PGM line programs that location.

27C64
Conditions:
Tamb = 25˚C ±5˚C
Start
VCC = 6.5 ±0.25V
VPP = 13.0 ±0.25V
VCC = 6.5V
VPP = 13.0V
X=0

Increment X
Verify Pass
Byte
Fail
No Yes Device
X = 10 ? Failed
Last Yes
Address?
No
Increment Address
VCC = VPP = 4.5V, 5.5V
All
Device Yes bytes No
Device
data?

27C64
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
27C64 – 25 I /P
Range: I = –40˚C to +85˚C
Access 12 = 120 ns
Time: 15 = 150 ns
17 = 170 ns
20 = 200 ns
25 = 250 ns
Device: 27C64 64K (8K x 8) CMOS EPROM

EPROMS Progr

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Instructions for Programming TUTOR EPROMs

The procedure for preparing the chips is as follows:

4. Select the 12.5 Volt level.

CEG 453/653 EPROM Handout 1/3

HEX 00 04 00 81 from ROM0

The reset vectors are SP = $0000 0444

SIGNAL LEAD COLOR SIGNAL LEAD COLOR

CEG 453/653 EPROM Handout 2/3

•= Vpp: Programming Voltage. Connect to Vcc for reading

CEG 453/653 EPROM Handout 3/3

© 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

A15 VPP VPP VPP 1 28 VCC VCC VCC VCC

Commercial Temperature Range VCC = 5V ±10%

Extended Temp Range (-40°C to +85°C) VCC = 5V ±10%

Temperature Under Bias -55°C to +125°C Lead Temperature

Capacitance TA = +25˚C, f = 1 MHz (Note 2) NMC27C64N

AC Waveforms (Note 6) (Note 9)

VPP 13.0V t VPS

ADDR = First Location

Program one 100 µs Pulse

Fail Verify Verify Fail Device

1st VCC = VPP =5.5V Fail Device

TABLE 1. Mode Selection

TABLE 2. Manufacturer’s Identification Code

Dual-In-Line Package (Q)

Dual-In-Line Package (N)

Life Support Policy

Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor

Absolute Maximum Ratings

Recommended DC Operating Conditions (Ta = 0 to +70°C)

DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)

Capacitance (Ta = 25°C, f = 1.0 MHz)

AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)

• Input pulse levels: 0.8 V to 2.4 V

Read Timing Waveform (1) (WE = VIH)

Address Valid address

Read Timing Waveform (2) (WE = VIH, OE = VIL )

Address Valid address

Dout Valid data

Read Timing Waveform (3) (WE = VIH, OE = VIL )*1

Dout Valid data

Write Timing Waveform (1) (OE Clock)

Address Valid address

Write Timing Waveform (2) (OE Low Fixed) (OE = VIL )

Address Valid address

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)

tCDR Data retention mode tR

VCC Data retention mode

HM6264BLP Series (DP-28)

2.54 Min 5.70 Max

Package Dimensions (cont)

HM6264BLSP Series (DP-28N)

Package Dimensions (cont)

HM6264BLFP Series (FP-28DA)

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

For further information write to:

Integrated Circuit Engineering Corporation

Integrated Circuit Engineering Corporation

Introduction Ref. report SCA 9708-548

- Two 16Mb dice in one package.