AStudy on Design and Dynamics of Voltage

Source Inverter in Current Control Mode to

Compensate Unbalanced and Non-linear Loads
Mahesh K. Mishra, Member, IEEE, and K. Karthikeyan

consists of three H-bridge VSIs that are connected to a

Abstract--In this paper, a design of the voltage source inverter common dc storage capacitor. Each VSI is connected to the
(VSI) in a hysteresis band current control mode is presented. A power network at the PCC through an isolation transformer.
proper selection of VSI parameters is necessary to track the The six output terminals of the transformer are connected in
desired reference currents at the point of the common coupling
to compensate unbalanced and non-linear loads. In this paper,
star. Also these six terminals can be connected in delta to
the authors carry out a detailed study on the design parameters compensate a delta connected load. In this case, each
and dynamics of the VSI while tracking a reference compensator transformer is connected in parallel with the corresponding
current. A simulation of three-phase, four-wire compensated load [4]. The purpose of these transformers is to provide
system is carried out using PSCAD 4.2.0 to verify the proposed isolation between the inverter legs and to prevent the dc
design methods. storage capacitor from being shorted by switches in different
inverter legs. This topology however is not suitable for
Index Terms--Active power filter, design, dynamics, hysteresis
band, interface inductance, power quality, switching frequency, compensation of load current containing dc components
in
voltage source inverter. addition to ac components due to the presence of isolation
transformers.
I. INTRODUCTION A three-phase, three-leg topology is shown in Fig. l(b). It
T HE parameters and the dynamic performance of the VSI
has six switches and a single dc storage capacitor. If we use
in current tracking mode play an important role in this topology, the zero sequence currents in the load cannot be
compensating unbalanced and non-linear load currents. The compensated and hence the zero sequence currents flow in the
important parameters of VSIs are the level of dc link voltage, neutral wire (N-n) between the system and load. The zero
value of dc storage capacitor, value of interface inductor and sequence current thus returns to the ac distribution system. In
hysteresis band. A proper selection of VSI parameters plays a addition, if the load is non-linear and contains harmonics, then
crucial role in the operation of active power filter. The VSI is these harmonics also enter the ac system, thus degrading the
generally operated in hysteresis band current control mode to power quality. In this topology, the generation of the three
track desired reference current at the point of common compensator currents is not independent because ifa±+ib+ifc=0.
coupling (PCC). Hence this scheme is not suitable for three-phase, four-wire
Before we go into the design details of the VSIs, it is distribution system with loads containing zero sequence
necessary to have a look at some commonly used topologies currents.
[1]-[9]. These are illustrated in Fig. 1(a)-(e). The inductance Lf Three-phase, four-leg and single capacitor inverter
in these figures represents the net inductance of the isolation topology shown in Fig. l(c) is suitable for the elimination of
transformer and/or additional external interface inductance. dc as well zero sequence component from the source current,
The switching losses of the inverter and the copper losses of if the load current contains dc components [5]. Three of its
the isolation transformer and/or external interface inductance legs are connected to three phases and the fourth leg is
are represented by a resistance Rf. The iron losses of the connected to the load and supply neutral through an interface
transformer are neglected. Each of the switches shown in Fig reactance. The reference current for the fourth leg is the
1(a)-(e) has an IGBT and an anti- parallel freewheeling diode. negative sum of three-phase load currents. This nullifies the
Fig. 1(a) illustrates the H-bridge inverter topology. It effect of dc component in load current. To maintain adequate
charge in the dc storage capacitor, a proportional integral (PI)
controller is used to regulate the flow of real power from the
Mahesh K. Mishra is with the Department of Electrical Engineering,
Indian Institute of Technology Madras, Chennai, India. (e-mail: source to compensator. When the compensator is working,
mahesh 0ee.iitm.ac.in). zero sequence current containing switching frequency and
K. Karthikeyan is a Ph.D scholar in Department of Electrical Engineering, harmonics is routed to path n-n'. Using fourth leg of inverter,
Indian Institute of Technology Madras, Chennai, India. (e-mail: the negative of zero sequence current (-ia) is tracked.
karthikeyan oee.iitm.ac.in).
Certainly it needs a higher bandwidth VSI to track the
0-7803-9771-1/06/$20.00 2006 IEEE. reference neutral current as it contains harmonics due to non-
linear loads. This increases the switching losses. If this current sa sa
is not tracked properly, it will leave high switching frequency
current components in the N-n path, which is not desirable.
Also this control algorithm is quite complicated as it requires v
coordination between the switches in the fourth (neutral) leg
and those in other three legs. f
Lf L i.
Fig. l(d) shows a neutral-clamped inverter VSI topology. R Rf -
It consists of six IGBT switches and two identical dc storage
capacitors. This topology is well equipped to compensate dc
components of the load, but due to the presence of dc n

components in VSIs, the two dc capacitors are charged to

]
different voltages. The total voltage of dc capacitors however iverter
is maintained constant by using a separate PI control loop. It
is not only the dc current in load which can make drift in the (c)
dc capacitor voltages from the reference value, but also the Vsa PCC 'la
unequal capacitance leakage currents, unequal delays in the p-

semiconductor devices, asymmetrical charging of the sb n

capacitors during transients and due to measurement and V
signal conditioning circuits [6]-[7], [10].
To overcome the above problem, a neutral clamped AL
inverter-chopper VSI topology is proposed in [8]-[9] as 'fa 'A lfc
depicted in Fig. 1(e). The function of the chopper is to transfer +
Rf Rf
3
energy between the two dc capacitors so as to make their ' \ \'9'0z
voltages close to the reference value. The chopper circuit a Lf f
requires an additional control hence increases the control n' b c
complexity. +

C2 - -
r Isa","^PCC lla | (d)

LOAD Fig. 1. VSI topologies (a) H-bridge VSItoporb |lbe

V ) srcl Vi Chopper
Ic 1i1
1i1lilvslsI I
(a)~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s 4, -v~~~~~~~~~~--------I&--------------iaTx'
il,

*inverter neutral clape VSI.R

inverte nea c dV

JatiJb+ 1~~~~n all above VSI topologies, there are some common
|rl
H|rl ~~~~~~parameters which must be carefully selected to provide
CdS t\t\ t\
?nl
1 1 ~~~~~~satisfactory
~~~~~~These
performance while tracking reference currents.
parameters are the dc link voltage dc capacitor (Vdc),
T- 2 2
1 44
2
4
~~~~~~~~(Cdt),
interface inductance (L1), hysteresis band (h) and
~~~~~~~~~switching frequency (fsw). Although it is possible to select
these parameters of the VSI circuit by trial and error, there is a
(b) need for a systematic study and investigation for the selection
of these parameters considering the various constraints in the
system, to ensure the faithful tracking of the given reference
compensator currents. This paper focuses on the above
described issues.
II. SWITCHING DYNAMICS OF VSI
Before we discuss the design of the VSI, it is necessary to
have an understanding of the switching dynamics of the VSI
while it tracks the given reference currents. Here, to make the
analysis simple, a three-phase H-bridge VSI topology is
chosen. Since for a three-phase four-wire system, each phase
is independent of neutral, only the single-phase H-bridge
inverter supported by a dc storage capacitor is considered for
analysis. The circuit for the single phase VSI is shown in Fig.
2 (a). The switching dynamics for other topologies given in
Section-I can be understood in a similar way. In Fig. 2(a), an
arbitrary reference filter current is shown by dashed curve.
The upper and lower limits of the reference currents are
created by adding and subtracting hysteresis band h to the
filter reference current. To track the positive ifref, at any time
tl, switches Sla and S2a are closed and S3a and S4a are opened.
This connects +Vdc to the inverter and the actual filter current
rises from (ifref- h) to (ifref + h) through ifref. Once it crosses the
limit (ifref +h), the actual current has to be brought within the
pre-defined band. To do this, the switches S3a and S4a are
closed and the switches Sla and S2a are opened. However, if
the actual current remains positive, the switches S3a and S4a
will not conduct. Hence the actual filter current flows through
diodes D4a and D3a. It is important to note that during the
negative slope of tracked current (from instant t1 to t2),
control input -Vd, is connected to the VSI through diodes D4a
and D3a and not through switches S3a and S4a.
III. DESIGN OF VSI PARAMETERS
As it has been discussed, in any one of the above
mentioned VSI topologies, the important parameters are dc
link voltage, the value of dc storage capacitor(s), the interface
inductor and the hysteresis band within which the actual
compensator current should follow the reference currents. A
systematic study on design of these parameters of a three-
phase H-bridge, VSI topology is presented in this section.
A. Selection of DC Link Voltage
Detailed simulation and experimental studies are carried
out to converge to an empirical relationship between the dc
link voltage and switching/tracking performance of the
compensator. In the simulation study, the dc link voltage is
varied from 1.3 to 2 times the peak value of the ac system
voltage. The total harmonic distortion (THD) of the
compensated source current is taken as figure of merit. The
simulation and the experimental results are tabulated in Table
I and II respectively. It is observed from the simulation and
the experimental study that when dc link voltage is
approximately equal to 1.6 times the peak ac system voltage,
with some variations, the THD is minimum. The study is
carried out for various values of interface inductance varying
from 10 mH to 40 mH. The value of dc capacitor in Fig. 2(a)
is taken as 2200 [tF. The system peak voltage (V,) is
considered as 172 volts. The ratio m (defined as VdlVm ) is
varied by changing the value of Vdc. The PI controller is used
to regulate the dc link voltage at reference value Vdcref [9].
TABLE I
SIMULATION STUDY: THD VARIATION WITH DC LINK VOLTAGE AND
INTERFACE INDUCTANCE

m
1.30 1.45 1.60 1.75 2.00
Lf (mH)
10 3.00 2.67 1.88 2.21 2.67
20 2.27 1.61 1.10 1.38 1.25
30 3.36 2.66 2.31 2.47 2.4
40 4.89 4.22 3.2 2.98 2.12
(a)
TABLE II
EXPERIMENTAL STUDY: THD VARIATION WITH DC LINK VOLTAGE AND
INTERFACE INDUCTANCE

m
1.30 1.45 1.60 1.75 2.00
Lf (mH)
10 5.35 4.87 4.43 4.41 4.17
20 5.68 5.24 4.79 5.35 4.89
30 6.53 6.74 6.06 5.87 5.36
40 6.85 7.15 6.2 6.43 6.19

(b)
Fig. 2. (a) Single phase H-bridge topology to study dynamics and performance The practical constraints imply that the dc link voltage
of VSI (b) Switching dynamics of VSI. should satisfy the following condition.
 Vm < Vd, < VCE rated (1) When Sswitch = 1, (VdC Vm sin cot) is applied to ab by
where VCE rated iS the rated value of collector to emitter voltage conducting S1- S2 or D1- D2 and non-conducting S3- S4 or
D3- D4. When Sswitch = -1, implies (- Vd, Vm sin cot) is applied
of the power switch Empirically, it can be concluded that the
to ab by conducting S3 - S4 or D3 - D4 and non-conducting
.

dc link voltage can be expressed as, S -S2 or D -D2.

VdC = m VdC = 1.6 Vm (2) From Fig 2(b), it is found that during the positive slope of
positive actual current, the input voltage to interface inductor
B. Selection of DC Storage Capacitor is (mVm Vm sin cot), where m = 1.6 and Vm is the peak of the
Once the dc link voltage is arrived as (2), the selection of system voltage. Using the Fig. 2(b), the relation for t2 on or t34
dc capacitor value is important. The dc capacitor value can be off is obtained as following [12].
selected based on the transients or voltage sag/swell occurring
in the system and its ability to regulate under this condition. - -L ~~(ifre
+ h)-(i e- h)
Let us assume that the compensator in Fig. l(a) is connected
to an X kVA system. The energy of the system in Joules per
34 off
m
-
V,Vm sinotmV, (9)

second is therefore given by Xx1000 J/s. Let us further which is simplified to

assume that, the VSI compensator deals with half (i.e. X12) I_{(ifref-ifref)+2h} Lf (10)
=~t9
and twice (i.e. 2X) kVA handling capacity under the transient
conditions for n cycles. Then the change in energy to be dealt mVomLofmsincot
by the dc capacitor is given as
AE = (2X -X n T 2) (3)
Similarly during the negative slope of the positive actual
current, the following relation is given for t2 off or t34 on
Now this change in energy (3) should be supported by the
energy of dc capacitor. Let us allow dc capacitor to change its t =
112 off :134 on
{-(ifref -Ire
f34ef )+2h}Lf (11)
voltage from 1. 4 Vdc to 1. 8 Vdc. Hence we can write, mV<(1 + sinct)
m
-Cdc[(1.8Vm ) -(1.4Vm)] =(2X-X 2)nT (4)
Table III shows the conduction details of various switching
which implies that, devices during the tracking of the reference current by the H-
bridge VSI as shown in Fig. 2(a).
C 2(2X- X /2)nT (5)
(1.8 Vm)2 (1.4 Vm)
TABLE III
CONDUCTION DETAILS OF POWER SWITCHES
For example, consider 10 kVA system, i.e. X =10 and
a
system peak voltage V,,= 325 V, n = 1/2, T= 0.02 s. The value
Positive actual current (ifact) Negative actual current (ifact)
of Cdc computed using (5) is 2218 [tF. It is also possible to
Positive slope Negative slope Positive slope Negative slope
extend this relation for compensator in dynamic voltage 112 On (or) t34 off 134 (or) t12 Off
on 112 (or) t34 off 134 (or) t12 off
on on

restorer (DVR) mode to mitigate voltage sag/swell [11]. For

ON OFF ON OFF ON OFF ON OFF
voltage sag, 1.8Vm represents the maximum allowable dc link Devices Devices Devices Devices Devices Devices Devices Devices
voltage. The term nT is replaced by Tsag and 1.4 Vm is replaced D1 -D2 S3 -S4 S1 - S2 D3 -D4
by reference dc capacitor voltage which is 1.6 Vm. The value SI - S2 S3 - S4 D3 -D4 S1 - S2 D1 -D2 S3 - S4 S3 -S4 S1 -S2
of the dc storage capacitor is given by, D3 -D4 D1 -D2 D3 -D4 D1 -D2
C 2(2X -X 2) Tsag (6)
dc (I .8 V ) 2- (1.6 Vm )2 Thus when the actual filter current is positive with the
positive slope, switches S1-S2 are ON and the other devices
Similarly to withstand voltage swell, the value of dc storage are OFF during t12 on or t34 off. Similarly the ON and OFF status
capacitor can be computed as of the switching devices can be explained with the help of the
C 2(2X-Xl2)
(1.6 V)2 (14V )2
Tsweii (7) above table using the function parameters t12 on or t34 off and
t]2 off or t340on

C. Selection ofInterfacing Inductor Consider slopes s, and S2 such that

Selection of the interface inductor is the next important if ref f ref = l
12on
step in VSI design. The proper selection of interface inductor (12)
plays a crucial role to give a satisfactory performance of the f1 ref -if ref =S2tl2off
VSI in terms of the bandwidth (switching frequency) and Then using (10), (11) and (12), ON/OFF time for the
hysteresis band enveloped over the reference quantity. In the switches SI/S2 and S3/S4 can be expressed as following.
Fig. 2(a) the supply system is assumed to be stiff and the 2hLf (13)
resistance of the interface inductance is neglected. The control tl 2 on t34 off
input voltage to track the reference current is given as mL/<1 sincot sjL
m m V.
Vab sswitch Vdc Vm sin t (8)
 2hLf value of current hysteresis band is +50O of the rated current
tl2off 34oii
and it is varied from +400 to +8%. Assuming 10 A of rated
sinct +s2Lf current, 2h = 1 A for h = +5O. The nominal switching
m mV.. frequency of IGBT is taken as 20 kHz. With these typical
It is noted that at 0=o)t, the switching frequency of the
value of m, h, andf, the interface inductor Lf is computed
inverterf, can be found as following.
using (22) and is found to be 13 mH. If the IGBT is operated
01- - f l(1+ +
S
at 10 kHz, the Lf becomes 26 mH. The interface inductance Lf
mVm tj m MV.O. m MV.. (15) is now varied from 10 mH to 30 mH and its effect on the
2hL1 (s -s )Lf switching performance is studied.
Jsw

Fig. 3(a) shows the variation of switching frequency of the

where Asw = 1T and T=t12 on+tl2 off or T= t34 on+t34 Off To find IGBT switch when m varies from 1.4 to 1.8 with variation in
out the maximum and minimum values of switching system voltage from -Vm to Vm. It is seen that for m=1.6, the
frequency, the following equality is solved. minimum and maximum values of switching frequencies are
12.1 kHz and 20 kHz respectively. For m=1.8, there is an
increase in minimum and maximum switching frequencies
2O0 sim 0 s2 f L
1 I from 15.5 to 22.4 kHz. For m=1.4, there is decrease in the
Vm mVm )= 0 minimum and maximum switching frequencies from 8.5 to
dO 2hLf K2+(S2-sl)Lf0 17.5 kHz.
mm )m The variation of switching frequency for different values
Generally the slopes of the tracking segments i.e. from of m as a function of phase angle (0) of voltage is illustrated
in Fig. 3(b). Since over a full range of phase angle
(ifref- h, t1) to (ifref + h,
t1) and (ifref + h, t1) to (i fref- h, t1 )
(i.e. 0 <0<360'), the system voltage attains zero value three
shown in Fig. 2(b) are very large as compared to s, and S2*
Therefore, s, and S2 can be approximately taken as zero except times and positive peak and negative peak each one time, the
at discontinuities. Then (16) can be simplified to switching frequency modulates from 8.5 to 22.5 kHz for
dfs, Vmsinf20 (17)
values of m varying from 1.4 to 1.8. The intersection of plate
with the switching frequency surface shows the operating
dO 4hLf switching frequencies for m=1.6.
Thus the solution of (17) can be written as following Fig. 3(c) and (d) illustrate the variation of switching
frequency of the IGBT switch as a function of hysteresis band
0 {+±n+ /forn =0,1,2 ....
(18) (h) and interface inductance (Lf) with 0. In Fig. 3(c), the
(2n +1)so / 2 hysteresis band is varied from 400 to 8% for constant value of
It can be further shown that, m=1.6. As a result of this,f, changes from 7.59 to 24.92 kHz.
The intersection of vertical plate (for h=0.5 A) with switching
surface shows the switching frequency varying from 12.15 to
a2f -2hL1 > f =
fswmax at O +=ln7f 19.94 kHz. In Fig. 3(d), Lf is varied from 10 to 30 mH, f, is
a02 plotted by changing 0 and keeping m=1.6, h=0.5 A. It is
Vm
2hL
=> fsw = f,imin at = +(2n + 1)7r / 2 evident that as Lf increases from 10 to 30 mH, thef, changes
{
from 26 to 5.28 kHz. The intersection of vertical plate with
The maximum and minimum values of switching frequency the switching surface shows range of switching frequency
can be computed for the above values of 0 from (15). These 12.19 to 20 kHz. In all these illustrations, it is observed that at
values are given as follows zero crossings of system voltages (i.e. at 0 = i nH), the
A mVm (20) switching frequency is maximum and at positive or negative
fwmax 4hL
peak of system voltages (i.e. at 0 = ± (2n+1)H / 2), the
switching frequencies are minimum for any given set of
flwmiln (1 2 (21) parameters.

Since the maximum value of switching frequency is

important for designing the interface inductor, hence the value
of Lf (in Henry) is given as,
L m VVm (22)
4 h fwmax

D. Design Example Switching Characteristics

on
Consider a three-phase system with 220 V rms phase
voltage. A typical value of m is taken as 1.6 as discussed
earlier (2), however it is varied from 1.4 to 1.8. The typical
 unbalanced R-L and three-phase diode bridge rectifier feeding
x 10 an R-L load. The compensator comprises of twelve IGBT
2.5 switches, each with anti-parallel diode, three isolation
transformers and a dc storage capacitor (Cdc). The secondaries
of the isolation transformers are joined in star and the star
point is connected to the neutral of the load (n) and source
(N). The H-bridge VSIs are connected to PCC through
0.5
interface inductors (Li). The resistance of this inductor is
1.8
400
denoted by Rf and is modeled to account total losses in the
16 5 00 inverter. The switching losses and ohmic losses in the actual
1, S
1 4 4400
0 0
compensator are denoted by PI,,,. The compensator reference
currents are extracted using theory of instantaneous
(a) symmetrical components [4]. Based on this theory, the
reference currents are given by,
x lo'
i* -isa i la v)(plavg
(Vsb
Vsa
2.5 ila
= =
+ Ploss )
'fa A

Vsbl (VSC
+plos) (23)
N + Vsa )
Ir1.5- 1fb 'lb 'sb
=
'lb
y

A
(plavg
.I 1 5-
*4-1
i* *_Vscl 7 (Vsa
i* i* _
.Vsb )(plavg + Ploss )
+
=
=
0.5 'fe 'sC ic A
1.8
360
,z1.6 180
270 where y = tan 0 <3, 0 is the desired phase angle between
90
1.4 0
<degfeS supply voltages (vsa, Vsb, vsc) and compensated source currents
(b)
0
(isa, isb, isc). The term Plavg in (23) is the dc or mean value of
the load power. It is computed using a moving average filter
that has an averaging time of half cycle or one cycle of supply
voltage waveform depending upon whether load current
25
contains odd or both odd and even harmonics. The term P/oss
2 in (23) accounts for the losses in the VSI while realizing the
N
actual compensator and is computed using PI voltage control
C,,
15
loop. It is a slow control loop which generates Ploss at every
positive zero crossing of phase-a voltage based on the
05, difference between the actual and reference voltage of the dc
08
360 capacitor.
~C\180 ee270
90
06 0
TABLE IV
h (A) 04 90 tee
SIMULATION PARAMETERS
0

(c) System Parameters Values

Frequency 50 Hz
x 104
Voltage (L-L) 400 V, rms
3 -
a Z,=40+j 18.85 Q, Zb=25+j 12.57 Q,
2.5 -
Unbalanced and non- Z,=90+j 25.13 Q
N 2 -
linear load a Three-phase full bridge diode rectifier drawing
3: 1.5 -- dc load current of 5 A
U,
I
1- -- DC storage capacitor Cd,=2200 gF
0.5
- Interface inductor Rf =0.5 Q, Lf =13 mH
0. 03

0.02 270
360 PI controller gains Kp= 10, K1 1
180
z
JabW 0.01 0
90 ees) Reference voltage Vd,,,f= 520 V
(cde9
(d) Hysteresis band ± 0.5 A

Fig. 3. Variation of switching frequencies (a) with
with m and 0 (c) with h and 0 (d) with Lf and 0.
IV. SIMULATION STUDIES
The load compensator is realized by using a H-bridge VSI
topology as shown in Fig. 1 (a). The load and the compensator
are connected at the PCC. The load consists of a three-phase
m and system voltage (b) Simulation time step 2 gs
The three-phase load consists of unbalanced impedances
and a rectifier load drawing a constant current of 5 A as given
in Table IV. These are shown in Fig. 4(a). The THD content
in these load currents are 12.21 /0, 9.17 °0 and 17.42 °0 in
phase-a, b and c respectively.
 The source currents after compensation are illustrated in
Fig. 4(b). As seen from this figure, the source currents are
balanced and sinusoidal. However the switching frequency
components are present due to VSI operation. The currents
have unity power factor relationship with respect to their
phase voltage. The THDs of compensated source currents as
shown in figure are less than 1%.
Fig 4 (c) shows the variation in switching frequencies of
the VSI for the given parameters in Table IV. The phase-a
voltage (Vsa) and compensator current (ifa) in phase-a are also
displayed to understand the variation of switching frequency
with them. From the figure, the switching frequency is found
to be varying between 11.3 kHz and 19.23 kHz. For same VSI
parameters, minimum and maximum switching frequencies (c)
computed using (20)-(21) are fmi= 12.1 kHz and frnax=20 kHz.
It is further observed that maximum and minimum switching
frequencies occur at zero crossings and peaks (positive and
negative) of the system voltage. This is as demonstrated
through Fig. 3(a)-(d) based on (15). The slight difference
between actual and computed switching frequencies is due to
the filter currents violating the hysteresis band limits within
the simulation time step. It is seen that there are drastic change
in switching frequency of the VSI due to its inability to track
the sudden changes in the reference current. Also the
formulations (15), (20)-(2 1) hold true for tracking reference
current with smooth variation.
Fig. 4 (d) shows the switching pulses and switching
frequency together. A close observation reveals that the (d)
variation in switching frequency is delayed by one switching
period. This is because the switching frequency can be Fig. 4 PSCAD simulation results (a) Load currents (b) Source currents (c)
Switching frequency variation with source voltage (d) switching frequency
calculated only at the end of one switching period. and switching pulses

V. CONCLUSION
Various topologies of VSIs from application point of view
are discussed in detail. In general for these configurations, the
proper design of VSI parameters is essential for satisfactory
performance of the compensator. The design of dc link
voltage is confirmed with simulation as well experimental
study. The analytical equations are derived to compute dc
capacitor, interface inductance, hysteresis band and switching
frequency. The simulation study for a three-phase, four-wire
compensated system is carried out with the designed
(a) parameters using PSCAD. The switching frequency variation
of the VSI is found similar to the theoretical values. The
simulation results are given to evaluate the compensator
performance.
VI. REFERENCES
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applications - a simulation study", Electric Power System Research,
Vol. 75, August 2005, pp. 161-170.
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power quality improvements," IEEE Trans. Industrial Electronics, Vol.
46, No. 5, Oct. 1998, pp. 960-971.
[3] M. El-Habrouk, M. K. Darwish, and P. Mehta, "Active power filters: a
review," IEE Proc. Electr. Power Appl., Vol. 147, No. 5, Sept. 2000, pp.
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(b)
[4] A. Ghosh and A. Joshi, "A new approach to load balancing and power
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829-836.
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VII. BIOGRAPHIES
Mahesh K. Mishra (S'2000-M'02) received his
Bachelor of Technology from College of
Technology, Patnagar, India and M.E. from
University of Roorkee, India in 1991 and 1993
respectively. In Feb. 2002, he received the Ph.D. in
Electrical Engineering from Indian Institute of
Technology, Kanpur, India. He has teaching and
research experience of about 12 years. For about 10
year he was a faculty in Electrical Engineering
Department, Visvesvaraya National Institute of
Technology, Nagpur, India. Currently he is an Assistant Professor in
Electrical Engineering Department, Indian Institute of Technology Madras,
India. His interests are in the areas of Power Distribution Systems, Power
Electronics and Control systems.
K. Karthikeyan received his Bachelor of
Engineering in Electrical and Electronics
Engineering from Syed Ammal Engineering
College-Ramanathapuram, Madurai Kamaraj
University, India, in 2002 and Master of
Engineering in power systems from College of
Engineering Guindy-Chennai, Anna University,
India in 2004. He is currently pursuing the Ph.D.
degree in the Power Systems Hardware Laboratory,
Department of Electrical Engineering, Indian
Institute of Technology Madras, India. His fields of interest include power
quality and power electronics control in power system.