Accurate Modeling of Submicron Symmetric-load Ring VCOs
M. Helena Fino*, António B. Leal **
*Department of Electrotechnical Engineering, FCT, hfino@ieee.org
** Chipidea - Microelectronica, S.A., www.chipidea.com
ABSTRACT
This paper proposes an accurate model for submicron
PMOS symmetric-load ring VCOs. The accuracy of
the model is achieved by adopting the Npower
transistor model. The explicit dependency of the VCO
model on MOS technological parameters makes it
quite robust against technological evolution. The
simplicity and efficiency of the model as well as the
accuracy of the results obtained make it suitable to be
integrated into an environment for the automatic
design of VCOs
Index Terms – Ring VCO Models, Submicron Mofet
models
I. INTRODUCTION
Voltage Controlled Oscillators (VCOs) are a key
element in PLLs. The design of VCOs is a
complex task since it involves the solution of
many design trade-offs depending on the
application of the PLL. To make things worse, the
simulation of VCOs is a very time consuming
process, because transient circuit simulations must
run long enough so that the steady state is
attained. This makes the design methodology
based on iterative simulations, usually adopted for
analog circuits, not practical for this class of
circuits. The development of efficient and reliable
VCO models is therefore a key element for the
automation of the circuit design. Besides accuracy
and simplicity, models must easily adapt to the
rapid technology evolution. Such robustness can
only be obtained if we develop models based on
transistor level technological parameters.
The quadratic Shockley’s MOSFET model has
been widely used as the basis for the analysis of
analog and digital circuits[1]. The simplicity of
the model makes it amenable to be used as a basis
for derived formulas ranging from the small signal
models of MOSFET transistors up to more
complex formulas as amplifiers gain, bandwidth,
pole zeros expressions in analog circuits. Should
we consider the digital world, we may enumerate
such derived formulas as those used for evaluating
CMOS gate delay or power estimation.
Unfortunately, as the sizes of MOSFET
transistors scale down, the quadratic model is no
longer applicable, for new physical effects such as
the velocity saturation and mobility degradation,
among others, must be accounted for. To
overcome the inaccuracy of Shockley’s MOSFET
model when applied to submicron circuits,
Sakurai’s Npower model was proposed [2]. This
model has been successfully used in the derivation
of analytical expressions for evaluating delay and
power dissipation in submicron CMOS gates [3-
5].
The previously proposed models for the ring
VCOs considered in this paper, although quite
simple, turn out to be rather innacurate when
applied to submicron technologies. In this paper
we propose de adoption of the Npower MOS
model as a basis for deriving ring VCO models.
Besides this introduction, this paper comprises
seven additional sections. In Section II a brief
description of Sakurai’s model is presented. In
Section III we present a brief description of a
Python script, we have developed for evaluating
Npower parameters for a given technology. In
Section IV ring VCOs are introduced. Section V
describes previously proposed models and in
Section VI we apply the Npower MOS model to
deriving the VCO model and we note some
limitations of the model proposed. In Section VII
a working example is presented. Section VIII is
dedicated to conclusions
II. MOSFET MODELING FOR SUBMICRON
CIRCUITS
In order to accurately characterize short-
channel circuits, Sakurai proposed the Npower
model where the MOS transistor behavior is
described by equations 1 trough 6.
VTh = VT 0 + γ ( 2.φ F − V BS − 2.φ F ) (1)
V D SAT = K .(VGS − VTh )m (2)
I D SAT = W .B.(VGS − VTh )n (3)
Leff
λ = λ0 − λ1.VBS (4)
ID = I D SAT .(1 + λ .VDS ) ⇐ VDS ≥ VDSAT (5)
 VDS V characteristics obtained with the model, over the
I D = I D SAT . 2 − . DS ⇐ VDS < VDSAT (6)
VDSAT VDSAT
For practical use on circuits employing current
technologies, several points should be noted:
− VBS plays an important role in circuit
characterization.
− The border between Saturation and Triode is no
longer given by the simple expression
VGS − VTh but depends also on model parameters,
characteristics obtained with Hspice.
For illustration purposes we will consider the
case for obtaining MOS parameters needed for the
model of the VCO to be shown in the application
example, in Section VII. There we consider a
VCO comprising 1.8V SMIC018 transistors with
sizes in table 1.
TABLE 1
TRANSISTOR SIZES FOR THE APPLICATION EXAMPLE

i.e., K and m. Switch (Nmos) Load (Pmos) Bias (Nmos)

− The dependency of Id on Vgs is no longer W = 50µ W = 5µ W = 30µ
L .66 L .5 µ L 2µ
quadratic. The power is n as stated in eq. (3). This
has severe implications not only in the static The parameters obtained for the VCO Load
behavior of circuits but in the dynamic behavior as transistors for the typical case, as well as for two
well, since expressions usually adopted for gm are additional corners, are shown in Table 2. In this
no longer valid. table we also show the values for the transistors
− The usually ignored dependency on VDS for the effective length, Lef, obtained from Hspice
TABLE 2
static behavior characterization of transistors in NPOWER MODEL PARAMETERS FOR 1.8V SMIC018 PMOS
the saturation region must now be taken into
Typical Corner Corner
account. Case C1 C2
Temperature 27 -40 125
III. AUTOMATIC GENERATION OF NPOWER Vdd 1.8 1.98 1.62
MODEL PARAMETERS Mos Model mos_tt mos_ff mos_ss
For the automatic generation of Npower MOS Lef (µ) . 4665 . 4542 . 4788
model parameters, we have developed a Python B(µ) 21.276 28.182 16.077
script. For the VCO model we will only use n 1.60 1.54 1.69
transistors with VBS=0, for the topology detailed K . 828 .884 .891
in Section IV. In this case, only six DC simulation m .770 .743 .795
points of Id(VDS,VGS), as illustrated in figure 1 λ0 .053 .054 .030
need to be evaluated [2]. Vt0 .462 .495 .428
Figure 2 shows the accordance of the
8.0E-04
Id(VDS,VGS)characteristics obtained with the
model, against those obtained with Hspice.
6.0E-04
ID(Vgs,Vds)
Id
4.0E-04
1.2E-02
2.0E-04

8.0E-03
0.0E+00 Vds
0.0 1.1 2.2 3.3
Id

4.0E-03
Fig. 1. Points for Npower model generation

To determine the model parameters (B, n, K, 0.0E+00

m, λ0 and Vt0), the program invokes Hspice for 0.0 0.6 1.2 1.8
Vds
performing a DC simulation of one transistor at
the six different points (automatically elected by
the program) and then, the algorithm described in Fig. 2. ID(VDS, VGS) for 1.8V SMIC018 PMOS
[2] is applied. A verification option is available,
transistor with W/Lµ=5/.5 : (-) simulated with
enabling the user to plot the Id(VDS,VGS)
Hspice, (*) from Npower model
 IV. PMOS SYMMETRIC-LOAD RING VCOS
Ring VCOs consisting of differential inverting
stages, as illustrated in figure 3, have been
proposed [6].
Fig. 3. Differential buffers VCO structure
Each differential stage contains PMOS
symmetric loads as illustrated in figure 4 [7].
Fig. 4. VCO Symmetric loads differential buffer
The bias current source, Ibias, is designed so
that the maximum voltage accross the symmetric
load is equal to the control voltage Vc.
V. PREVIOUS VCO MODELS
The frequency of oscillation of these ring
oscillators is usually evaluated with eq.7, where
tdelay is the propagation delay of each buffer stage
f osc = (2.N .t delay )
−1
(7)
The first model proposed for the VCO
comprising the delay cells represented in figure 4
considers eq.(8) for the evaluation of tdelay where
the effective buffer output capacitance, Ceff, and
the effective resistance Reff of the symmetric load
are considered.
t delay = Reff .C eff (8)
In [7] Reff is considered as directly proportional
to the small signal resistance at the ends of the
swing range of the output voltage, and thus the
inverse of the transconductance gm of one of the
two equally sized load transistors when biased at
the control voltage Vc. By considering the drain
current of one of the transistors given by eq. (9),
taking the derivative with respect to Vc yields
eq.(10).
I D = (β 2)(Vc − Vt ) 2 (9)
Reff = gm−1 = (β (Vc −Vt) )−1 (10)
Combining the previous eq.s (7), (8) and (10)
we obtain eq. (11) for the VCO linear model.
β (Vc − Vt )
f osc = (11)
2.N .C eff
In [8] a new model is proposed, yielding more
accurate results for the case of small values of the
control voltage. This model considers the
effective resistance of the symmetric load as the
ratio between the maximum voltage swing, VLMax,
and ILmax,. Since by design constraints, the
maximum voltage swing equals the control
voltage, Reff is given by eq. 12, leading to the VCO
model represented in eq. 13
Vc
Reff = (12)
β .(Vc − Vt ) 2
β .(Vc − Vt ) 2
f osc = (13)
2.N .C eff .Vc
VI. NEW VCO MODEL
The proposed models rely on the quadratic
MOS model, thus leading to inaccurate results
when submicron technologies are used. Much
more accurate results may be obtained if we
consider Npower MOS model in the evaluation of
the effective resistance of the VCO symmetric
loads. As the MOS transistors comprising the
symmetric loads have a null bulk source voltage,
the Npower model will resume to eq. 14, and eq.
15, for transistors in saturation region.
VTh = VT 0 (14)
I D = I D SAT .(1 + λ 0 .V DS ) ⇐ V DS ≥ V DSAT (15)
Using the previous equations we obtain eq.16
for the symmetric load effective resistance,
yielding the new VCO model in eq.(17)
−1
2.B.W (VC − VTh ) (1 + λ0 .Vc )
n
Reff = (16)
Leff Vc
 B.W (VC − VTh ) (1 + λ 0 .Vc )
n conditions as well as for granting the access to the
f osc = . (17) technology files, which made this work possible.
Leff Vc.N .C eff

The proposed model is based on an

2.2E+08
approximate expression for evaluating the
symmetric load effective resistance. To overcome
1.8E+08
this limitation, a charge-based analytical model

Frequency
which accounts for the symmetric load transistor
1.4E+08
operating regions should be derived. Yet, the
accuracy of the results we have obtained for
1.0E+08
several examples is quite good, thus making a
more complex model unnecessary.
6.0E+07
The second limitation of the model proposed is
1.0E+00 1.2E+00 1.4E+00 Vc
that it contains no information regarding the limits
of validity of the model. This additional
information will be considered in future work.
Fig. 5. Frequency vs. Vc for a 1.8V SMIC018
VII. APPLICATION EXAMPLE seven stage VCO: (*)Hspice; (__) New model; (__)
Model [8]
TABLE 3
As an application example we have considered
MAXIMUM AND AVERAGE RELATIVE ERRORS.
a seven-stage symmetrical load differential VCO.
Typical Corner C1 Corner C2
Each stage considered is illustrated in Figure 4, New Model New Model New Model
with the transistor sizes shown in Table 1. The Model [8] Model [8] Model [8]
results obtained for the typical case as well as for Av. 2.0% 13.0% 3.4% 16.0% 1.8% 3.8%
corners C1(upper lines) and C2 (lower lines) are Max 3.0% 24.0% 7.0% 29.4% 3.0% 9.0%
illustrated in figure 5.
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ACKNOWLEDGMENT of High-Energy Physics Experiments”, PdD. Dissertation,
M. Helena Fino would like to thank Chipidea - Technische Universitat Wien, February 1999.
Microelectronica, S.A., for providing excellent working