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Abstract — A new bridgeless buck PFC rectifier that converter, but also on the switching losses of the primary
substantially improves efficiency at low line of the universal line switches of the downstream dc/dc output stage and the size
range is introduced. By eliminating input bridge diodes, the and efficiency of its isolation transformer. Because switching
proposed rectifier’s efficiency is further improved. Moreover, losses dominate at light loads, the light-load efficiency of a
the rectifier doubles its output voltage, which extends useable
power supply exhibits a steep fall-off as the load current
energy of the bulk capacitor after a drop-out of the line voltage.
The operation and performance of the proposed circuit was decreases.
verified on a 700-W, universal-line experimental prototype At lower power levels, i.e., below 850 W, the drawbacks of
operating at 65 kHz. The measured efficiencies at 50% load the universal-line boost PFC front-end may partly be
from 115-V and 230-V line are both close to 96.4%. The overcome by implementing the PFC front-end with a buck
efficiency difference between low line and high line is less than topology. As it has been demonstrated in [3], the universal-
0.5% at full load. A second-stage half-bridge converter was also line buck PFC front end with an output voltage in the 80-V
included to show that the combined power stages easily meet range maintains a high-efficiency across the entire line range.
Climate Saver Computing Initiative Gold Standard. In addition, a lower input voltage to the dc/dc output stage
has beneficial effects on its light-load performance because
I. INTRODUCTION
lower-voltage-rated semiconductor devices can be used for
Driven by economic reasons and environmental concerns, the dc/dc stage and because lower input voltage reduces the
maintaining high efficiency across the entire load and input- loss and size of the transformer.
voltage range of today’s power supplies is in the forefront of The buck PFC converter operation in both DCM and CCM
customer’s performance requirements. Specifically, meeting mode was described first in [4], whereas additional analysis
and exceeding U.S. Environmental Protection Agency’s and circuit refinements were described in [5]-[12]. Because
(EPA) Energy Star [1] and Climate Saver Computing the buck PFC converter does not shape the line current
Initiative (CSCI) [2] efficiency specifications have become a around the zero crossings of the line voltage, i.e., during the
standard requirement for both multiple- and single-output off- time intervals when the line voltage is lower than the output
line power supplies. Generally, the EPA and CSCI voltage, it exhibits increased total harmonic distortion (THD)
specifications define minimum efficiencies at 100%, 50%, and a lower power factor (PF) compared to its boost
and 20% of full load with a peak efficiency at 50% load. For counterpart. As a result, in applications where IEC61000-3-2
example, for the highest-performance tier of single-output and corresponding Japanese specifications (JIS-C-61000-3-2)
power supplies with a 12-V output, i.e., for the Platinum level need to be met, the buck converter PFC employment is
power supplies, the required minimum efficiencies at 100%, limited to lower power levels.
50%, and 20% load, measured at 230-V line, are 92%, 94%, In this paper, a bridgeless buck PFC rectifier that further
and 91% respectively. improves the low-line (115-V) efficiency of the buck front
In universal-line (90-264-V) applications, maintaining a end by reducing the conduction loss through minimization of
high efficiency across the entire line range poses a major the number of simultaneously conducting semiconductor
challenge for ac/dc rectifiers that require power-factor components is introduced. Because the proposed bridgeless
correction (PFC). For decades, a bridge diode rectifier buck rectifier also works as a voltage doubler, it can be
followed by a boost converter has been the most commonly designed to meet harmonic limit specifications with an output
used PFC circuit because of its simplicity and good power voltage that is twice that of a conventional buck PFC
factor (PF) performance. However, a boost PFC front-end rectifier. As a result, the proposed rectifier also shows better
exhibits 1-3% lower efficiency at 100-V line compared to hold-up time performance. Although the output voltage is
that at 230-V line. This drop of efficiency at low line can be doubled, the switching losses of the primary switches of the
attributed to an increased input current that produces higher downstream dc/dc output stage still significantly lower than
losses in semiconductors and input EMI filter components. that of the boost PFC counter part.
Another drawback of the universal-line boost PFC front To verify the operation and performance of the proposed
end is related to its relatively high output voltage, typically in circuit, a 700-W, universal-line experimental prototype
the 380-400-V range. This high voltage not only has a operating at 65 kHz was built. The measured efficiencies at
detrimental effect on the switching losses of the boost 50% load over the input voltage range from 115-V to 230-V
S1
D1 D3
C1 0
t
+ S1
V AC
RL VO
-
0
t
T L /2
D2 D4
C2
TL
L2 (a)
L1
S2
S1
Fig. 1. Proposed bridgeless buck PFC rectifier.
D1 D3
C1
are more than 96%. In addition, the full-load efficiency
difference between low line and high line is less than 0.5%. V AC
+
24
DEAD DEAD S1
ANGLE ANGLE
VIN I IN D1 D3
VO C1
+
V AC
L1 RL VO
0 θ0 π − θ0 π θ D2 D4
C2
Fig. 4. Ideal input voltage and input current waveforms of a PFC buck
rectifier.
S2
Because the PFC buck rectifier does not shape the line (a)
LB
current during the time intervals when the line voltage is
lower than the output voltage, as shown in Fig. 4, there is a S1
, k ≥ 0.5 . (2) D1 D3
S = k ⋅S
e S f, max S
C1
25
STP42N65M5
CT 1 L1 10% 20% 50% 100%
1:100 98
S1 L 1 , L2 +
C1
D1 D3 60uH, 24 turns 80 V
VIN=115 VAC
GSIB2580 3x
RHRP1560 Litz wire 1000uF - 97
0.1mm x 110 /100 V
strands,
90 V RMS
V AC PQ3225-DMR95
~265 VRMS
Efficiency [%]
96
VIN=230 VAC
RHRP1560 C2 +
D2 3x 95
GSIB2580 D4 80 V
1000uF
/100 V -
CT 2
STP42N65M5 L2
94 fS = 65 kHz
1:100
S2 VO = 160 VDC
V CC2
RS Z2 93
V RAMP 70 80 90 100 150 200 250 300 350 400 450 500 550 600 650 700
Z1 Output Power [W]
Lo Ho VS VB CS FB Fig. 7. Measured efficiency of the proposed bridgeless buck PFC rectifier.
IR2113 Hin DRV NCP1203 V REF
COM VCC Lin VCC GND
voltage, the peak voltage stress on switch S1 and S2 can be as
high as 380 V, which is the peak input voltage at the
V CC1
maximum line. The peak current stress on switch S, which
Fig. 6. Experimental prototype circuit of the proposed bridgeless buck PFC occurs at full load and low line, is approximately 9 A.
rectifier.
Therefore, a STP42N65M5 MOSFET (VDSS = 650 V, RDS =
as shown in Fig. 5(c). In this implementation, a bi-directional 0.079 Ω) from ST was used for each buck switch. Since
switch is formed by the serial connection of switches S1 and output diodes D3 and D4 must block both the same peak
S2 with their anti-parallel diodes DS1 and DS2. voltage stress and conduct the same peak current as the
Yet another variation of the proposed bridgeless buck PFC switches, an RHRP1560 diode (VRRM = 600 V, IFAVM = 15 A)
rectifier is in Fig. 5(d). In this circuit, the anodes of from Fairchild was used as boost diode D. It should be noted
freewheeling diodes D3 and D4 are connected directly to the that the employed output diode is a low-cost conventional
negative and positive output rails, respectively, instead of to silicon diode since the reverse-recovery related loss in the
the midpoint of the output capacitors as in Fig. 1. It is proposed rectifier is much smaller than that of its boost
interesting to note that the circuit in Fig. 5(d) exhibits a non- counterpart, which frequently uses expensive silicon-carbide
linear gain characteristic given by diodes. In fact, the voltage across the switches and diodes are
2D much lower than those of a boost rectifier at low line
VO = VIN . (3) operation, and the turn-on loss and the reverse-recovery-
1 + (1 − D) 2
related losses are significantly lower.
According to Eq. (3), if duty cycle D is near unity, i.e., To obtain the desired inductance of output inductor L1 and
when input voltage VIN is close to half of output voltage VO,
L2 of approximately 60 μH and also to achieve high
the input-to-output gain is similar to that shown in Eq. (1).
efficiency at light-load, the output inductor was built using a
However, if duty cycle D is near zero, i.e., when input
pair of ferrite cores (PQ-3225, DMR95) and 24 turns of Litz
voltage VIN is much greater than output voltage VO, the input-
wire (0.1mm, 110 strands). Litz wires were employed to
to-output gain becomes
reduce fringe effects near the gap area of the inductors.
VO = DVIN , (4)
Three aluminum capacitors (1000 μF, 100 VDC) were
which is similar to the input-to-output gain of a conventional used for output capacitors C1 and C2 for their ability to meet
buck converter. the hold-up time requirement (20 mS at 50% load and 12 mS
Finally, if reverse voltage blocking switches that allow at full load).
unidirectional current flow are utilized for switches S1 and S2 As shown in Fig. 6, the bulk capacitor voltage that is the
in Fig. 1 and Figs. 5(a), 5(b), and 5(d), diodes D1 and D2 can voltage across series connected capacitors C1 and C2 was
be eliminated. regulated by a single controller (NCP1203 from On-Semi).
Switches S1 and S2 were operated simultaneously by the same
III. EXPERIMENTAL RESULTS gate signal from the PWM controller. Although both switches
The performance of the proposed rectifier in Fig. 1 was were always gated, only one switch carried positive current
evaluated on a 65-kHz, 700-W prototype circuit that was and delivered power to the output, i.e., switch S1 on which
designed to operate from a universal ac-line input (85 VRMS- the positive input voltage was induced, as shown in Fig. 2.
264 VRMS) with a 160-V output. The other switch on which the negative input voltage is
Figure 6 shows the schematic diagram and component induced, i.e., switch S2 in Fig. 2, did not influence the
details of the experimental prototype circuit. Since the drain operation since diode D2, which is connected in series with
voltage of switches S1 and S2 are clamped to the voltage switch S2, blocked the current. It should be noted that the
difference between the input voltage and output capacitor voltage across each capacitor C1 or C2 can be independently
26
5.0
VIN
PO=700 W measured Class D
4.0
VIN=115 VAC PO=700 W
VIN=115 VAC
VIN VO=160 VDC 3.0
Current [A]
VO=160 VDC
THD = 43.4%
[50 V/div] PF = 0.886
IIN 2.0
IIN
[10 A/div]
1.0
Current [A]
VO=160 VDC VO=160 VDC
THD = 23.3%
VIN PF = 0.948
[100 V/div] 1.0
IIN
IIN
0.5
[5 A/div]
0.0
THD = 23.3% 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
PF = 0.948 (b)
0.6
(b) measured Class D
0.5
VIN
PO=75 W PO=75 W
0.4 VIN=115 VAC
VIN=115 VAC
Current [A]
VO=160 VDC
0.3
THD = 31.3%
VIN VO=160 VDC PF = 0.921
27
VC2 VC1+C2 PO=350 W
VC1+C2
[50 V/div]
VC1, VC2
VOUT
[50 V/div] VC1 [5 V/div] VOUT
I IN VIN
28
10% 20% 50% 100%
94
93
92
91 VIN=115 VAC
Efficiency [%]
90
89
88
VIN=230 VAC CSCI Single-Output
87
Power Supply “Gold”
86
85
84
10 20 30 40 50 60 70 80 90 100 150 200 250 300 350 400 450 500 550 600 650 700
Output Power [W]
Fig. 13. Measured total efficiency of the proposed bridgeless buck PFC rectifier and half bridge 2nd stage converter. The power
supply delivers 12 V dc output from 115 V and 230 V ac inputs. Efficiency requirements of Climate Saver Computing
Initiative (CSCI) “gold” specification are also plotted.
The measured total efficiency of the proposed bridgeless [3] L. Huber, L. Gang, and M.M. Jovanović, "Design-Oriented Analysis
and Performance Evaluation of Buck PFC Front-End," IEEE Applied
buck PFC rectifier and half bridge 2nd stage converter is
Power Electronics Conf. (APEC) Proc., pp.1170-1176, Feb. 2008.
plotted in Fig. 13. The power supply that delivers 12 V dc [4] H. Endo, T. Yamashita, and T. Sugiura, "A high-power-factor buck
output from 115 V and 230 V ac inputs meets the efficiency converter," IEEE Power Electronics Specialists Conference (PESC)
requirements of CSCI Gold specifications over the entire load Rec., pp. 1071-1076, June 1992.
and input ranges. [5] R. Redl and L. Balogh, "RMS, dc, peak, and harmonic currents in high-
frequency power-factor correctors with capacitive energy storage,"
IV. SUMMARY IEEE Applied Power Electronics Conf. (APEC) Proc., pp.533-540,
In this paper, a new bridgeless buck PFC rectifier that Feb. 1992.
substantially improves the efficiency at low line has been [6] Y.W. Lo and R.J. King, "High performance ripple feedback for the
buck unity-power-factor rectifier," IEEE Transactions on Power
introduced. The proposed rectifier doubles the rectifier output
Electronics, vol. 10, no.2, pp.158-163, March 1995.
voltage, which extends useable energy after a drop-out of the [7] Y.S. Lee, S.J. Wang, and S.Y.R. Hui, "Modeling, analysis, and
line voltage. Moreover, by eliminating input bridge diodes, application of buck converters in discontinuous-input-voltage mode
efficiency is further improved. operation", IEEE Transactions on Power Electronics, vol. 12, no.2,
The operation and performance of the proposed circuit was pp.350-360, March 1997.
verified on a 700-W, universal-line experimental prototype [8] G. Spiazzi, "Analysis of buck converters used as power factor
preregulators," IEEE Power Electronics Specialists Conference (PESC)
operating at 65 kHz. The measured efficiencies at 50% load Rec., pp. 564-570, June 1997.
from 115-V and 230-V line are close to 96.4%. The [9] V. Grigore and J. Kyyrä, "High power factor rectifier based on buck
efficiency difference between low line and high line is less converter operating in discontinuous capacitor voltage mode", IEEE
than 0.5% at full load. Finally, a half bridge dc-dc converter Transactions on Power Electronics, vol. 15, no.6, pp.1241-1249, Nov.
is added as a second stage converter. The measured total 2000.
efficiency is well above the CSCI specifications at both 115- [10] C. Bing, X. Yun-Xiang, H. Feng, and C. Jiang-Hui, "A novel single-
phase buck pfc converter based on one-cycle control," CES/IEEE
V and 230-V line. International Power Electronics and Motion Control Conf. (IPEMC),
pp.1401-1405, Aug. 2006.
ACKNOWLEDGEMENT
[11] G. Young, G. Tomlins, and A. Keogh, "An acdc converter," World
The authors want to thank David L. Dillman and Juan Ruiz, Intellectual Property Organization, International Publication Number
Support Engineers from the Power Electronics Laboratory, WO 2006/046220 A1, May 4, 2006.
Delta Products Corporation, for their assistance in [12] W.W. Weaver and P.T. Krein, "Analysis and applications of a current-
constructing the experimental converters and collecting data. sourced buck converter," IEEE Applied Power Electronics Conf.
(APEC) Proc., pp.1664-1670, Feb. 2007.
REFERENCES [13] D. Maksimović, "Design of the clamped-current high-power-factor
[1] Environmental Protection Agency (EPA), “Energy Star Program boost rectifier," IEEE Transactions on Industry Applications, vol. 31,
no.5, pp.986-992, September/October 1995.
requirements for single voltage external ac-dc and ac-ac power
supplies,” available at [14] R. Redl, A.S. Kislovski, and B.P. Erisman, "Input-current-clamping: an
inexpensive novel control technique to achieve compliance with
http://www.energystar.gov/ia/partners/product_specs/program_reqs/EP
S_Eligibility_Criteria.pdf harmonic regulations," IEEE Applied Power Electronics Conf. (APEC)
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[2] Climate Savers Computing Initiative, White Paper, available at
[15] L. Huber and M.M. Jovanović, "Design-oriented analysis and
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