326
3, MARCH 1990
Considerations for Fast Settling Operational
Amplifiers
Abstracr -The design considerations for fast-settling operational ampli-
fiers (opamps) are significantly different between sampled-data switched-
capacitor (SC) and conventional continuous-time applications. In SC cir-
cuits, the shape of the output voltage waveform of an opamp is of no
consequence provided that the output settles to within a specified tolerance
of its steady-state value prior to the next sampling instant. This feature
allows for an optimum opamp frequency shaping to obtain a minimum
small-signal settling time. The theory applies to any opamp that is well
approximated by a two-pole model, including the conventional two-stage
and single-stage folded-cascode topologies. As the commonly-used equiva-
lent-circuit Miller-effect model for frequency compensation has generally
been improperly applied to two-stage transconductance amplifiers, it does
not provide sufficient accuracy to achieve the optimum phase margin
condition. Therefore, the use of equivalent-circuit models has been refined
to provide greater accuracy and to eliminate some previous misconcep-
tions.
I. INTRODUCTION
M ANY aspects of the settling behavior and frequency
response of operational amplifiers (opamps) have
been analyzed by various authors [1]-[6]. Generally, it has
been shown that in order to obtain the desired
settling/frequency characteristics, accurate frequency
shaping must be employed. In conventional continuous-
time applications, opamps are frequency compensated
(either internally for two-stage opamps or via the loading
capacitance for single-stage opamps) for a unity-gain phase
margin of approximately 60 deg to insure closed-loop
stability, and to maximize flatness of the closed-loop am-
plitude response [l],[2]. Flat gain characteristics are par-
ticularly important in minimizing waveform distortion in
continuous-time pulse-amplifier applications. By contrast,
the specific shapes of the opamp output waveforms are of
no consequence in some applications, such as in sampled-
data switched-capacitor (SC) circuits where it is only nec-
essary that the outputs settle to within a specified toler-
ance of their final values prior to the next sampling
instant. By exploiting this unique feature of SC circuits, an
optimum opamp phase margin criterion has been devel-
Manuscript received November 9, 1988; revised June 5, 1989. D.
Allstot was supported by the National Science Foundation under Con-
tract MIP-8709158. This paper was recommended by Associate Editor
T. T. Vu.
H. C. Yang was with Department of Electrical and Computer Engi-
neering, Oregon State University, Corvallis, OR. He is now with National
Semiconductor, Santa Clara, CA.
D. J. Allstot is with the Department of Electrical and Computer
Engineering, Oregon State University, Corvallis, OR 97331.
IEEE Log Number 8933445.
0098-4094/90/0300-0326$01.00 01990 IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO.
oped that gives the minimum settling time of an opamp for
a given gain/bandwidth product.
Our analysis has shown that the small-signal settling
time of a two-pole (one or two-stage) opamp exhibits a
well-defined minimum for a specific value of the unity-gain
phase margin. Since the settling time is also shown to be
strongly dependent on phase margin, precise frequency
shaping is required in order to achieve the minimum
settling time (MST). Unfortunately, the commonly used
equivalent-circuit model of the opamp based on the Miller
approximation has in the past been improperly applied to
two-stage transconductance amplifiers and does not pro-
vide sufficient accuracy with whch to achieve the MST.
Therefore, improved equivalent-circuit models have been
developed and are presented in the second part of t h s
paper. In addition to being significantly more accurate
than the previous modeling, wherein the dominant pole
was always associated with the first stage, the improved
modeling accounts for the possibility of a second-stage-
dominant pole. In fact, for CMOS and GaAs operational
transconductance amplifiers (OTA) that drive on-chp ca-
pacitive loads, the dominant pole is usually associated with
the second stage. Our results show that whichever pole is
dominant before compensation remains dominant after
compensation. Hence, some considerable confusion that
has existed previously regarding pole-splitting frequency
compensation is eliminated.
In Section 11, we develop a new optimum phase margin
design criterion for OTA’s used in SC applications. In
Section 111, we present some improved modeling tech-
niques for two-stage opamps that provide sufficient accu-
racy with whch to achieve the optimum phase margin
condition. In Section IV, we describe sensitivities to MOS
process variations.
11. OPTIMUM PHASE MARGINFOR sc
APPLICATIONS
We begin t h s section with a brief review of the fre-
quency and step-response equations of a second-order
system. We then use t h s theory to derive an optimum
unity-gain phase margin that allows for the maximum
sampling frequency in SC circuits. Finally, design equa-
tions are developed to allow two-pole opamps to be com-
pensated for the optimum phase margin condition.
YANG A N D ALLSTOT: FAST SETTLING OPERATIONAL AMPLIFIERS 321

A . Frequency/ Time Response Equations for a Two-Pole (VOLTS)

System
In most switched-capacitor circuits, the maximum size
of the output voltage step between sampling instants is
small enough so that only small-signal analysis is neces- I I
II
sary. Therefore, the opamp is modeled using a linear I
I
I
I
two-pole model which is very useful in determining the I
I I
I
I
pole-splitting compensation capacitance [ 7 ] ,[ 81. The open- I
I
I
I
I I
loop transfer function of the two-pole small-signal circuit I
I
prior to frequency compensation is given by 0 tP t6 mm
a0 Fig. 1. Definition of small-signal settling time, r,, with an error toler-
a(s) = (1) ance of D percent. The first positive peak of the underdamped re-
(1+ s/w1)(1+ +2) sponse occurs at time t p .

where a, is the low-frequency gain of the opamp and o1

and w 2 are the radian frequencies of first and second Underdamped (overshoot followed by exponentially
left-half-plane (LHP) poles, respectively. The unity-gain damped sinusoid), k < 1 :
closed-loop transfer function is given by
k
4 s ) -
A ( s ) = --
A,
l+a(s) (~/o,)~+2k(~/w,)+l
(2)
uo(t)=1-
(1- k2)1/2 (
sin[ (1 - k2)”’wot]

where
+cos[(l- k2)1’2w,t]]exp( - k w o t ) . (9)
a0
A,=- (3)
1+a,
B. Small-Signal Settling Behavior of a Second-Order System
w, = [w1w2(1 + a,)] ‘I2 (4)
The small-signal settling time of an operational ampli-
and fier, t,, is defined (Fig. 1) as the minimum time required
for the output voltage of the amplifier to settle to withm
an error tolerance, D , of its final steady-state value. Using
(7)-(9), it can be shown that the settling behavior of a
Defining the pole separation factor as /3 = w 2 / w 1 , the two-pole system is strongly dependent on the damping
damping factor is expressed in terms of p as factor k . For a nominal value of the low-frequency open-
l+P loop voltage gain, a,, the damping factor is only a func-
k= (6) tion of the pole separation factor, p, according to (6).
2[ ~ ( 1 a,)]1’2
+ ’
The time response of a second-order system is usually
The second-order system of ( 2 ) has three possible re- discussed in terms of the normalized variable wot [ 2 ] .Since
w, is a function of k from (9,and therefore, also of /3
sponses to a voltage step input; namely, overdamped,
critically damped, and underdamped corresponding to k > from (6), w,t is a dependent variable. As a first step in
finding the shortest response time of the second-order
1, k = 1 , and k < 1, respectively. The normalized time
responses are obtained from ( 2 ) using the inverse Laplace system, the time of the first peak of the underdamped
transform as follows. response, t , (Fig. l ) , is determined by setting the first
derivative of (9) equal to zero to obtain
Overdamped: (exponentially approaching the steady- m
state value), k > 1: t, =
1 wo(l - k 2 ) l l 2
uo(t)=1-
2( k 2 - 1)’I2 Now, using (4) in (lo), t, as a function of /3 is
1 77
( - k l w o t )- -exp ( - k 2 w o t ) ] (7) t = (11)
k2 w l l p ( 1 + a,) - ( 1 + p)’/4] 12’ ’

where k l = k - ( k 2 - l ) 1 / 2 and k 2 = k + ( k 2 - l ) 1 / 2 .
Critically Damped: (also exponentially approaching the
final value), k = 1:
uo ( t ) = 1 - (1+ wot ) exp ( - wet). (8)
The minimum of t, with respect to p determines the
shortest possible response time, and. is determined by
setting the first derivative of ( 1 1 ) equal to zero and solving
to obtain p = 1 + 2 a , . Substituting this value into (6) gives
 I,
328
0 MST mmE)
Fig. 2. Definition of the minimum small-signal settling time (MST) for
a two-pole system with an error tolerance of D percent. Settling time is
increased for either more or less damping.
the optimum damping factor as
l + a,
k=
[(l+ 2 a 0 ) ( l + ities in response time are associated with the natural frequency of the
Since a, >> 1 is usually true in practical cases, (12) simpli-
fies to k = 0.707 meaning that the absolute fastest re-
sponse of the system corresponds to the Butterworth re-
sponse. However, t h s does not indicate the minimum
settling time in general since the error band, D, was not
considered in the above analysis. In fact, it can be shown
that the Butterworth response is underdamped exhibiting a
transient overshoot of 4.3 percent, and therefore, yields the
minimum settling time only for the cases where D > 0.043.
The Butterworth response provides a unity-gain phase
margin of approximately 60 deg.
For high precision SC circuits, an error tolerance smaller
than 4.3 percent is required. The minimum settling time is
obtained when the two-pole opamp is underdamped and
the phase margin is chosen so that the first peak of the
step response just touches the upper settling error limit as
shown in Fig. 2. Referring to the figure, it is clear that this
is the minimum since either an increase or decrease in the
damping factor results in greater settling time.' Therefore,
to realize the maximum sampling frequency, the phase
margin condition "upper error bound = first peak" must
be satisfied. The normalized voltage of the first peak
determined from (9) is equal to one plus the overshoot:
first p e a k = l + e x p [ - k ~ / ( l - k ~ ) " ~ ] (13)
and since the upper error bound voltage is (1+ D), then
D = exp[ - k T / ( l - k2)'j2].
(14)
Using (6) with p >> 1, the optimum pole-separation factor,
Po, is determined from (14) as [lo]
'Actually, the absolute minimum settling time occurs for the case
wherein a doublet is deliberately introduced to give a three-pole one-zero
response with the singularities placed so that ths first peak just touches
the upper bound, and the second peak just touches the lower error bound.
It has been shown that this is probably not a practical solution because of
high sensitivities to parameter variations [9].
IEEE TRANSACTIONS ON CIRCUITS A N D SYSTEMS. VOL. 37, NO. 3, MARCH 1990
60-
0.0O01 ?&
a. = 1000 V/V
3 0 4 0 5 0 6 0 7 0 8 0 0
PHASE MARGIN (DEGREES)
Fig. 3. Normalized small-signal settling time versus unity-gain phase
margin for common values of the error tolerance, D. The discontinu-
system, and occur when response peaks or valleys just enter the
bounded region for increasing phase margin.
For a given error band, D, the minimum settling time of
the SC circuit is achieved by designing the two-pole opamp
so that the poles are separated in accordance with (15).
In opamp design, the settling time is usually considered
as a function of phase margin, &, rather than of the pole
separation factor, P, or equivalently of the damping factor,
k . Thus a relationship between the settling time and the
phase margin is desirable. Approximating the small-signal
unity-gain frequency, U,, as U, = aoo,, and the unity-gain
time constant, T,, as T, = l/w,,, the phase margin, @m, of a
two-pole system (assuming widely separated poles) is ex-
pressed as
@,=180°-tanp'(o,/o,)-tanp'(o,/w2)
=180"-tan-'(w,/o,)-tan-'(w,/~wl). (16)
For example, with a, =lo00 V/V and fi = w 1 / 2 n =1
kHz, the normalized small-signal settling time, t,/r,, of
the two-pole system is plotted versus the unity-gain phase
margin in Fig. 3. Clearly, the normalized settling time is a
very strong function of the phase margin, and thus in
order to obtain maximum operating speed, an accurate
phase margin is required. The phase margin corresponding
to the MST, @,,,(MST),is also a function of the error band
tolerance as seen in Fig. 3, and is derived using (15) and
(16) (with the assumption that tan-'( o,/wl) = 90") as
For D = 0.01, (17) gives @,,,,(MST)= 70". Note that when
D + 0, +m(MST)+ 76" which corresponds to the critically
damped response of the two-pole system.
C. Compensation Considerations
In the previous section, it was shown that the Butter-
worth response provides the MST only for the rather
impractical and imprecise cases wherein D > 0.043. For
YANG AND ALLSTOT: FAST SETTLING OPERATIONAL AMPLIFIERS 329

ct Rt +5v

I 1

Fig. 4. Small-signal model of two-pole opamp with pole-splitting com-

pensation elements RI and Cl.

higher precision applications, D is much smaller, and

therefore, an improved compensation technique is required -5v

to achieve the MST. Fig. 5 . A typical two-stage CMOS opamp used to test the compensa-
tion model. The fractions represent MOSFET ( W / L ) ratios in microme-
Fig. 4 shows a two-pole small-signal equivalent circuit of ters. RI and Cl are the pole-splitting frequency compensation elements.
a two-stage opamp whch after adding compensation ele-
ments exhibits three LHP poles and one zero. Solving the
network equations and using the dominant pole approxi- where
mation technique [l],[ll], the pole and zero frequencies
after compensation are
g1g2
w1 = (18)
(8m2+~1+g2)~/+g2~l+glC2
(gm2 + g1+ ~2)c/+ g1C2 + g2C1
w, = (19)
CICf + c2c/+ C1C,

and
c=C1+C2. (25e)
and
1 The solutions of (24) and (25) give the compensation
w, = element values which provide the MST response for the
C,(l/g,, -R/) opamp.
where g, = l / R l and g, = l / R 2 . The values for the com-
pensation capacitance, Cr, and the nulling resistance, R,, 111. IMPROVED
EQUIVALENT
CIRCUITMODELING
are usually chosen so that the zero exactly cancels the first In t h s section, we examine the use of small-signal
nondominant pole [12]. Therefore, to obtain a simple two- equivalent circuits in frequency compensating two-pole
pole system and to minimize the small-signal settling time opamps. Our results show that the previous techniques
for a given amplifier bandwidth, (18)-(21) must satisfy based on Miller-multiplied capacitance models are suitable
only for those amplifiers in which the first-stage pole is
o2= wz (22)
dominant prior to compensation. In most SC circuits, the
and internal opamps are transconductance amplifiers whch
U3 = Po., (23) drive on-chp capacitive loads, and thus for these opamps,
the second-stage pole is dominant. Hence, in order to more
where P,, is determined from (15). Solving (22) and (23) accurately model the second-stage-dominant pole systems,
gives the element values for optimum compensation as and to subsequently realize the optimum phase margin
condition, we have extended the small-signal model to
include resistance effects in addition to Miller capacitance
effects.
(24)
A . Problem Description
and In order to test the accuracy of the compensation tech-
c, + c2 niques, a CMOS two-stage transconductance amplifier (Fig.
’-
C -
(~/-1/gim2)(grn2+ g l + g * )
. (25a) 5) was designed. As a first step in compensation, the
parameter values (Table I) for the small-signal model or
Substituting (24) into (25a) and solving for C, gives Fig. 6(a) were determined from Fig. 5. Unfortunately, thls
two-pole one-zero model is not convenient for calculating
C, [
= - b + ( b2 - ~ U C ) ” ~ ] / ~ U R f and C, because of the presence of the right-hand plane
330 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 37, NO. 3, MARCH 1990

200 200

r 1 -Original Model
2- Miller Capacitor Approx.

Fig. 6. Small-single models of (a) the two-pole one-zero, and (b) the
two-pole opamp before frequency compensation.

Using the small-signal parameter values given in Table I,

the two-pole one-zero model of Fig. 6(a), and the simpli-
fied two-pole model of Fig. 6(b) were simulated using
1 SPICE2. It is clear from the responses shown in Fig. 7 that
1st Stage 2nd Stage the simplified two-pole model (curve 2) is a poor approxi-
gnl ( B S ) 87.60 266.00 mation to the two-pole one-zero model (curve 1) especially
at critical frequencies near the unity-gain frequency. This
error in modeling before compensation significantly affects
R' (kn) 866.55
1 197.63
the accuracy of the unity-gain phase margin after compen-
20.80
Cgd (fF) sation. For example, a desired error tolerance of D = 0.01
requires an optimum phase margin of 70 degs. Using
(24)-(29) in conjunction with the model of Fig. 6(b), the
(RHP) zero introduced by Cgd;, Therefore, the next step compensation element values are calculated as R , = 12.3
usually involves using the Miller effect to develop the k a , and C, = 4.97 pF. Using these values in compensating
two-pole no-zero model of Fig. 6(b) [ll].In this circuit, the CMOS two-stage opamp of Fig. 5 results in a simu-
Miller capacitance C,, (C), is shunted across the first lated unity-gain phase margin of 84 degs. Because the
(second) stage to account for the effect of the gate-drain resulting phase margm deviates significantly from the opti-
capacitance, Cgd, on the frequency of the first (second) mum value of 70 degs, and because a doublet is also
stage pole. The RHP zero is assumed to be at a very high created due to inexact pole-zero cancellation, a very long
frequency relative to the unity-gain bandwidth, and is, settling time is observed. (Doublets may also result in
therefore, ignored. In the two-pole model of Fig. 6(b), the reduced settling time in SC circuits [9] with a tradeoff in
total branch resistances are R , = RI' = l / g i and R , = R,' increased sensitivity to MOS process variations. In prac-
= l/g,', and the total branch capacitances are given by tice, an adaptive compensation technique [12] may be used
to guarantee accurate pole-zero placement in the presence
c, = e,'+c,, (26) of typical variations.)
and
As previously stated, on-chip CMOS and GaAs
c, = C,' + c,, = e,, transconductance amplifiers are usually second-stage dom-
with inant-pole systems with R,'C,'< R2'C2' in the model of
Fig. 6(a). Conventional application of the Miller-multi-
plied capacitance effect in developing the equivalent cir-
and cuit of Fig. 6(b) predicts that the first-stage pole moves to
a lower frequency for a nonzero value of cgd and will
become dominant if C and/or g,, is large enough as
gd.
indicated in Fig. 8(a). This commonly-held view (c.f. [13, p.
We now show that when applied to a second-stage- 3771 is incorrect in terms of basic root locus theory wherein
dominant transconductance amplifier, this modeling ap- the poles of a two-pole system can never cross one another
proach does not allow frequency compensation to a suffi- as pole-splitting negative feedback is applied [l].The cor-
cient degree of accuracy to obtain the MST response. rect pole movements are as indicated in Fig. 8(b). With an

With the series R - C compensation network connected in parallel

increase of Cgd or gm2,the second-stage pole moves to a
with Cgd,the system kctuady exhibits three LHP poles and two zeros. The lower frequency remaining dominant, while the first-stage
zero associated with the R - C network is the one that is moved into pole moves to higher frequency remaining non-dominant.
the LHP to cancel the firdnonfdominant pole. The zero associated with
Cgdremains fixed in the RHP at its original frequency. In general, the poles are always split apart with the appli-

YANG AND ALLSTOT: FAST SETTLING OPERATIONAL AMPLIFIERS
t JW
Cgd=O P, p2
i- t
(b)
Fig. 8. (a) Unrealizable root-locus plot of pole splitting implied by
conventional application of the Miller capacitance model to a second-
stage dominant pole system, (b) Correct root locus plot predicted using
the improved model.
Cad
(b)
Fig. 9. Circuits for calculating impedance looking into Cgd (a) from the
first stage, and (b) from the second stage.
cation of pole-splitting compensation no matter whch of
the poles is dominant. It is now clear that the equivalent
circuit model of Fig. 6(b) with Miller-multiplied capaci-
tances is not an accurate representation of second-stage-
dominant transconductance amplifiers, and therefore, can-
not be used to achieve the MST response in this case.
B. Improved Equivalent Circuit Model
In order to achieve the MST response, modeling tech-
niques have been developed that are more accurate at
frequencies near the unity-gain frequency of the opamp.
The improved equivalent circuit model includes the con-
ventional first-stage-dominant one as a special case, and is
able to accurately predict the pole movement for optimum
frequency compensation of second-stage-dominant
transconductance amplifiers.
In the circuit of Fig. 6(a), the impedance looking into
Cgd from the left, Z , , is found from Fig. 9(a) as
~
331
Fig. 10. Impedance versus frequency looking into Cgd from the first
stage.
VI V”
Fig. 11. A complete two-pole small-signal circuit model prior to fre-
quency compensation.
when the operating frequency is low, (30) becomes
1 I
+
Since Cgd(gm2/g,‘ 1) is simply the Miller capacitance,
the conventional model clearly applies at low frequencies
(Fig. 10). When the operating frequency is between
g2//( c2’ + cgd) and ( gm2 + g2/)/c2/:
In t h s frequency range, the impedance is not due to the
Miller capacitance, but rather to a resistor, R,,, which
may be called a “Miller resistance.” When the operating
frequency is higher than ( gn,, + g2’)/C2:
(33)
whch is due to a capacitance, Csl, equivalent to C,, and
C,’ in series. The impedance looking into Cgd from the
right (Fig. 9(b)) is just Cgd in series with R,’ and Cl’. the
complete equivalent circuit model shown in Fig. 11 is
based on the impedances derived above. From thls analy-
sis, it is clear that the conventional equivalent circuit using
the Miller-multiplied capacitors is an incomplete model
accurate only for low frequencies.
SPICE simulations on the improved equivalent circuit
model of Fig. 11 using the small-signal circuit parameters
listed in Table I are compared with simulations of the
original circuit model (Fig. 6(a)) in Fig. 12. Excellent
agreement between the two circuits is obtained over the
frequency range of interest. The high-frequency RHP zero
due to Cgdis not included in the new equivalent circuit as
332 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL. 31, NO. 3, MARCH 1990

1 -Original Model
2 - New Equlv. Model

100
GAiN

-100 1
.;ICg
c \
1 2 , -_
grnl __ --cMl 9,2 > __
FREO (Ht)
,, VIn<% --cy 1) Vl<Ri --
c;
Fig. 12. Comparison of the simulated frequency responses of the com-
plete two-pole small-signal model of Fig. 11- to the original circuit
model of Fig. 6(a).

the frequency of the zero is usually large relative to the

unity-gain frequency.

n
Although the complete equivalent circuit is very accu- 200 200
1 - Original Model
rate, it is complicated, and must be simplified for ease of 2- Miller Resistor Approx.
use in frequency compensation calculations. In SC applica-
tions, the OTA is usually a second-stage dominant-pole
system with the nondominant pole at the output of the
first stage. Therefore, in the high-frequency range between
g2'/(C2'+C), and (g,, + g2')/Ci, the "Miller resistor"
(32) dominates the effect of the impedance Z, on the first
stage, while the capacitances c M 1 and C,, can be ignored.
For the second stage, R,' is removed for simplicity without
a significant reduction in accuracy. The simplified equiva- 10 100 1K 10K l 0 0 K 1 M 10M l 0 0 M 1G
-200
100
lent circuit for the second-stage dominant-pole system is -a (w)
shown in Fig. 13(a). Perhaps surprisingly, it has the same (a)
form as the previous simplified model of Fig. 6(b), with the 200
1 -Original M-I
only difference being in how the element values are deter- - 2 - Miller Capacitor Approx.
mined. For the first stage of Fig. 6(b):

R , = R,'R,,/(R,'+ R,,), C,=c,' (34)

and for the second stage,

R , = R ,', C, = C,' + CgdClr/(Cgd+ C,') . (35)

This two-pole circuit with new element values is applied to -200'

t ' 1 " '
U
' ' 7
1 -200
frequency compensation in the same manner as before. In 10 100 1K 10K l 0 0 K 1Y 10M 100M 10 100

the case of the transconductance amplifier, note that R , is =a (na

reduced significantly from R,' due to the small Miller
resistance, R,, (32), and C, is almost unchanged. There-
fore, R,C, < R1'C1', i.e., the first-stage pole moves to a
hlgher frequency because of the Miller resistor effect, while
the second-stage pole moves to a lower frequency.
For most general purpose opamps with output stages,
the condition R,'C,'> RiC2' is usually satisfied. There-
fore, the opamp is a first-stage dominant-pole system prior
to compensation. In this case, R,, and C,, in Fig. 11 may
be ignored due to their very h g h impedances at low
frequencies, while at the output of the second stage, re-
moving R,' is usually a valid approximation. With these
simplifications, the equivalent circuit for the first-stage
dominant-pole system reduces to the conventional Miller
capacitor model of Fig. 13(b) [14].
(b)
Fig. 14. Simulated frequency responses (after frequency compensation)
of the orignal circuit of Fig. 6(a) versus (a) the new two-pole model
using the Miller resistance, and (b) the old two-pole model using the
Miller capacitance.
C. Applications in Frequency Compensation
The simplified equivalent circuit for the second-stage
dominant-pole system (Fig. 13(a)) was derived using (34)
and (35) and applied to frequency compensation for the
MST response. The compensation element values were
calculated using Table I and (24) and (25) with D = 0.01
as R , =18.86 kQ and C, = 2.65 pF. SPICE simulations
with these values for the simplified equivalent circuit and
the original circuit of Fig. 6(a) are compared in Fig. 14(a).
YANG AND ALLSTOT: FAST SETTLING OPERATIONAL AMPLIFIERS 333

110, I

1
0. 75Cf 1. OCf 1. lCf

0.759, 65.7 68.6 70.8

I (52.4) (59.4) (56.4)
1 I
I I I I I I I
I
I
I , ! I I1 I 1

TIM€ (nS) 1.25gm

(54.2) (58.0) (61.4)
Fig. 15. Simulated step responses of the CMOS opamp for curve (1) the
MST case (approximately 70-deg phase margin), and curve (2) the (4
conventional 60-deg phase margin case. Note that the MST design is
faster even though the compensation capacitance required to achieve
the larger phase margin is somewhat larger.
1 I 0.9 C' 1.1 C'

The agreement is excellent at frequencies near the unity-

I 0*75
I (E:) I 67.5
(57.4) I
gain crossover frequency where the phase margin, and thus
the settling time, is determined. Although the agreement is
not as good at low frequencies, this is of no concern in
frequency compensation. The simulated unity-gain phase
margins were 72.4 deg and 73.1 deg for the original and
the simplified equivalent models. The small difference was compensation capacitance was varied by f 10 percent,
caused by neglecting the high-frequency zero introduced while the g,'s and the compensation resistance were varied
by C,, in Fig. 6(a). The conventional first-stage by f 2 5 percent. As shown in Table II(a), the MST exhib-
dominant-pole equivalent circuit (Fig. 13(b)) using the ited nearly identical sensitivity to the commonly-used 60-
Miller capacitance effect was also applied to the compen- deg case. As shown in Table II(b), the sensitivities were
sation of the transconductance amplifier with R , = 12.63 also simulated for k25-percent variations in RI' and R2',
kQ and C, = 4.97 pF, as calculated previously. The SPICE and +lo-percent variations in C,' and C,'. Again, the
simulation results of Fig. 14(b) show poor agreement with sensitivities were similar. Obviously, we cannot compen-
the original circuit in both the low- and hgh-frequency sate the opamp exactly at the MST point over processing
ranges. variations. The key point here is that if we select the MST
Finally, the more accurate compensation element values as the nominal condition, then including process varia-
obtained using the improved model, R , =18.86 kQ and tions, the range of settling times is always less than the
C, = 2.65 pF, were used in a simulation of the CMOS range obtained if we select 60 deg as the nominal condi-
opamp of Fig 5. The results indicated good cancellation of tion. The improvement is typically a factor of two. This
the pole-zero doublet, and a unity-gain phase margin of argument obviously applies for temperature variations as
67.6 deg which is an error of less than four percent relative
well.
to the ideal 70-deg phase margin. For comparison, the In practical SC circuits, the load capacitance is not
previous technique yielded a phase margin of 84 deg giving constant during the two clock phases. The question then
a 20-percent error. With some minor empirical adjustment, naturally arises as to how the MST compensation applies
the 70-deg phase margin, and thus the MST response for to this situation. First of all, t h s situation always exists
D = 0.01 is achieved with Rf =17 kQ and C, = 2.9 pF. regardless of the specific compensation technique. Sec-
The simulation results of the step responses for the 70-degondly, in high-speed SC circuits, it is normally assumed
MST and the commonly-used 60-deg phase margin re- that the output of the SC integrator is being sampled
sponses are shown in Fig. 15. It is seen that the MST during the integration phase. Hence, the loading capaci-
response, (the first peak of the response touches the uppertance during the integration phase should be used in
error limit), reduces the settling time considerably as com-
frequency response and compensation calculations.
pared with the 60-deg phase margin case even though a The effect on settling time of large-signal slew-rate limit-
slightly larger compensation capacitance is required to ing is currently under investigation, and will be published
achieve the larger phase margin. later. We are somewhat justified in neglecting slew-rate
effects in many applications. Using conventional two-stage
IV. DISCUSSION AND CONCLUSIONS
or cascode opamps, slew-rate effects may be ignored for
One potential concern relates to the sensitivity of the cases wherein the maximum output voltage change during
MST response to process variations. Variations in the any sampling period is less than about 500 mV. For
phase margin were simulated with standard process varia- high-frequency CMOS SC filters, either class AB or adap-
tions about both the MST and nominal 60-deg cases. The tively-biased [15]-[19] opamps may be used as they do not
334
exhibit slew-rate limiting, and therefore, small-signal anal-
ysis is applicable.
A frequency compensation technique for fast settling
opamps has been presented, and an improved equivalent
circuit model for a two-stage opamp was also proposed.
The results show that for a first-stage dominant-pole sys-
tem, the Miller capacitance approximation is appropriate
whereas for the second-stage dominant-pole system, the
Miller resistance approximation is required. This improved
modeling not only provides for much more accurate com-
pensation, but also improves the understanding of pole-
splitting compensation. The minimum small-signal settling
time analysis is also applicable to the optimization of
one-stage two-pole opamps [201-[ 221.
ACKNOWLEDGMENT
The authors gratefully acknowledge the early contribu-
tions of Jeffery R. Ireland to this work. Helpful sugges-
tions from Prof. G.C. Temes of UCLA are greatly appreci-
ated. Special thanks are due V. G. Allstot for her efforts in
preparing the figures.
REFERENCES
[l] P. R. Gray and R. G. Meyer, Analysis and Design of Analog
Integrated Circuits, 2nd ed., New York: Wiley, 1982.
[2] S. Rosenstark, Feedback Amplifier Principles. New York: Macmil-
lan, 1986.
[3] B. Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationshp
between frequency response and settling time of operational ampli-
fiers,” IEEE J . Solid-State Circuits, vol. SC-9, pp. 347-352, Dec.
1974.
[4] R. J. Apfel and P. R. Gray, “A fast-settling monolithic operational
amplifier using doublet compression techniques,” IEEE J . Solid-
State Circuits, vol. SC-9, pp. 332-340, Dec. 1974.
[5] C. T. Chuang, “Analysis of the settling behavior of an operational
amplifier,” IEEE J . Solid-State Circuits, vol. SC-17, pp. 74-80.
Feb. 1982.
J. C. Lin and J. H. Nevin, “A modified time-domain model for
nonlinear analysis of an operational amplifier,” IEEE J . Solid-State
Circuits, vol. SC-21,. pp. 478-483, June 1986.
J. E. Solomon, “The monolithic op-amp: A tutorial study,” IEEE
J . Solid-State Circuits, vol. SC-9, pp. 314-332, Dec. 1974.
P. R. Gray and R. G. Meyer, “MOS operational amplifier
design-A tutorial overview,” IEEE J . Solid-State Circuits, vol .
SC-17, pp. 969-982, Dec. 1982.
[91 S. D. Jen, H. C. Yang, and D. J. Allstot, “Operational amplifier
compensation using doublet-decompression for switched-capacitor
circuits,” in Proc. 31st IEEE Midwest Svmp. on Circuits and
Systems, pp. 4-6, Aug. 1988.
H. C. Yang, J. R. Ireland, and D. J. Allstot, “Improved operational
amplifier compensation techniques for high-frequency switched-
capacitor circuits,” in Proc. 30th IEEE Midwest Symp. on Circuits
and Systems, pp. 952-955, Aug. 1987.
R. Gregorian and G. C. Ternes, Analog M U S Integrated Circuitsfor
Signal Processing. New York: Wiley, 1986.
W. C. Black, Jr., D. J. Allstot, and R. A. Reed, “A high perfor-
mance low power CMOS channel filter,” IEEE J . Solid-Stute
-.
Circuits. vol. SC-15. DD. 929-938.
.- Dec -.
- 1980
[13] P. E. Allen &d D.‘k. Holberg, C M O S Analog Circuit Design,
New York: Holt, Rinehart and Winston, 1987.
[14] H. C. Yang and D. J. Allstot, “An equivalent circuit model for
two-stage operational amplifiers,” in proc. IEEE Int. Svmp. on
Circuits and Systems, pp. 635-638, June 1988.
[15] R. Castello and P. R. Gray, “A hgh-performance micropower
switched-capacitor filter,,. IEEE Solid-State Circuits,
J , sc-20,
pp. 1122-1132, Dec. 1985.
[16] s. H. ~~~i~ and p, R, G ~ “pipelined~ ~ 5, ms/s 94,it analog-to-dig-
ita1 converter,” IEEE J . Solid-State Circuits, vol. SC-22, PP.
954-961, Dec. 1987.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL. 37, NO. 3, MARCH 1990
C. Yu. J. J. Yane. and D. J. Allstot. “A hi&-swine class-AB CMOS
operational am$fier,” in Proc. IEEE I;. S y m i . on Circuits and
Svstems, pp. 151-154, June 1988.
M. G. Degrauwe, J. Rigmenants, E. A. Vittoz, and H. J. DeMan,
“ AdaDtive biasing CMOS amDlifiers.” IEEE J . Solid State Circuits,
vol. SC-17, pp. 522-528, June 1982.
T. S. Fiez and D. J. Allstot, “A hgh-swing adaptively-biased
CMOS amplifier,” in Proc 31st IEEE Midwest Symp on Circuits
and Systems, pp. 852-854, Aug. 1988.
M. A. Abu-Dayyh, “A fast-settling folded-cascode CMOS opera-
tional amplifier, Master’s thesis, Dept. Elect. Comput. Eng., Ore-
gon State Univ., 1988.
C. Toumazou, D. G. Haigh, and 0. Richards, “Fast settling GaAs
operational amplifiers for switched capacitor applications,” in Proc.
IEEE Int. Symp. on Circuits and Systems, pp. 659-662, May 1989.
M. A. Abu-Dayeh, H. C. Yang, and D. J. Allstot, “Analysis and
design of a fast-settling folded-cascode CMOS operational ampli-
fier for switched-capacitor applications,” in Proc. 32nd IEEE Mid-
west Symp. on Circuits and Svsrems, Aug. 1989.
rIc
Howard C. Yang (S’87-M90) received the M.S.
and the Ph.D. degrees in electrical engineering
from Oregon State University in 1986 and 1989,
respectively.
From 1984 to 1989, he was a graduate research
assistant at Oregon State University working on
GaAs photodetectors and CMOS and GaAs ana-
log integrated circuits. In 1990, he joined Na-
tional Semiconductor, Santa Clara, CA, as a
Senior Circuit Design Engineer, where he is cur-
rently working on CMOS and BiCMOS analog
IC design.
Dr. Yang is a membe:r of Sigma Xi.
David J. Allstot (S’72-M78-SM83) received the
B.S.E.S. degree from the University of Portland,
the M.S.E.E. degree from Oregon State Univer-
sity, and the Ph.D. degree in electrical engineer-
ing and computer sciences, from the University
of California, Berkeley.
From 1973 to 1975, he was with Tektronix,
Inc. in the Digital IC Design Group. From 1975
to 1979, he served as a Graduate Research assis-
tant, Acting Assistant Professor, and IBM Doc-
toral fellow in the EECS Department at the
University of California, Berkeley. Between 1979 and 1981, he held
positions-at Texas Instruments, Inc. and MOSTEK, Inc. Since 1981, he
has been involved in private consulting. He served as an Adjunct Assis-
tmt Professor at Southern Methodist University from 1981 to 1984. In
1985-1986, he was the Visiting MacKay Lecturer at UC Berkeley, and in
1986 he joined the Department of Electrical and Computer Engineering
at Oregon State University where he is currently an Associate Professor.
Dr. Allstot was a co-recipient of the 1980 IEEE W. R. G. Baker Award,
and recipient of the 1988 Carter Award for outstanding teaching from the
College of Engineering at Oregon State University. He is a member of
Eta Kappa Nu and Sigma Xi.