Introduction to VLSI Design, VLSI I, Fall 2010

11. Sequential Elements 1

mm 40 60 80 100 120

40
11. Sequential Elements

J. A. Abraham

Department
60 of Electrical and Computer Engineering
The University of Texas at Austin
EE 382M, VLSI I
Fall 2010
80
October 4, 2010

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 1 / 39

Floor Plan
MIPS Floorplan
How mm
do you 40 60 80 100 120
estimate block
areas?
Begin with
block diagram
40
Each block has
Inputs
Outputs
Function
Type: array,
60
datapath,
random
logic
Estimation
depends
80 on type
of logic

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 1 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 2

Area Estimation

mm 40 60 80 100 120
Arrays
Layout basic cell
Calculate core area from number of cells
Allow area for decoders, column circuitry
40
Datapaths
Sketch slice plan
Count area of cells from cell library
Ensure wiring is possible
60
Random Logic
Compare complexity do a design you have done
For design in a new technology, estimate from scaling design in
the old technology
80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 2 / 39

MIPS Slice Plan

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 3 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 3

Typical Layout Densities

mm
Typical number
40 of high quality
60 layout 80
given below100 120
Derate by 2 for class projects to allow routing and some
sloppy layout
Allocate space for big wiring channels
40
Element Area
Random logic (2 metal layers) 1000 – 1500 λ2 /transistor
Datapath 250 – 750 λ2 /transistor
60
or, 6W L + 360λ2 /transistor
SRAM 1000 λ2 /bit
DRAM 100 λ2 /bit
80
ROM 100 λ2 /bit

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 4 / 39

Sequencing

Combinational
mm 40 logic 60 80 100 120
Output depends on current inputs
Sequential logic
Output depends on current and previous inputs
40 Requires separating previous, current, future
Called state or tokens
Example, Finite-State Machine (FSM), pipeline

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 5 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 4

Sequencing, Cont’d

mm 40 60 80 100 120
If tokens moved through pipeline at constant speed, no
sequencing elements would be necessary
Example, fiber-optic cable
40 Light pulses (tokens) are sent down cable
Next pulse sent before first reaches end of cable
No need for hardware to separate pulses
But dispersion sets min time between pulses
This
60 is called wave pipelining in circuits
In most circuits, dispersion is high
Delay fast tokens so they don’t catch slow ones

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 6 / 39

Sequencing Overhead

mm 40 60 80 100 120

Use flip-flops to delay fast tokens so they move through

exactly one stage each cycle
40
Inevitably adds some delay to the slow tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead
60 But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 7 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 5

Sequencing Elements

Latch: Level sensitive

mm Also called
40 transparent60latch, D latch
80 100 120
Flip-Flop: Edge triggered
Also called master-slave flip-flop, D flip-flop, D register, D Flop

40

Timing Diagrams
60Transparent
Opaque
Edge-trigger

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 8 / 39

Latch Designs

mm 40 60 80 100 120
Pass Transistor Latch

+ Tiny
+ Low
40 clock load
– Vt drop Used in the 1970s
– Non-restoring
– Back driving
60
– Output noise sensitivity
– Dynamic
– Diffusion input
80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 9 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 6

Latch Designs, Cont’d

Transmission Gate Latch
mm 40 60 80 100 120
+ No Vt drop
– Requires inverted clock

40
Inverting Buffer Latch

+ Restoring
60
+ No Backdriving
+ Fixes either
Output noise sensitivity
80 Or diffusion input
– Inverted output

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 10 / 39

Latch Designs, Cont’d

Latch with Tristate Feedback

mm 40 60 80 100 120

+ Static
– Backdriving risk
Static
40 latches are now
essential

Latch with Buffered Input

60

+ Fixes diffusion input

+ Non-inverting
80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 11 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 7

Latch Designs, Cont’d

Latch with Buffered Output

mm used in40standard cells

Widely 60 80 100 120
+ No backdriving
+ Very robust (most important)
– Rather large
40
– Rather slow (1.5 – 2 FO4 delays)
– High clock loading

Datapath
60 Latch

+ Smaller, faster
-80Unbuffered input

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 12 / 39

Flip-Flop Design
Flip-flop is built as a pair of back-to-back latches
mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 13 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 8

Enable
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay
mm Clock Gating:
40 increase60 80 skew
en setup time, 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 14 / 39

Reset
Force output low when reset asserted
Synchronous vs. asynchronous
mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 15 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 9

Set/Reset

mm 40 60
Set forces output high when enabled 80 100 120

Flip-flop with asynchronous set and reset

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 16 / 39

Sequencing Methods

mm 40 60 80 100 120

Flip-Flops

40

2-Phase Trans-
parent Latches
60

Pulsed Latches
80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 17 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 10

Timing Diagrams

mm 40 60 80 100 120

Contamination and
Propagation Delays
tpd
40
Logic Propagation Delay
tcd Logic Contamination Delay
tpcq Latch/Flop Clk-Q Prop. Delay
tccq Latch/Flop Clk-Q Cont. Delay
tpdq Latch D-Q Prop. Delay
tcdq
60
Latch D-Q Cont. Delay
tsetup Latch/Flop Setup Time
thold Latch/Flop Hold Time

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 18 / 39

Example: Master-Slave Flip Flop

mm 40 60 80 100 120

40

60

tsetup =
80 tpcq =
thold =

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 19 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 11

Maximum Delay: Flip-Flops

tpd ≤ Tc − (tsetup + tpcq )

mm 40 60 | {z 80 } 100 120
sequencing overhead

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 20 / 39

Maximum Delay: 2-Phase Latches

tpd = tpd1 + tpd2 ≤ Tc − (2tpdq )
| {z }
mm 40 60 sequencing
80 100 120
overhead

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 21 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 12

Maximum Delay: Pulsed Latches

tpd ≤ Tc − max(tpdq , tpcq + tsetup − tpw )

mm 40 | 60 {z 80 } 100 120
sequencing overhead

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 22 / 39

Minimum Delay: Flip-Flops

tcd ≥ thold − tccq

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 23 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 13

Minimum Delay: 2-Phase Latches

mm tcd1
40, tcd2 ≥ thold
60 − tccq − tnonoverlap
80 100 120

Hole
40 time reduced
by nonoverlap
Paradox: hold
applies twice each
cycle,
60 versus only
once for flops
But a flop is
made of two
latches!
80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 24 / 39

Minimum Delay: Pulsed Latches

tcd ≥ thold − tccq + tpw

mm 40 60 80 100 120
Hold time increased by pulse width

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 25 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 14

Clock Skew

We have assumed
mm 40 zero clock
60 skew 80 100 120
Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing
40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 26 / 39

Skew: Flip-Flops

mm 40 60 80 100 120
tpd ≤ Tc −(tpcq + tsetup + tskew )
| {z }
sequencing overhead

40
tcd ≥ thold − tccq + tskew

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 27 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 15

Skew: Latches

mm 40 60 80 100 120

40

2-Phase Latches
tpd ≤ Tc 60
− (2tpdq ) Pulsed Latches
| {z } tpd ≤ Tc −
sequencing
overhead max(tpdq , tpcq + tsetup − tpw + tskew )
| {z }
tcd1 , tcd2 ≥ sequencing overhead
thold − tccq80 − tnonoverlap + tskew tcd ≥ thold + tpw − tccq + tskew
tborrow ≤ tborrow ≤ tpw − (tsetup + tskew )
Tc /2 − (tsetup + tnonoverlap + tskew )
ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 28 / 39

Two-Phase Clocking

If setup times are violated, reduce clock speed

If hold times 40
mm are violated,60chip fails at80any speed 100 120
Use tools to analyze clock skew
Easy way to guarantee hold times: use 2-phase latches with
big non-overlap times (used in academic designs)
40 these clocks φ , φ (ph1, ph2)
Call 1 2

Safe Flip-Flop
Flip-Flop with
non-overlapping
60 clocks
Very slow – nonoverlap
adds to setup time, but
no hold time problem
Use timing
80 analysis and
add buffers to slow signals
if hold time is at risk
ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 29 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 16

Summary

Flip-Flops 40
mm 60 80 100 120
Very easy to use, supported by all tools
2-Phase Transparent Latches
Lost of skew tolerance and time borrowing
Pulsed
40 Latches
Fast, some skew tolerance and borrowing, hold time risk
Sequencing overhead Minimum logic de- Time borrowing
(Tc − tpd ) lay (tcd ) (tborrow )
Flip-flops60 tpcq + tsetup + tskew thold − tccq + tskew 0
Tc
Two-phase trans- 2tpdq thold − tccq − 2
− (tsetup +
parent latches tnonoverlap +tskew tnonoverlap +
in each half-cycle tskew )
Pulsed latches max(tpdq , tpcq + thold −tccq +tpw + tpw − (tsetup +
80 tsetup − tpw + tskew ) tskew tskew )

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 30 / 39

High Performance Flops

The modified Svensson latch, DEC Alpha 21064

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 31 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 17

High Performance Flops, Cont’d

The amplifier-based flip-flop

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 32 / 39

High Performance Flops, Cont’d

The mm
hybrid latch flip-flop
40 of AMD
60 K6 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 33 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 18

Basic Flop in AMD Athlon Processor

Clock pulse is generated using monoshots at the rising edge
mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 34 / 39

High Performance Flops, Cont’d

The enabled two-way MUX pulsed flip-flop of K7

mm 40 60 80 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 35 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 19

Cycle Stretching

mm 40 60 80 100 120

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60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 36 / 39

Fixing Hold-Time Violations

mm 40 60 80 100 120

Measure all hold times with respect to the main clock

40
Adjust the hold time if the flop is receiving a delayed clock
Compute the shortest path delay from the rising edge of the
clock
Check to see if there are any hold time failures
60

80

ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 37 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010
 Introduction to VLSI Design, VLSI I, Fall 2010
11. Sequential Elements 20

Example: Fixing Hold-Time Violations

mm 40 60 80 100 120

40

60
Shortest path delay from A → E = 100 + 40 + 40 + 20 = 200 ps
Delay between CLK1 and CLK = 50 ps
Adjusted hold time = 200 + 50 = 250 ps
Hold Slack = (Path Delay) − (Adjusted Hold Time) = 200 − 250
80
= −50 ps
=⇒ FAIL (Hold slack should be ≥ 0)
ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 38 / 39

Example: Fixing Hold-Time Violations, Cont’d

mm 40 60 80 100 120

40

Insert 4 inverters after D, with each adding a 20 ps

60
(or can insert one AND gate)
Long path (4 invs.) = 100 + 50 + 50 + 20 + 80 + 10 = 310 ps
Now the minimum cycle time at which the path can operate =
(Path80Delay) − (CLK → CLK1 Delay) = 310 − 50 = 260 ps
If possible, add the additional delay to fix hold time violations in
the short path (without affecting the long paths)
ECE Department, University of Texas at Austin Lecture 11. Sequential Elements J. A. Abraham, October 4, 2010 39 / 39

Department of Electrical and Computer Engineering, The University of Texas at Austin

J. A. Abraham, October 4, 2010