IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
9, SEPTEMBER 2006
A 120-MHz–1.8-GHz CMOS DLL-Based Clock
Generator for Dynamic Frequency Scaling
Jin-Han Kim, Student Member, IEEE, Young-Ho Kwak, Student Member, IEEE,
Mooyoung Kim, Student Member, IEEE, Soo-Won Kim, and Chulwoo Kim, Senior Member, IEEE
Abstract—A delay-locked loop (DLL)-based clock generator
for dynamic frequency scaling has been developed in a 0.35- m
CMOS technology. The proposed clock generator can generate
clock signals ranging from 120 MHz to 1.8 GHz and change the
frequency dynamically in a short time. If the clock generator scales
its output frequency dynamically by programming with the same
last bit, it takes only one clock cycle to lock. In addition, the clock
generator inherits advantages of a DLL. The proposed DLL-based
clock generator occupies 0.07 mm2 and has a peak-to-peak jitter
of 6.6 ps at 1.3 GHz.
Index Terms—Clock generator, delay-locked loop (DLL), DLL-
based frequency multiplication, fast lock, low jitter.
I. INTRODUCTION
C OMPARED to most phase-locked-loop (PLL)-based clock
generators and local oscillators [1]–[9], delay-locked loop
(DLL)-based counterparts exhibit less jitter and phase noise be-
cause of no jitter accumulation. This is true even under severe
supply noise which is becoming common and critical in many
SoCs. Furthermore, they show stable operation with process,
voltage and temperature (PVT) variations, are easier to design,
and occupy smaller area due to a simpler loop filter [10]–[13].
Recently, several DLL-based clock generators and a local oscil-
lator have been proposed to overcome the difficulty of frequency
multiplication with DLLs and utilize the several inherent ad-
vantages of DLLs over PLLs [10]–[14]. The DLL-based local
oscillator for PCS applications consumes large power and area
and the frequency multiplication factor cannot be changed once
the LC-tank value is chosen [10]. The frequency synthesizer in
[11] multiplies input clock frequency by a fixed multiplication
factor, 9, and generates a 1-GHz off-chip clock signal with an
external 50- pull-up resistor [11]. The multiplying DLL pro-
posed in [12] uses multiplexers (MUXes) which cause jitter due
to a fixed supply voltage. In addition, the duty cycle of the fre-
quency multiplied output clock is not 50% which is required
in many high-performance applications. The DLL-based clock
generator proposed in [13] provides a low-jitter on-chip clock
signal with a variable multiplication factor. Its frequency-mul-
tiplied output clock has a 50% duty cycle even with a non-50%
duty cycle input. It also overcomes the limited locking range
Manuscript received August 24, 2005; revised April 20, 2006. This work
was supported by Grant R08-2003-000-10899-0 from the Basic Research Pro-
gram of the Korea Science and Engineering Foundation and IT-SOC Promotion
Group.
The authors are with the Department of Electronics Engineering, Korea Uni-
versity, Seoul 136-713, Korea (e-mail:ckim@korea.ac.kr).
Digital Object Identifier 10.1109/JSSC.2006.880609
0018-9200/$20.00 © 2006 IEEE
2077
of DLLs. However, large internal node capacitances of the fre-
quency multiplier limit the operating speed of the clock gen-
erator. Finally, the multiplying DLL (MDLL) in [14] was pro-
posed to be highly integrated in clock and data recovery unit,
of which the high-frequency portion of jitter can be filtered out
by injection locking using a slave oscillator. The multiplication
factor of the MDLL can be changed from 1 to 10.
In this paper, a DLL-based clock generator is demonstrated
in a 0.35- m CMOS technology. The proposed clock generator
can multiply input frequency dynamically, which enables dy-
namic voltage scaling and can increase the maximum operating
frequency owing to the proposed frequency multiplier. The pro-
posed frequency multiplier has small internal node capacitances
and is controlled by simple enabling logic circuits. As a result,
the generator can operate from 120 MHz to 1.8 GHz with var-
ious input signals and multiplication factors. Hence, the pro-
posed clock generator can be used in clock and data recovery
applications or in a dynamic frequency scaler in microproces-
sors, which needs a fast lock during frequency change.
This paper is organized as follows. Section II briefly
overviews the architecture of proposed frequency multiplier.
Section III presents the circuit implementation of the frequency
multiplier concretely. The proposed frequency multiplier
consists of transition detector and edge-combiner. Section IV
describes the operation of DLL-based clock generator using the
proposed frequency multiplier for dynamic frequency scaling.
Experimental results, die photo, and performance comparisons
to previous works are shown in Section V.
II. ARCHITECTURE OF PROPOSED FREQUENCY MULTIPLIER
To overcome the problems of conventional DLL-based clock
generators, we have proposed a new one. The key idea of
the proposed DLL-based clock generator is shown in Fig. 1.
The architecture of the proposed DLL-based clock generator
features a programmable multiplication factor controller and
a high-frequency frequency multiplier. The buffered outputs
of the voltage-controlled delay line (VCDL) are applied to the
inputs of the frequency multiplier. The multiplication factor
controller generates select signals for both the MUX and the
transition detector. Appropriate phases for DLL locking are
selected by the MUX. Whenever each buffered VCDL output
rises, the transition detector generates a short period pulse,
as shown in Fig. 2. The edge combiner puts the short pulses
together and toggles the phase of output at every negative
edge of the short pulses. Thus, the multiplier output clock
signal toggles at every rising edge of signal . Fig. 2 shows
an example of frequency multiplication by two. Even though
the duty cycle of signals is not 50%, the output clock signal
2078
Fig. 1. Block diagram of DLL-based clock generator.
Fig. 2. Waveforms of frequency multiplication by two.
does toggle at 50% duty cycle because each virtual pulse is
generated at every rising edge of the signals. If the VCDL
has delay cells, then the output clock frequency can be
expressed as
(1)
where is the frequency of the reference signal and the
multiplication factor can be chosen dynamically by the
multiplication factor controller.
III. CIRCUIT IMPLEMENTATION OF FREQUENCY MULTIPLIER
To enhance the operating frequency of the frequency
multiplier while maintaining dynamic programmability, the
frequency multiplier is proposed as shown in Fig. 3. The circuit
implementation of each block is as follows. First, the transition
detector consists of three inverters and a three-input NAND
gate as shown in Fig. 3. Enable signals ( ) for adjusting the
multiplication factor are fed to the NAND gates. Each buffered
VCDL output ( ) is then fed to a NAND gate and three inverters
at the same time. If signal rises, one input of a NAND gate
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
2
Fig. 3. Block diagram of proposed frequency multiplier ( 4).
Fig. 4. Simulated waveform which shows the signal propagation failure at
1.6 GHz without signal ordering in the edge-combiner.
will arrive faster than the other which comes after three-inverter
delay. As a result, at the rising edge of output of buffer, the
NAND gate generates the negative narrow pulse corresponding
to the three-inverter delay. Second, the edge-combiner consists
of symmetric NANDs, inverters, and a toggle pulsed latch (TPL).
The negative pulses are transferred through three stages of
two-input AND gates which is constructed by a symmetric
NAND and an inverter. Node A results in an AND operation of
the negative pulses. Therefore, whenever any buffered VCDL
output feeds the transition detector, a short pulse is generated
at node A. Finally, the TPL toggles its output signal as long
as the negative pulse is generated at node A. If a pulse signal
propagating through the edge combiner arrives at a certain
internal node during the transition time of a previous pulse
signal, a malfunction may occur, which limits the operation
frequency of the edge combiner. To prevent this problem,
the number of fan-in of a symmetric NAND gate is limited to
two. In addition, outputs of the transition detector are paired
to guarantee maximum pulse separation as shown in Fig. 3,
which reduces signal transition overlap and increases the op-
erating frequency of the frequency multiplier by 15%. Fig. 4
shows the failing case when the transition detector outputs
are connected without signal ordering to the edge combiner.
If two pairs of adjacent inputs, ( and ) and ( and ),
feed to NAND gates and , respectively, overlap between
adjacent signals reduces the voltage levels of nodes x and y.
In the same manner, voltage reduction and overlap in nodes x
and y results in voltage level degradation of node i. As a result,
KIM et al.: A 120-MHZ–1.8-GHZ CMOS DLL-BASED CLOCK GENERATOR FOR DYNAMIC FREQUENCY SCALING
Fig. 5. Edge-combiner circuits. (a) Symmetric NAND. (b) TPL.
Fig. 6. Detailed block diagram of DLL-based clock generator.
pulses at node A are not generated properly. Fig. 5 shows the
circuit implementation of edge-combiner. Each component was
controlled by the regulated supply for supply noise suppression.
A pull-down path of a symmetric NAND gate is divided into
two paths and input connections are switched for symmetric
short propagation. The operation of TPL is as follows. During
the short pulse width, the nMOS pass transistor turns on and
transmits input data ( ) to output. Furthermore, the output is
inverted and fed back to input data until next pulse is triggered.
Consequently, TPL can be considered a toggle-edge-triggered
flip-flop. The pMOS transistor (M1) of TPL prevents internal
node X from voltage drop of . Also, it provides a negative
setup time when input data changes from logic “Low” to logic
“High”. The increased size of the nMOS pass transistor can
have a better drive strength at node X than the equivalent size
of transmission gate. Thus, the total propagation time through
TPL determines the maximum frequency of the frequency mul-
tiplier. Because data transfers through only an nMOS transistor
and three inverters, the frequency multiplier maintains dynamic
frequency programmability and operates at high frequency
compared to the frequency multiplier in [4], which suffers from
large internal node capacitance.
IV. DLL-BASED CLOCK GENERATOR
Fig. 6 shows the overall block diagram of the frequency
multiplier for dynamic frequency scaling. The proposed
2079
Fig. 7. Schematics of (a) charge-pump circuit, (b) charge-pump bias circuit,
and (c) voltage regulator.
DLL-based clock generator was implemented in a 0.35- m
single-poly four-metal CMOS process with a 3.3-V supply.
The phase detector (PD) with reset circuitry has increased the
locking range by initial condition as proposed in [12]. The
lock range for the DLL is from 240 to 500 MHz. A charge
pump with replica bias controls the charge pump current for
adaptive bandwidth. Schematics of a charge pump and its bias
circuit are shown in Fig. 7. The charge pump is similar to that
introduced in [15] and can make the voltages of nodes
and n1 equal. Then the offset is canceled. The bias current is
controlled by the last bit, which was compared through PD
as shown in Fig. 7(b). The bandwidth is determined by the
VCDL gain ( ) and charge pump current. The VCDL gain
is inversely proportional to charge pump current. Therefore,
as the position of the last bit decreases, the VCDL gain will
be reduced, and the charge pump current should be reduced to
maintain the bandwidth. Delay of VCDL is controlled by the
regulated supply voltage. The regulator consists of a two-stage
current mirror as shown in Fig. 7(c) [16]. The bandwidth of the
regulator was controlled by the bias voltage of . Thus, the
regulated voltage swing results in the adaptive bandwidth ac-
cording to input frequency and independent of the supply noise.
Finally, there are the MUX and the frequency multiplier. The
MUX selects the last bit which connects to the PD according
to the control signal. Hence, the selected number of delay
cell outputs determines the maximum frequency of multiplied
output by (1). For example, if the multiplication factor is 3 in
2080 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006

Fig. 9. Input and multiplied output.

Fig. 8. Dynamic frequency multiplication example, where D represents

“disable”.

Fig. 8, the MUX selects the output of the sixth tap as the last bit
and the number of delay cell is six. The maximum frequency
of multiplied output is input frequency . In addition, if
the multiplication factor controller enables the first, third, and
fifth transition detectors, the frequency of the multiplied output
will be halved: input frequency . Therefore, when the
frequency multiplier scales its output frequency dynamically by
Fig. 10. Jitter histogram of the output.
programming with the same last bit, it takes only one cycle time
for locking, which is critical for dynamic power management
for system-level power reduction. Other combinations marked
in gray in Fig. 8 can be chosen, but in those cases, some cycle
time is wasted before the multiplied output clock is generated.
For example, if the multiplication factor is changed from 1 to
2 with the last bit of 8 and the multiplication factor controller
enables the second transition detector instead of the third, the
first multiplied pulsewidth is narrower than desired and should
be discarded.
To reduce static phase offset and mismatch of delay path, the
replica bias charge pump and dummy delay cells in the VCDL
are used. Furthermore, a symmetric NAND gate is used in the
phase detector and layout of the proposed clock generator was
carefully done to reduce mismatch.
Fig. 11. Dynamic frequency scaling example (from 1.6 GHz to 400 MHz and
then to 800 MHz).
V. EXPERIMENTAL RESULT
Input and output waveforms of the frequency multiplier
are shown in Fig. 9. The measured waveforms of Fig. 9 show Inside the chip, the sinusoidal input signal becomes a square
a 1.3-GHz frequency multiplier output from an input refer- wave after passing through several buffers and then feeds the
ence frequency of 325 MHz, giving a multiplication factor of DLL-based clock multiplier. The measured output waveform
four. The measured sinusoidal input signal is the output of looks triangular due to the weak driving capability of the output
a signal generator which feeds the device under test (DUT). driver. The measurement result with a quiet supply shows
KIM et al.: A 120-MHZ–1.8-GHZ CMOS DLL-BASED CLOCK GENERATOR FOR DYNAMIC FREQUENCY SCALING
Fig. 12. Performance comparison of the DLL-based frequency multipliers.
Fig. 13. Die photo.
peak-to-peak jitter of 6.6 ps and rms jitter of 1.8 ps in Fig. 10.
Fig. 11 shows that the frequency multiplier output changes
from 1.6 GHz to 400 MHz and then to 800 MHz with one cycle
lock time. The minimum and maximum multiplied output fre-
quencies are 120 MHz and 1.8 GHz with input frequencies of
240 MHz and 450 MHz, respectively. The triangles in Fig. 12
are simulated maximum operating frequency of the proposed
multiplier featuring programmability for dynamic frequency
scaling. The proposed clock multiplier increases the operating
frequency significantly in a given technology as shown in
Fig. 12. The clock generator die photo is shown in Fig. 13.
The clock generator occupies 0.07 mm in a 0.35- m CMOS
process. The performance of the implemented clock generator
is summarized in Table I.
2081
TABLE I
PERFORMANCE SUMMARY
VI. CONCLUSION
In this paper, a DLL-based clock generator for dynamic fre-
quency scaling was proposed. This clock generator has been
designed in a 0.35- m CMOS process and could increase the
maximum operating frequency owing to the proposed frequency
multiplier. The proposed frequency multiplier has small internal
node capacitances and was controlled by simple enabling logic
circuits. As a result, the generator can operate from 120 MHz
to 1.8 GHz with various input signal and multiplication factors.
Since the multiplied output was made from each rising input
signal, output signal maintain 50% duty cycle ratio independent
of duty cycle ratio of the input signal. In addition, with plain dig-
ital logic for frequency adjustment, the multiplication factor can
be changed dynamically with fast lock time. In case of the same
last bit, it takes only one-cycle to lock during frequency scaling.
Since the DLL includes the voltage regulator and replica bias,
the generator can suppress the supply noise and have adap-
tive bandwidth. The implemented DLL-based clock generator
shows that for a reference signal of 325 MHz and a multipli-
cation factor of four, the measured peak-to-peak cycle-to-cycle
jitter is 6.6 ps at 1.3 GHz. The proposed clock generator can
be used in clock and data recovery applications or in dynamic
2082
frequency scalers for low-power microprocessors which need a
fast lock during frequency change.
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Jin-Han Kim (S’04) received the B.S. and M.S. de-
grees in electronics engineering from Korea Univer-
sity, Seoul, Korea, in 2002 and 2005, respectively,
where he is currently working toward the Ph.D. de-
gree in electronics and computer engineering.
His research interests are in PLL/DLL design for
high-speed communications and panel display driver
IC design.
Mr. Kim was the recipient of the IEEE Seoul Sec-
tion Student Paper Contest Award in 2004.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006
Young-Ho Kwak (S’04) received the B.S. degree
in electronics engineering from Korea University,
Seoul, Korea, in 2004, where he is currently working
toward the Ph.D. degree in electronics and computer
engineering.
His research interests are in clock and data re-
covery for high-speed communications, high-speed
serial link, and PLL design.
Mr. Kwak was the recipient of the IEEE Seoul Sec-
tion Student Paper Contest Award in 2005.
Mooyoung Kim (S’04) received the B.S. degree
in electrical computer engineering from Korea
University, Seoul, Korea, in 2004, where he is
currently working toward the Ph.D degree in the area
of integrated circuits and systems.
His research interests include mixed-mode circuit
and system design.
Soo-Won Kim received the B.S. degree in electronics
engineering from Korea University, Seoul, Korea, in
1974, and the M.S. and Ph.D. degrees in electrical en-
gineering from Texas A&M University, College Sta-
tion, in 1983 and 1987, respectively.
He joined the Department of Electronics Engi-
neering at Korea University as an Assistant Professor
in 1987. Since 1989, he has been a Professor in
Department of Electronics Engineering at Korea
University, Korea. His research area is in design
of mixed mode IC, RF PLL, and high-speed and
low-power digital systems.
Chulwoo Kim (S’98-M’02-SM’06) received the
B.S. and M.S. degrees in electronics engineering
from Korea University, Seoul, Korea, in 1994 and
1996, respectively, and the Ph.D. degree in electrical
and computer engineering from the University of
Illinois at Urbana-Champaign in 2001.
While at the University of Illinois, during
1997–2000, he was a research assistant with the
Coordinated Science Laboratory. In 1999, he also
worked as a summer intern at the Design Technology
at Intel Corporation, Santa Clara, CA. In May
2001, he joined IBM Microelectronics Division, Austin, TX, where he was
involved in Cell processor design. Prior to joining IBM, he was a Research
Staff Member with the University of California, Santa Cruz, CA, in 2001.
Since September 2002, he has been with the Department of Electronics and
Computer Engineering, Korea University, where he is currently an Assistant
Professor. His current research interests are in the areas of wireline transceiver,
high-speed I/O, PLL/DLL, dynamic power management, and network on chip.
Dr. Kim received the HumanTech Thesis Contest Bronze Award from Sam-
sung Electronics Corporation (1996), the International Low-Power Design Con-
test Award at the IEEE International Symposium on Low-Power Electronics and
Design (2001), the Design Automation Conference (DAC) Student Design Con-
test Award (2002), and Semiconductor Research Corporation (SRC) Inventor
Recognition Award (2002).