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Display Research Lab

Flexible Display –
AMOLED on Metal Foils
T.K. Chuang, M. Trocolli, A. Jamshidi Roudbari, G. Reed, Y.L. Chang, P.C. Kuo, and M. Hatalis
(Display Research Laboratory, Lehigh University)
J. Spirko, K. Klier, S. Preis, Xiaohan Zhang, R. Pearson, H. Najafov, and I. Biaggio
(Lehigh University)

T. Afentakis and A. Voutsas

(Sharp Labs of America, Camas, WA)

E. Forsythe, J. Shi, and S. Blomquist

(U.S. Army Research Laboratory, Adelphi, MD) 19th May 2005 (COT Open House)
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Display Research Lab

Outline
Introduction
Metal Foils Preparations
Surface Polishing
Deposition and Testing of Insulating Layers
Polymeric Top-Emitting Diodes
Architecture and Fabrication of PLEDs
Characterization of PLEDs
Encapsulation and Testing/Analysis
Poly-Si TFT Backplanes and Poly-Si TFT Performance
Electronics:
Ring Oscillators
Shift Registers
OLED TFT Pixels
Display Testing and Driving Approaches
Conclusions
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Display Research Lab

Why it needs to be metal foils?

Present Future

• Bulky • Low Profile

• Heavy • Light Weight
• Fragile • Rugged
• High Power • Low Power
• Rigid • Flexible
• High Performance • High Performance

High Performance System on a Panel or Foil

Possible ONLY with Polysilicon TFT Technology
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Display Research Lab

Processing Facilities
Poly-Si TFTs Backplanes
PECVD:
Gate dielectric and
amorphous silicon
deposition, and
hydrogenation.
Polymeric Top-Emitting Diodes
Furnace:
Post-doping activation,
silicon crystallization,
and annealing.

Perkin-Elmer Aligner: Tegal 920E RIE Dry

Capable of processing 6”
silicon wafers and metal
foils.
Etcher:
Programmable Spinner: Asymtek Automati c Dispenser:
Reactive Ion Etcher is
Polymers spinning can be Dispensing various sealants with
under installation.
programmed. high accuracy.

Technics Plasma Dry LPCVD:

Etcher: Thermal oxidation.
Oxygen and CF 4 are
available in this system.
1 um gate is achievable.

RF Magnetron Sputter E-beam Evaporator: Evaporator: MBraun Glove Box:

with Thermal Evaporator:
Three different targets can
be placed in the system, and
a thermal evaporator is also
included.
A series o f materials can be
evaporated in this system,
for instance, gold, titanium,
platinum, aluminum, nickel,
and silver.
(Dept. of ECE at Lehigh U.,
Microelectronics Research
Lab, Prof. Marvin White.)
For calcium deposition. For polymers processing and
encapsulation.
In the near future, another set of therm al evaporator/sputter will
be connected to the glove box. Then, the entire PLED process can
be done without exposing the polymers (PEDOT and PPV) to the
air.
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Metal Foils vs. Plastics

Outstanding Advantages of Metal Foils Demerits of Metal Foils
Readily compatible with poly-silicon TFT technology Tend to be rough and thus require polishing or
planarization.
due to superior thermal properties.

Enable thermal oxidation to be used for gate dielectric Need to be coated with an insulating coating.
for high performance & high reliability TFT circuits.

Lower thermal expansion enables small design rules Coating layer should withstand high temperature if
for high performance TFT circuits. thermal oxidation is used for gate dielectric growth.

Higher thermal conductivity enables dissipation of Microstructure of metal foils changes upon annealing
thermal loads. due to grain growth.

High conductivity of metal foils renders them useful as Stresses need to be balanced to avoid warping.
global power or ground terminal.

Compatible with most wet chemical processes.

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Metal Foils Preparation – Display Research Lab

Surface polishing
As-received SS-304 Mechanical polishing Electro-polishing &
Chemical/Mechanical Polishing

Surface finishing with Ra less than 10 nm can be achieved.

CAUTION: Isolated defects may exist depending upon substrate.

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Metal Foils Preparation – Display Research Lab

Insulating layers deposition and testing

Deposit/coat insulating layers on metal foils and then anneal at 900 oC. Evaporate
aluminum through shadow mask that defines test pads of 1 cm2. Identify shorts
between the 1 cm2 aluminum pads and metal foil substrate. 56 total sites were
tested for each substrate (5 inch).
Insulating coatings of metal foils that can withstand high temperature processing
is possible

Initial Result (many shorts) Optimized Result (no shorts)

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Poly-Silicon TFTs Backplanes – Display Research Lab

Effect of inter-metal dielectric layers

Initial Inter-metal Dielectric Process Optimized Dielectric Process
(many shorts) (few shorts)

Each red lines indicates a group of 20 gate lines and each blue line indicates a
group of 20 data lines that are shorted to power lines.
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Polymeric Top-Emitting Diodes – Display Research Lab

Architecture and Fabrication

Each pixel is driven by two PMOS thin-
film transistor. One transistor works as a
switch, and the other one control the
current passing through the light-emitting
diode.
Top-gate poly-silicon transistors are
adopted, as well as the top-emitting
polymeric light-emitting diodes.
Prior to the fabrication of transistors, the
substrate was well-polished and coated by
an insulating layer.
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Polymeric Top-Emitting Diodes – Display Research Lab

Characterizations
Calcium PLEDs have much higher luminescence and can be driven at lower voltage.
A “red-shifted” spectrum was observed on calcium PLED.
Pt/Ca PLED has a current turn-on voltage of 5.0V, which is 3.03V less than Ni/Ca PLED.
Pt/Ca PLED has higher current density than the other PLEDs. Thus, the higher brightness is
expected.

Light Turn-on:
VT,Ca = 6.5 V
VT,A l = 10.8 V

Current Turn-on:
VT,Ca = 8.0 V
VT,A l = 10.5 V

Aluminum Calcium
Light turn-on 10.8V 6.5V
Current turn-on 10.5V 8.0V
8.0
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Polymeric Top-Emitting Diodes – Display Research Lab

Optimization of ITO Sputtering

The optimized ITO has much less sheet resistance below
100ohm/ all over the wafer, as well as better uniformity.
The transmission of a blank glass is around 92%, mostly
due to the refraction rather than the absorption. The
optimized ITO (green curve) has a great transmission,
around 85%, at 550nm wavelength, which is the same
wavelength as our PLEDs emitting.
According to the previous statement, one can obtain a
transmission higher than 92% by means of optimizing the
film thickness.

353 38

RF Power: 100 W 984 334 46 38

RF Power: 50 W
Thickness: 1783 Å Thickness: 1556 Å
Argon Flow: 10 sccm 482 1440 171 42 65 36 Argon Flow: 5 sccm
D.R.: 1.98 Å/s D.R.: 0.86 Å/s
625 410 46 38

418 39

U%=68% U%=20%
(Initial Rs Distribution) (Current Rs Distribution)

Flexible Encapsulation and Testing/Analysis
Encapsulation
100 micron thick foils, 4” in diameter
Radius of curvature during testing <5cm
The steel substrate was insulated by SOG only.
A hermetic and flexible encapsulation is under developing.
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Display Research Lab
Testing and Analysis
EL and PL Measurements:
Extract I-V-B curves and spectra.
IPP (Integrated Inpuled Photoconductivity):
Determine and characterize traps and the
degradation analysis.
AFM-Surface Roughness Analysis:
The anode surface roughness plays a significant
role during the devices aging.
XPS/UPS-Work Function Measurements:
Work functions will be measured on new cathode
materials.
(D. Cahen and A. Kahn, "Electron Energetics at Surfaces and
Interfaces: Concepts and
Experiments", Advanced Mat erials vol. 15 (2003) p. 271.)
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Display Research Lab

Conclusions
A novel approach has been developed for producing high quality metal foil
substrates.
A multilayer coating process has been developed for insulating the metal
foils, as well as inter-metal isolation.
Top-emitting PLEDs with Pt anode and Ca cathode show promising
characteristics and will be capable of being integrated onto poly-silicon
TFTs backplanes.
TFTs backplanes are ready for being integrated with PLEDs.
Sputtering conditions of transparent/conductive ITO have been optimized
and show excellent characteristics.
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Poly-Silicon TFTs Backplanes– Display Research Lab

Progress on metal foils

• Fabricated on 4 inch Steel Wafers

• General Purpose Electronics
• 4 Arrays (60x80 pixels – 250um Pitch)
• Diagonal size: ~1 in
• Test Display driver circuits

• Fabricated on 5 inch Steel Wafers

• General Purpose Electronics
• 1 Array (640x480 pixels – 110um Pitch)
• Diagonal size: ~ 3 1/4 in
• Display row driver circuits integrated
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Poly-Silicon TFTs Backplanes– Display Research Lab

VGA active-matrix array on metal foil

• 1 Array (640x480 pixels – 105x110um), 3.3” diagonal size

• Polysilicon TFT Circuits for integrated drivers & Test Structures
• Array contains 614,400 polysilicon TFTs over an area of 35 cm2
• Integrated polysilicon TFT display scan driver circuits
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Display Research Lab

6 Inch Laser Crystallize Steel Wafers

6 inch Laser Annealed Steel Wafers

• Will include:
• 1 Array (640x480 pixels – 110um Pitch)
• Diagonal size: ~ 3 1/4 in
• Display row driver circuits integrated
• General Purpose Electronics
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Display Research Lab

OLED Displays: 2-TFT Pixel

-Advantages:
PMOS Architecture
-Simple proven benchmark design (minimal development time)
-Low transistor count (increases reliability and yield)
-High aperture ratio (possible high resolution implementations)
-Easy to control (LCD driving IC’s with minimal modifications can be used)
-Disadvantages :
-Displa y brightness non-uniformity due to device parameter variations
-PMOS architecture required for better performance

CMOS Architecture
Design Criteria:

⋅ µ ⋅ C*OX ⋅ ⋅ (Vgs − Vth )

1 W
Dimensions of M1: Id =
2 L

Fram eTim e
Capacitor value: C = I off ⋅
GreyLevel
∂I Vt ⋅ ξVt
First level non-uniformity: = 2⋅ + ξµ
I Vgs − V t
* ξVt, ξ µ threshold voltage and mobility variations

Standard timing diagram for a voltage addressed display

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Physical Layout: 2-TFT Pixels, Small Pitch

- 2 TFT PMOS Active Pixel

- 110um x 105um Pitch
- Storage capacitance between
Poly-silicon and Active layers
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Functionality of AM-OLED pixels

2 TFT 250 um Pitch - PMOS Architecture 2 TFT 110 um Pitch – PMOS Architecture
120.0
3.E-05
100.0
80.0 2.E-05
Iout (uA)

Io ut (A)
60.0

40.0 1.E-05
20.0
0.0 0.E+00
0 2 4 6 8 10 -8 -6 -4 -2 0 2 4 6 8

Vdata (V) V data (V )

2 TFT 125 um Pitch – CMOS Architecture

6.E-06 • Measurement Cond itio ns:

5.E-06 Vdd =10V
4.E-06 Vadd= -5V (2-TFT)
Iout (A)

3.E-06 held constant for 20µs

+10V (4-TFT)
2.E-06
Vdata applied for 20µsec
1.E-06
Measurement conditio ns simulate operatio n of a full-VGA disp lay (50-60Hz refresh rate)
0.E+00
-5 -3 -1 1 3 5
V data (V )
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Display Research Lab

Poly-Silicon TFT Performance

Low Temperature (300-600 o C) process (ELA + PECVD SiO2 gate dielectric)
High Temperature (800-1000 o C) process (SPC + the rmal SiO2 gate dielectric)

1.E-04 1.E-04

1.E-06 1.E-06

Ids( A)
1.E-08
Ids (A)

1.E-08

1.E-10 1.E-10

1.E-12 1.E-12

1.E-14 1.E-14
-20 -10 0 10 20 -30 -20 -10 0 10
Vgs(V) Vgs(V) Poly-Silicon TFT
NMOS and PMOS TFT at Vd = 0.1 V and 1.1 V

Gate Ox ide Device (W/L=20/4) Mobility (cm^2/Vs) Vt (V) SS (V/dec) Ioff (A)
PECVD NMOS 267 +1.4 1.4 1 pA
ELA
PMOS 87 -9.8 2.4 0.1 pA
Thermal NMOS 210 +2.3 2.6 1 pA
SPC
PMOS 130 -3 3.4 1 pA
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Display Research Lab

Electronics: Ring Oscillators

Ring Oscillator: 19 CMOS inverter stages, buffered output, 15V supply operation.
Free-running over frequency: 50MHz; translate into 0.8ns prop. delay time / inverter.
V OU T (2V/div)

0.E+00 5.E-08 1.E-07 2.E-07 2.E-07

Time (s)

Fabricated Ring Oscillator

Lots of other analog and digital circuits has been fabricated on

stainless steel foils to For display or sensory applications like
A/D,D/A, Sample & Hold, Op Amps.
Ring Oscillator Architectures
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Display Research Lab

Electronics: Shift Registers

In order to have lower number of transistors and higher yield, half bit shift registers has been used.
Dynamic Half bit Shift Registers. (Fast, Lower Complexity, higher yield)
18 or 22 TFTs / stage.
Fmin = 50kHz, Fmax = 1.45MHz @ 14V
16/4
16/4
CLKB
CLKA
V OUT (2V/div)

8/4
8/4
16/4 80/4 16/4 80/4

Vin Vout
8/4 8/4 40/4
40/4

CLKB CLKA

0.E+00 5.E-06 1.E-05 2.E-05 2.E-05

Output Buffers
Time (s)

10 Stage of Dynamic Shift Register fabricated on metal foil

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Display Research Lab

Electronics: Shift Registers

Static Half bit Shift Register (runs at low frequencies, no pre-charging)
Fmin = 100Hz, Fmax = 1.25MHz @ 14V.
Both architectures suitable for row display driver role.

16/4
CLKA 16/4
CLKB

8/4
8/4
VOUT (2V/div)

Vin 16/4 80/4 16/4 80/4

Vout

8/4 40/4 8/4 40/4

CLKB CLKA
8/4 8/4

4/4 Output Buffers 4/4

0.E+00 1.E-05 2.E-05 3.E-05 4.E-05 5.E-05

Time (s)

10 Stage of Static Shift Register fabricated on metal foil

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Display Research Lab

Sample and Hold Circuit

Typical Sample and Hold operation diagram 3
S ample Clock
2.5
A nalog Input
S ampled Output
2

Voltage ( V)
1.5

Sampling Clock 1
Load
0.5
Unity gain buffer
(high current capabilities) 0
0.E+00 2.E-03 4.E-03 6.E-03 8.E- 03 1.E- 02 1.E-02 1.E- 02 2.E- 02 2.E- 02 2.E- 02
Storage Capacitor
(sav es data as a voltage v alue) Tim e ( s)

Circuit Characteristics:
- CMOS Pass gate
- Integrated clock inverter for pass gate
- Analog buffer with long double gate
differential pair for lower Kink Effects
and higher linearity
- Large capacitor for retention of data for
high resolution displays
- Just 125 um pitch
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Display Research Lab

Display Testing Approach

A portable Lab-view based
testing platform has been
developed that enables
AMOLED to be tested as a
24 (scan) x 32 (data) blocks
with each block containing
20x20 pixels.
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Driving Approaches (Microcontroller Based)

Microcontroller based Custom Driver Board for full PC Interface.
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Display Research Lab

Conclusions
High Performance Shift Registers were demonstrated on flexible stainless steel foils with
ELA PolySi TFTs.
Designs suitable as integrated display drivers, and for a wide variety of general purpose
digital circuitry of flexible foils.
2 TFT pixel arrays for AMOLED Displays where developed on stainless steel foils and
operational characteristics were demonstrated
Pixels varying in pitch were demonstrated, targeting application specific resolution
requirements.
Display testing approach has been clarified and different driving techniques has been
introduced.
Continuing Activities:
Advancing the yield of polysilicon TFT active matrix arrays on flexible metal foils.
Improving the efficiency of the top-emitting PLEDs.
Integration of OLED & PLED diodes onto the polysilicon TFT active matrix arrays.
Development of a “Hermetic” flexible encapsulation process of AMOLED.
Versatile approaches are developing for diagnostics of PLEDs, for instance, Integrated
Pulsed Photoconductivity (IPP).
The full PC display driving interface board is in progress.