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0-In CDC is the industry’s most comprehensive and easy-to-use clock-domain • Detects and reports combination-
crossing verification solution, integrating advanced verification engines with ally and sequentially reconvergent
engineered methodologies. Using 0-In CDC, customers can efficiently and CDC signals
effectively eliminate all clock-domain crossing problems from their designs. • Highlights CDC reconvergence
that matches known bug signa-
tures
The CDC Verification Challenge designed to ensure proper transmission
and reception of data. The third problem • Automatically generates CDC
Modern system-on-chip (SoC) designs
protocol monitors with built-in
typically contain many separate clock is incorrect logic function where CDC
coverage support
domains. In hardware, clock-domain signals reconverge (i.e., CDC combina-
crossing (CDC) signals are often subject tional and sequential reconvergence). To • Verifies CDC protocols in
to the effects of metastability. However, avoid this, designers must perform exten- simulation using 0-In Assertion
the effects of metastability cannot be sive manual analysis wherever CDC Synthesis system
analyzed using conventional RTL simu- signals reconverge. Using 0-In® CDC, • Exhaustively verifies CDC
lation. As a result, many CDC-related designers can verify that their designs are functionality using formal
functional bugs go undetected until free of all three types of CDC problems. verification technology
post-silicon verification. • Fully IEEE 1364 Verilog
Designs with CDC signals encounter Ease of Use
language compliant, including
three fundamental types of problems — 0-In CDC accepts a wide variety of non-synthesizable code
all are caused by metastability. The first Verilog coding styles, including non-
problem is propagation of metastability. synthesizable constructs common in early
To avoid this, designers use synchro- stages of designs. In addition, 0-In CDC
nizers to reduce the probability that can be run early in the design process, in
metastability leaks into general logic a fully static mode, with no testbench.
throughout the design. The second 0-In CDC supports Verilog simulator
problem is corruption of data transferred command line arguments, so integration
across clock domains. To avoid this, into existing design environments is
designers implement CDC protocols simple. 0-In CDC is fast and has large
w w w. m e n t o r. c o m
capacity, so it can be used after every the 0-In Assertion Synthesis system. Formal Verification
design change, before code check-in. 0-In In simulation, these monitors detect all Using the formal verification capa-
CDC makes an ideal regression tool. violations that might lead to corruption bility included in 0-In CDC, designers
of transferred data. Additionally, these can exhaustively verify that the function
CDC Static Analysis monitors gather coverage information of the design is tolerant of metastability
0-In CDC uses fast static RTL that helps assess how thoroughly the effects in CDC signals.
analysis to automatically identify and design has been tested for correct CDC First, assertions are placed in the
report all clocks (including gated and functionality. design to check for the failures that could
derived clocks), all clock domains, all
be caused by metastability (for example,
signals crossing clock domains, and all CDC Reconvergence
violations of mutual exclusivity, viola-
synchronizers (including user-defined Metastability causes variable and
tions of Gray coding, and data integrity
synchronizers). 0-In CDC also reports unpredictable delays in the transitions
problems). Then, 0-In CDC exhaustively
all missing (i.e., ad-hoc) synchronizers. of received CDC signals. These variable
analyzes all possible metastability
delays might cause the logic that
CDC Protocols scenarios on all CDC signals, including
recombines the CDC signals — either
CDC signals without explicit synchro-
While proper synchronization ensures combinationally or after sequential
nizers. Any metastability scenario that
that metastability does not leak into delays — to fail. As a result, when the
could cause the design to violate an asser-
general logic, it does not by itself ensure design is implemented in silicon it
tion is reported as a simulation trace.
correct CDC functionality. Every signal might experience functional problems.
that crosses clock domains must adhere 0-In CDC embodies the industry’s Advanced Debugging Options
to an appropriate CDC protocol. most advanced technology for analysis 0-In CDC provides several debugging
Otherwise, transferred data will be of CDC reconvergence. It reports all options, including concise textual reports
corrupted in the presence of metasta- CDC reconvergence up to a user-speci- and color-coded graphical debug using the
bility in the hardware. For example: A fied sequential depth and filters out false unified 0-In View reporting environment,
single-bit control signal transmitted out reconvergence. Information in the recon- with links to popular debugging tools.
of a fast clock domain must stay stable vergence report is grouped and organ-
long enough to be sampled by a slower ized to help the user easily check suspect
receiving clock domain (i.e., the control reconvergence logic. 0-In CDC also
signal must be stable longer than one highlights CDC reconvergence that
receiving clock period). matches known bug signatures.
0-In CDC automatically generates
protocol monitors for popular CDC design
styles, including: single-bit control signals
crossing domains via 2DFF synchronizers,
multi-bit data signals crossing domains
using 2DFF synchronizers, mux-synchro-
nized data/control signals, handshake
synchronizers, and FIFO synchronizers. 0-In CDC provides the industry’s most
The automatically generated CDC comprehensive clock- domain crossing
verification environment.
protocol monitors run in simulation using