Title: Fet Ampilfier

Objective :
To determine the polarity of a JFET, its performance as an ampifier and to study the
circuit component and power supply polarity necessary to permit a JFET to
function as an amplifier.

Theory:
A junction field-effect transistor (JFET) is a semiconductor device that is controlled
like a vacuum tube. In its simplest form, the JFET is a layer or channel of N-type
material that acts like a resistor between its two end drain. On the both sides of the
channel, P-type material form a gate through which electrons flow(drain current)
from source to drain. However, when a control voltage is applied to the gate which
is a reverse-bias gate-to-source condition, the channel is depleted and the current
through the N-channel decreases. Once the channel has been depleted enough, the
JFET is said to be pinched off that is, no further drain current will flow. It is important
to note, however, that current will flow while the channel is pinched off. The point is
that no further amount of current will flow. It is also important to note that a JFET
amplifier (common source) will have a Q point of operation well into the pinch-off
region, allowing for a symmetrical(positive to negative) output voltage swing.

Equipment: Audio signal generator , Oscilloscope, DC power supply, VTVM,

Test Leads
Diagram:

Components: (1) 2N3823 FET, or equivalent, Resistors (all 0.25W):

(1) 1kΩ , (1)2.2kΩ, (1) 4.7kΩ, (1) 5.6kΩ, (1) 8.2kΩ, (1)470kΩ

(2) 0.0-µF capacitos, (1) 100-µF capacitor

Procedure :
1. An ohmmeter on the R *100 range was used to measure S-G, G-D and
S-D in both direction of lead polarity and was recorded in Table 57-1. A
diode junction was indicated during the measurements. The JFET was
forward bias tindicate the P-channel with a positive ground and a
negative drain potential. The N-channel was then grounded and a
positve drain connected.

2. The circuit was then connected as shown in Fig. 57-3 with the VDD
polarity and the electrolytic capacitor connected as shown in the
circuit. A 1kHz at 100mVp-p and a 2.2kΩ as a load (drain) was then
connected to the circuit. The dc peak-to-peak voltages were then
measured and recorded in table 57-2. The voltage gain (Av) was then
determined.

3. The load resistor was then replcaed with 4.7-kΩ, 5.6kΩ, and 8.2kΩ and
the dc and ac peak-to-peak values around the circuit was then
measured and recorded. The Av was then determined.

4. The 8.2kΩ resistor was used as the drain load. The power supply was
increase to 30V dc and the effect noted upon the amplifier and the
results in Table57-3.

5. The source bypass capcitor was then removed from the circuit and the
effects noted upon the gain and dc parameters. The results was
recorded in Table 57-3. Note that VDD=15V and RL=5.6kΩ.

6. A frequency check was made while the bypass capacitor was removed
of the amplifier. The low frequency cutt off value and the coupling
capacitor was then determined.
Results:

Table 57-1

Procedure Step Measurement R,Ω

1 S to G ∞

G to D 0.968

S to D ∞

S to G 0.984

G to D ∞

S to D ∞

Table 57-2

Proced RD,k I- VG(d VD(dc VS(dc VG(ac VD(ac VS(ac Av

ure Ω T,mA c) ) ) ) ) )
Step

2 2.2 2.13 0 4.68 2.10 98mV 0.210 0 547m

V

3 4.7 2.08 0 9.71 2.02 98mV 0.377 0 927m

V

5.6 2.02 0 11.84 1.86 98mV 0.441 0 527m

V

8.2 1.56 0 13.94 1.54 98mV 0.54 0 39.9

mV

Table 57-3

Procedure VDD Noted Effects

Step
4 30Vdc VSsa me

VD DCvoltage increased
to 20.81V
VD AC0.63 increase
voltage
VG AC Remain the same
both AC and DC

5 15Vdc Capacitor Removed

VD Decreased to
0.17AC/DC decreased
6.12V
VSIncreased 1.07DC/AC
increase 0.021
VGAC remains the
same/DC remains the
same
Questions:
1. What was the polarity of the JFET used in this experiment?

Ans: In this experiment the JFET was N-channel, that is it was negatively
ground and with a positive drain.

2. What is function of the bypass capacitor? What happens when it is removed

from the amplifier circuit?

Ans: The bypass capacitor is AC short, because of this, the signal is coupled
directly into the gate, since the source is bypassed to ground, all of the AC
input voltage appears between the gate and the source, hence producing an
AC drain current. When the bypass capacitor is removed from the circuit the
voltage across the drain decreased both in AC and DC, the voltage across the
source increased both in the AC and DC, while it remained the same across
the gate.

3. What factors influence the input resistance of the amplifier?

 4. What is the overall effect that is created by increasing the value of load
resistance?

Ans: When the value of the load resistance value was increased the voltage
across the drain (DC) decreased while the drfain (AC) increased, the voltage
across the source and gate both AC and DC remainded constant.

5. What effects to the amplifier are created by increasing the value of the power
supply voltage?

Ans: When the power supply voltage was increase the voltage across the
source and gate remained the same while it increased across the drain.

Discussion:
JFET operation is based on varying the channel width to control the drain current.
There are two ways that the channel width can be varied, either that the gate
source junctions are reverse biased causing the depletion layer to form. When the
size of the depletion layer increase which is an insulator, it decreases the current
across the material area of the channel, causing channel conduction to decrease.
The greater the magnitude of VGS, the greater the sizeof the depletion layer, and the
lower the device current or as as V GS becomes more negative, drain current (ID)
decreases. And the second method for increasing the depletion layer is the hold VGS
constant while VDS is increased.

The gate-source junction of JFET is never allowed to become forward bias, because
the gate material is not constructed to handle any significant amount of current. If
the junction is allowed to become forward biased, the gate current may destroy the
component.

From the experiment, the bypass capacitor was a AC shorts, because of this, the
signal was coupled directly into the gate since the source was bypassed to ground,
all of the AC input voltage appeared between the gate and the source, hence
producing an AC drain current.

When this capacitor was removed from the circuit the voltage across the drain
decreased both AC and DC, the voltage across the source increased both AC and
DC, while it remained the constant across the gate. When the value of the load
resistance was increased the voltage VD(DC) decreased from 12.57V to 6.04V while
VD(AC) increased from 0.210V to 0.54V. the voltage errors the source and the gate
remained the same.

Conclusion:
It was concluded that the JFET performs effeciently as an amplifier. It was also found
that the bypass capacitor is the component that cause an AC drain current and the
DC drain voltage decrease while the AC drain voltage increase in the load
resistance value.
UNIVERSITY OF TECHNOLOGY
JAMAICA
Electronics Devices and Circuits Lab
4

Name: Floyd Huggins (ID#:0902033)

Tutor: Mr. Portuondo

GROUP: Tuesday 3-6pm

Date: 11/16/2010