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ECE4680
Computer Organization and Architecture Processor
Memory
Memory
Memory
Datapath
The Big Picture: Where are We Now? Memory Hierarchy: Principles of Operation
°At any given time, data is copied between only 2 adjacent levels:
°The Five Classic Components of a Computer • Upper Level: the one closer to the processor
- Smaller, faster, and uses more expensive technology
Processor • Lower Level: the one further away from the processor
Input
- Bigger, slower, and uses less expensive technology
Control
Memory °Block:
• The minimum unit of information that can either be present or not
Datapath Output present in the two level hierarchy
Lower Level
To Processor Upper Level Memory
°Today’s Topic: Memory System Memory
Blk X
From Processor Blk Y
Processor-DRAM Memory Gap (latency) °Hit: data appears in some block in the upper level (example: Block X)
• Hit Rate: the fraction of memory access found in the upper level
µProc • Hit Time: Time to access the upper level which consists of
1000 60%/yr.
CPU RAM access time + Time to determine hit/miss
(2X/1.5yr)
“Moore’s Law” °Miss: data needs to be retrieve from a block in the lower level (Block Y)
Performance
1988
1998
1981
1982
1983
1984
1986
1987
1989
1990
1991
1992
1993
1994
1995
1996
1997
Block X
From Processor Block Y
Time
ECE4680 Memory.3 2002-4-21 ECE4680 Memory.6 2002-4-21
Memory Hierarchy: How Does it Work? Technology Trends
°Temporal Locality (Locality in Time): If an item is referenced, it will tend Capacity Speed (latency)
to be referenced again soon.
Logic: 2x in 3 years 2x in 3 years
• Keep more recently accessed data items closer to the processor
DRAM: 4x in 3 years 2x in 10 years
°Spatial Locality (Locality in Space): If an item is referenced, items
whose addresses are close by tend to be referenced soon.
Disk: 4x in 3 years 2x in 10 years
• Move blocks consists of contiguous words to the upper levels
DRAM
Year Size Cycle Time
1980 1000:1! 64 Kb 2:1! 250 ns
Lower Level 1983 256 Kb 220 ns
To Processor Upper Level Memory
Memory 1986 1 Mb 190 ns
Blk X 1989 4 Mb 165 ns
From Processor Blk Y 1992 16 Mb 145 ns
1995 64 Mb 120 ns
Memory Hierarchy of a Modern Computer System SPARCstation 20’s Memory System Overview
Memory Module 7
Memory Module 5
Memory Module 4
Memory Module 3
Memory Module 1
• Provide access at the speed offered by the fastest technology.
Memory Module 2
Memory Module 6
Memory Module 0
Processor Processor Bus (Mbus) 64-bit wide
Control
Secondary
Storage Processor Module (Mbus Module)
Second Main
(Disk) SuperSPARC Processor
On-Chip
Registers
Level Memory
Cache
°The next two lectures will concentrate on random access technology 512 × 8 SRAM
• The Main Memory: DRAMs bits<7:0> Memory Bus<127:0>
• Caches: SRAMs