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DR(n) LP(n)
VO(n)
NS(n)
CO(n) CP(n)
Np
DR1 LP1
VO1 (B+)
AC NS1
IN CO1 CP1
FSCQ-series
Drain
RSY1
Rstr H11A817A R1
Dz
CSY RSY2
RF CF R1
KA431
R2 Q Picture ON
2. Step-by-step Design Procedure In this section, a design procedure is presented using the
schematic of Figure 1 as a reference. Figure 2 illustrates the
1. Define the system specifications design flow chart. The detailed design procedures are as
(Vlinemin, Vlinemax, fL , Po , Eff ) follows:
[STEP-1] Define the system specifications
2. Determine DC link capacitor (CDC)
and DC link voltage range - Line voltage range (Vlinemin and Vlinemax).
- Line frequency (fL).
3. Determine the reflected output voltage
(VRO) - Maximum output power (Po).
- Estimated efficiency (Eff) : The power conversion
4. Determine the transformer primary side efficiency must be estimated to calculate the maximum input
inductance (Lm)
power. If no reference data is available, set Eff = 0.7~0.75 for
low voltage output applications and Eff = 0.8~0.85 for high
5. Choose proper FPS considering input
power and Idspeak voltage output applications. In the case of Color TV
applications, the typical efficiency is 80~83%.
6. Determine the proper core and the With the estimated efficiency, the maximum input power is
minimum primary turns (Npmin)
given by
P
7. Determine the number of turns for each P in = ------o- (1)
output and Vcc auxiliary circuit E ff
For multiple output SMPS, the load occupying factor for
8. Determine the startup resistor each output is defined as
Po ( n )
K L ( n ) = ------------
- (2)
9. Determine the wire diameter for each
Po
winding
where Po(n) is the maximum output power for the n-th
output. For single output SMPS, KL(1)=1. It is assumed that
Is the winding window Y
area (Aw) enough ? Vo1 is the reference output that is regulated by the feedback
control in normal operation.
N
Y
Is it possible to change the core ? [STEP-2] Determine DC link capacitor (CDC) and the
DC link voltage range.
N
Typically, the DC link capacitor is selected as 2-3uF per watt
of input power for universal input range (85-265Vrms) and
1uF per watt of input power for European input range (195V-
10. Choose the secondary side rectifier diodes 265Vrms). With the DC link capacitor selected, the
minimum DC link voltage is obtained as
min min 2 P in ⋅ ( 1 – D ch )
V DC = 2 ⋅ ( V line ) – ------------------------------------ (3)
C DC ⋅ f L
12. Design the synchronization network
where CDC is the DC link capacitor and Dch is the duty cycle
13. Design the voltage drop circuit for burst ratio for CDC to be charged as defined in Figure 3, which is
operation
typically about 0.2. Pin, Vlinemin and fL are specified in
STEP-1.
14. Design the feedback control circuit
The maximum DC link voltage is given as
T ON T OFF TF
TS
- +
+ Figure 5. Typical Waveforms of Quasi-Resonant
Lm
VDC VO Converter
VRO
- FPS -
After determining fsmin and TF, the maximum duty cycle is [STEP-6] Determine the proper core and the minimum
calculated as primary turns.
V RO min
D max = ------------------------------------- ⋅ ( 1 – fs × TF ) (6) Table 2 shows the commonly used cores for C-TV
min
V RO + V DC application for different output powers. When designing the
transformer, consider the maximum flux density swing in
where VDCmin is specified in equation (3) and VRO is normal operation (∆B) as well as the maximum flux density
determined in STEP-3. in transient (Bmax). The the maximum flux density swing in
Then, the primary side inductance is obtained as normal operation is related to the hysteresis loss in the core
min 2 while the maximum flux density in transient is related to the
( V DC ⋅ D max ) core saturation.
Lm = ---------------------------------------------
- (7)
min
2 ⋅ fs ⋅ P in
With the chosen core, the minimum number of turns for the
where Pin, VDCmin and Dmax are specified in equations (1), transformer primary side to avoid the over temperature in the
(3), and (6), respectively and fsmin is the minimum switching core is given by
frequency.
peak
Once Lm is determined, the maximum peak current and RMS min L m I ds 6
NP = -------------------------- × 10 (10)
current of the MOSFET in normal operation are obtained as ∆ BA e
min
peak V DC D max where Lm is specified in equation (7), Idspeak is the peak
I ds = ----------------------------------- (8)
min drain current specified in equation (8), Ae is the cross-
Lm fs
sectional area of the transformer core in mm2 as shown in
rms D max peak Figure 6 and ∆B is the maximum flux density swing in tesla.
I ds = -------------- ⋅ I ds (9)
3 If there is no reference data, use ∆B =0.25~0.30 T.
where VDCmin, Dmax and Lm are specified in equations (3), Since the MOSFET drain current exceeds Idspeak and reaches
(6) and (7), respectively and fsmin is the minimum switching ILIM in a transient or fault condition, the transformer should
frequency. be designed not to be saturated when the MOSFET drain
current reaches ILIM . Therefore, the maximum flux density
(Bmax) when drain current reaches ILIM should be also
considered as
[STEP-5] Choose the proper FPS considering input
power and peak drain current. min L m I LIM 6
NP = -------------------- × 10 (11)
B max A e
With the resulting maximum peak drain current of the
MOSFET (Idspeak) from equation (8), choose the proper FPS where Lm is specified in equation (7), ILM is the pulse-by-
whose the pulse-by-pulse current limit level (ILIM) is higher pulse current limit, Ae is the cross-sectional area of the core
than Idspeak. Since FPS has ± 12% tolerance of ILIM, there in mm2 as shown in Figure 6 and Bmax is the maximum flux
should be some margin for ILIM when choosing the proper density in tesla. Figure 7 shows the typical characteristics of
FPS device. Table 1 shows the lineups of FSCQ-series with ferrite core from TDK (PC40). Since the core is saturated at
rated output power and pulse-by-pulse current limit. low flux density as the temperature goes high, consider the
high temperature characteristics. If there is no reference data,
use Bmax =0.35~0.4 T.
Maximum Output Power
The primary turns should be determined as less than Npmin
230VAC ILIM (A) values obtained from equation (10) and (11).
PRODUCT 85-265Vac
±15% Min Typ Max
FSCQ0565RT 70 W 60 W 3.08 3.5 3.92
FSCQ0765RT 100 W 85 W 4.4 5 5.6 Aw
FSCQ0965RT 130 W 110 W 5.28 6 7.84 (mm2)
FSCQ1265RT 170 W 140 W 6.16 7 7.84
FSCQ1465RT 190 W 160 W 7.04 8 8.96
FSCQ1565RT 210 W 170 W 7.04 8 8.96
FSCQ1565RP 250 W 210 W 10.12 11.5 12.88
min
N p = n ⋅ N s1 > N p (13)
M agnetization Curves (typical)
M aterial :PC40
25 ℃
where n is obtained in equation (12) and Np and Ns1 are the
500 number of turns for the primary side and the reference
60 ℃ output, respectively.
100 ℃
400
The number of turns for the other output (n-th output) is
determined as
Flux density B (mT)
300 Vo ( n ) + VF ( n )
N s ( n ) = --------------------------------- ⋅ N s1 ( 14 )
V o1 + V F1
200 where Vo(n) is the output voltage and VF(n) is the diode
(DR(n)) forward voltage drop of the n-th output, respectively.
100
NS(n) + VF(n) -
0
0 800 1600 DR(n) +
M agnetic field H (A/m) VO(n)
Figure 7. Typical B-H Characteristics of Ferrite Core -
(TDK/PC40)
+ VF2 -
Np NS2 Linear
Regulator
- DR2 VO2
Output Power Core +
VRO
70-100W EER35 -
+
100-150W EER40
EER42
- VFa + N + VF1 -
Rcc NS1
150-200W EER49 a
Vcc Va D DR1 +
a
Table 2. Commonly Used Cores for C-TV Applications + +
VO1
- 18V -
-
where Iop and Idrv are the currents required for IC operation
and MOSFET gate drive, respectively. Iop is given in the
Vo2stby data sheet and Idrv is obtained as
I drv = V cc ⋅ C iss ⋅ f s ( 19 )
Rstr where Dmax and Idsrms are specified in equations (6) and (9),
Vo(n) is the output voltage of the n-th output, VF(n) is the
R CC
Vcc Vco Da diode (DR(n)) forward voltage drop, VRO is specified in
STEP-3 and KL(n) is the load occupying factor for n-th
FSCQ-series
output defined in equation (2).
Vz
(18V)
C a1 C a2
The current density is typically 5A/mm2 when the wire is
long (>1m). When the wire is short with a small number of
turns, a current density of 6-10 A/mm2 is also acceptable.
Avoid using wire with a diameter larger than 1 mm to avoid
Figure. 11 Startup and Vcc Auxiliary Circuit severe eddy current losses as well as to make winding easier.
For high current output, it is recommended using parallel
windings with multiple strands of thinner wire to minimize
- Startup resistor (Rstr) : The average of the minimum skin effect.
current supplied through the startup resistor is given by Check if the winding window area of the core, Aw (refer to
Figure 6) is enough to accommodate the wires. The required
⎛ 2⋅V min ⎞ winding window area (Awr) is given by
V
I sup
avg
= ⎜ line
------------------------------------- – -----------------⎟ ⋅ ------------
start 1 ( 22 )
⎜ π 2 ⎟ R
⎝ ⎠ str
Aw r = Ac ⁄ KF (26)
where Vlinemin is the minimum input voltage, Vstart is the where Ac is the actual conductor area and KF is the fill factor.
start voltage (15V) of FPS and Rstr is the startup resistor. The Typically the fill factor is 0.2~0.25 for single output
startup resistor should be chosen so that Isupavg is larger than applications and 0.15~0.2 for multiple outputs applications.
the maximum startup current (50uA). If not, Vcc can not be If the required window (Awr) is larger than the actual window
charged up to the start voltage and FPS will fail to start up. area (Aw), go back to the STEP-6 and change the core to a
bigger one. Sometimes it is impossible to change the core
The maximum startup time is determined as due to cost or size constraints. In that case, reduce VRO in
V start STEP-3 or increase fsmin, which reduces the primary side
max
T str = C e ⋅ --------------------------------------------------
avg max
- ( 23 ) inductance (Lm) and the minimum number of turns for the
( I sup – I start ) primary (Npmin) shown in equation (7) and (10).
voltage and current margins for the rectifier diode are as [STEP-11] Determine the output capacitors considering
follows the voltage and current ripple.
V RRM > 1.3 ⋅ V D ( n ) (29) The ripple current of the n-th output capacitor (Co(n)) is
obtained as
rms
I F > 1.5 ⋅ I D ( n ) (30)
where VRRM is the maximum reverse voltage and IF is the rms rms 2 2
I cap ( n ) = ( ID ( n ) ) – Io ( n) (31)
average forward current of the diode.
where Io(n) is the load current of the n-th output and ID(n)rms
A quick selection guide for the Fairchild Semiconductor is specified in equation (28). The ripple current should be
rectifier diodes is given in Table 3. In this table, trr is the smaller than the maximum ripple current specification of the
maximum reverse recovery time. capacitor. The voltage ripple on the n-th output is given by
peak
Ultra Fast Recovery Diode I
o ( n ) max D I V R K
RO C ( n ) L ( n )
∆ V o ( n ) = -------------------------- ds
+ ----------------------------------------------------------
- (32)
Co ( n ) fs
min ( Vo ( n ) + VF ( n ) )
Products VRRM IF trr Package
EGP10B 100 V 1A 50 ns DO-41
UF4002 100 V 1A 50 ns DO-41 where Co(n) is the capacitance, Rc(n) is the effective series
resistance (ESR) of the n-th output capacitor, KL(n), Dmax and
EGP20B 100 V 2A 50 ns DO-15
Idspeak are specified in equations (2), (6) and (8) respectively,
EGP30B 100 V 3A 50 ns DO-210AD VRO is specified in STEP-3, Io(n) and Vo(n) are the load
FES16BT 100 V 16 A 35 ns TO-220AC current and output voltage of the n-th output, respectively
EGP10C 150 V 1A 50 ns DO-41 and VF(n) is the diode (DR(n)) forward voltage drop.
EGP20C 150 V 2A 50 ns DO-15 Sometimes it is impossible to meet the ripple specification
EGP30C 150 V 3A 50 ns DO-210AD with a single output capacitor due to the high ESR of the
electrolytic capacitor. In those cases, use additional LC filter
FES16CT 150 V 16 A 35 ns TO-220AC
stages (post filter) to reduce the ripple on the output.
EGP10D 200 V 1A 50 ns DO-41
UF4003 200 V 1A 50 ns DO-41
EGP20D 200 V 2A 50 ns DO-15
EGP30D 200 V 3A 50 ns DO-210AD
[STEP-12] Design the synchronization network.
FES16DT 200 V 16 A 35 ns TO-220AC
The FSCQ-series employs a quasi-resonant switching
EGP10F 300 V 1A 50 ns DO-41
technique to minimize the switching noise and loss. In this
EGP20F 300 V 2A 50 ns DO-15 technique, a capacitor (Cr) is added between the MOSFET
EGP30F 300 V 3A 50 ns DO-210AD drain and source as shown in Figure 12. The basic
EGP10G 400 V 1A 50 ns DO-41 waveforms of a Quasi-Resonant Converter are shown in
Figure 13. The external capacitor lowers the rising slope of
UF4004 400 V 1A 50 ns DO-41
drain voltage, which reduces the EMI caused by the
EGP20G 400 V 2A 50 ns DO-15 MOSFET turn-off. To minimize the MOSFET switching
EGP30G 400 V 3A 50 ns DO-210AD loss, the MOSFET should be turned on when the drain
UF4005 600 V 1A 75 ns DO-41 voltage reaches its minimum value as shown in Figure 13.
EGP10J 600 V 1A 75 ns DO-41 The optimum MOSFET turn-on time is indirectly detected
EGP20J 600 V 2A 75ns DO-15 by monitoring the Vcc winding voltage as shown in Figure
12 and 13. The output of the sync detect comparator (CO)
EGP30J 600 V 3A 75 ns DO-210AD
becomes high when the sync voltage (Vsync) exceeds 4.6V
UF4006 800 V 1A 75 ns TO-41 and low when the Vsync reduces below 2.6V. The MOSFET is
UF4007 1000 V 1A 75 ns TO-41 turned on at the falling edge of the sync detect comparator
output (CO).
Table 3. Fairchild Diode Quick Selection Table
Np N s1 Vds
FSCQ-series
Lm V o1
Sync comparator VRO
+ Drain
CO Cr + VRO
Ids V ds VDC
-
-
4.6/2.6V
GND
Vsync TF
Sync Vcc Vco Na
R cc Da Vovp (12V)
18V Vsyncpk
C a1 C a2 D SY
4.6V
R SY1 2.6V
V sync
CO TQ
C SY R SY2
MOSFET Gate
pk R SY2 normal
V sync = ---------------------------------- ⋅ V a ( 33 )
R SY1 + R SY2
[STEP-13] Design voltage drop circuit for the burst
where Vanormal is the Vcc auxiliary voltage in normal mode.
operation.
Choose the voltage divider RSY1 and RSY2 so that the peak
value of sync voltage (Vsyncpk) is lower than the OVP
threshold voltage (12V) to avoid triggering OVP in normal VO2
operation. It is typical to set Vsyncpk to be 8~10V. M icom
Linear
To synchronize the Vsync with the MOSFET drain voltage, VO1 (B+) Regulator
the sync capacitor (CSY) should be chosen so that TF is same RD
as TQ as shown in Figure 13. TF and TQ are given as Dz (VZB )
Rbias
R3
R1
T F = π ⋅ L m ⋅ C eo (34) CF RF D1
Q1
C Picture ON
normal
⎛ Va ⎞
R
R SY2
= R SY2 ⋅ C SY ⋅ ln ⎜ -------------------- ⋅ ----------------------------------⎟
KA431
TQ (35) A R2
⎝ 2.6 R SY1 + R SY2⎠
operation, the picture on signal is applied and the transistor in Figure 16, the feedback loop can be easily implemented
Q1 is turned on, which de-couples R3, Dz and D1 from the with a one-pole and one-zero compensation circuit. The
feedback network. Thus, only Vo1 is regulated by the current control factor of FPS, K is defined as
feedback circuit in normal operation and is determined as
R1 + R2 I pk I LIM
V o1 = 2.5 ⋅ ⎛ --------------------⎞ (36) K = ---------
- = ----------------- (38)
⎝ R2 ⎠ V FB V FBsat
Figure 15 shows the standby mode operation waveforms. In where Ipk is the peak drain current and VFB is the feedback
standby mode, the picture on signal is disabled and the voltage for a given operating condition, ILIM is the current
transistor Q1 is turned off, which couples R3, Dz and D1 to limit of the FPS and VFBsat is the internal feedback saturation
the reference pin of KA431. If R3 is much smaller than R1, voltage, which is typically 2.5V.
Vo2 is dominant in the feedback loop. Before Vo2 drops to
In order to express the small signal AC transfer functions,
Vo2stby, the voltage on the reference pin of KA431 is higher
the small signal variations of feedback voltage (vFB) and
than 2.5V, which increases the current through the opto LED.
controlled output voltage (vo1) are introduced as vˆFB and vˆo1.
This pulls down the feedback voltage (VFB) of FPS and
forces to stop switching. Once FPS stops switching, Vo2
decrease, and when Vo2 reaches Vo2stby, the current through
vo1
the opto LED decreases allowing the feedback voltage to
rise. When the feedback voltage reaches 0.4V, FPS resumes vbias
switching with a predetermined peak drain current. FPS
Assuming that the forward voltage drop of D1 is 0.5V, the vFB RD
approximate output voltage for Vo2 in standby mode is given ibias
by Rbias
iD
RB CB
stby R1
V 02 = V ZB + 0.5 + 2.5 (37) CTR :1 CF RF
Vo2 Ipk
MOSFET
Vo2stby current
2
1 RL ( 1 – D ) (1 + D)
w z = -------------------- , w rz = ----------------------------------------
- and w p = -------------------
R c1 C o1 2 R L C o1
DL m ( N s1 ⁄ N p )
[STEP-14] Design the feedback control circuit.
Since FSCQ-series employs current mode control as shown where Lm is specified in equation (7), D is the duty cycle of
the FPS, Co1 is the output capacitor of Vo1 and RC1 is the
ESR of Co1.
40 dB
When the converter has more than one output, the low fp Light load
frequency control-to-output transfer function is proportional
to the parallel combination of all load resistance, adjusted by 20 dB
20 dB Loop gain T
40 dB
fp
High input voltage
0dB
20 dB fzc
fz Compensator
Low input voltage fp fpc
-20 dB
frz 0 dB
fc
fz frz Control to output
-40 dB frz
-20 dB
2.5 ⋅ R 1
R 2 = ------------------------ (41)
V o1 – 2.5
(c) The resistors Rbias and RD used together with the opto-
coupler H11A817A and the shunt regulator KA431 should
be designed to provide proper operating current for the
KA431 and to guarantee the full swing of the feedback volt-
age for the FPS device chosen. In general, the minimum
cathode voltage and current for the KA431 are 2.5V and
1mA, respectively. Therefore, Rbias and RD should be
designed to satisfy the following conditions.
V bias – V OP – 2.5
--------------------------------------------- > I FB ( 43 )
RD
V OP
-------------
- > 1mA (44)
R bias
where Vbias is the KA431 bias voltage as shown in Figure 16
and VOP is opto-diode forward voltage drop, which is
typically 1V. IFB is the feedback current of FPS, which is
typically 1mA.
Application Device Input Voltage Output Power Output Voltage Ripple Spec
(Rated Current)
Color TV FSCQ0765RT 85-265Vac 83W 125V (0.4A) ±5%
(60Hz) 24V (0.5A) ±5%
18V (0.5A) ±5%
12V (1.0A) ±5%
- It is assumed that the efficiency is 83% at the minimum input voltage and full load condition.
- Since the maximum input power is 101.2W, the DC link capacitor is set to be 220uF by 2uF/Watt.
5. Choose the proper FPS considering the input power and current limit
Typical current limit of FPS (ILIM) 5.00 A
Minimum ILIM considering tolerance 4.40 A > 4.05 A
->O.K.
- Considering the tolerance of 12%, FSCQ0765RT is chosen, whose pulse-by-pulse current limit is 5A (typical).
7. Determine the number of turns for each output and Vcc drop circuit
Vo2 in standby mode (Vo2stby) 8.0 V Vo2= 24 V in normal mode
Vcc auxiliary voltage drop ratio (Kdrop) = 0.37
stby
Minimum Va in standby mode (Va ) 13.0 V
Va in normal mode (Vanormal) = 37.7 V
VF(n) # of turns
Winding for Va (37.7V) 1.2 V 19.7 => 20 T
Winding for Vo1 (125V) 1.2 V 64 => 64 T
Winding for Vo2 (24V) 1.2 V 12.8 => 13 T
Winding for Vo3 (18V) 1.2 V 9.7 => 10 T
Winding for Vo4 (12V) 1.2 V 6.7 => 7T
Winding for Vo5 (V) V 0.0 => 0T
Number of turns for primary winding (Np)= 64 T > 63.7 T
--->enough turns
Ungapped AL value (AL) 3130 nH/T2
Gap length (G) ; center pole gap = 1.04337 mm
- In standby mode, Vo2 is reduced from 24V to 8V. In order to prevent Vcc under voltage lockout in standby mode, Va in
standby mode is designed as 13V. Then, Va would be 37.7V in normal mode.
-Assuming that the maximum switching frequency is 90kHz, the maximum current consumed by FPS is 9mA. Vcc resistor is
determined as 1.5kΩ.
- For each winding, the diameter of wire is determined so that the current density should be about 5A/mm2
- For EER3540 core, the winding window area is 223mm2. Assuming a fill factor of 0.2, this core is enough to accommodate
the wires.
VD(n) ID(n)rms
Rectifier diode for Vcc 153 V 0.10 A
Rectifier diode for Vo1 (125V / 0.4A) 500 V 0.95 A
Rectifier diode for Vo2 (24V / 0.5A) 99 V 1.14 A
Rectifier diode for Vo3 (18V /0.5A) 75 V 1.12 A
Rectifier diode for Vo1 (12V /1A) 51 V 2.17 A
Rectifier diode for Vo5 (V /A) 0 V ##### A
- Since the output capacitance of MOSFET is 100pF (typical), external capacitor (Cr) of 1nF is used.
100
80
60
40
Gain (dB)
20
0
1 10
control-to-output 100 1000 10000
-20
Compens ator
-60
frequency (Hz)
0
1 10 100 1000 10000
-30
-60
Phase (degree)
-90
-120
Control-to-output
- The control bandwidth (crossover frequency) is about 600Hz with a phase margin of 50 degrees.
Design Summary
• High efficiency (>80% at 85Vac input)
• Wider load range through the extended quasi-resonant operation
• Low standby mode power consumption (<1W)
• Low component count
• Enhanced system reliability through various protection functions
• Internal soft-start (20ms)
1. Schematic
T1 D205
EER3540 EGP20D
18V, 0.5A
RT101 1 10
5D-9 C204
C210 1000uF
470pF 35V
C102 3 11 1kV
220uF D204
400V R102 BEAD101 D105 EGP20D
120kΩ 1N4937 4 12V, 1A
R101 0.25W 13
BD101 120kΩ C107 C205
R106 C106 1nF C209 1000uF
0.25W
1.5kΩ 10uF 1kV 470pF 35V
1 12 1kV
1W 50V
Drain D103
SYNC 1N4937 D202
3 Vcc IC101 5 EGP20J
ZD101 FSCQ0765RT R104 R103 6 125V, 0.4A
D106 14 L202
18V GND FB 1N4148 1.5kΩ 5.1Ω C201 BEAD C202
1W 0.25W 0.25W 15 C207 100uF 47uF
2 4
470pF 160V 160V
16 1kV
C105
C104 C103 R105 3.9nF D203
10uF 47nF 470Ω 50V EGP20D
50V 50V 0.25W 24V, 0.5A
17
7 C203
C208 1000uF
LF101 470pF 35V
18 1kV
VR201
R201 30kΩ
1kΩ
OPT101 0.25W
817A ZD201
R202 R205 5.1V
C101 C206 100kΩ
1kΩ R203 22nF
0.5W
330nF 0.25W 39kΩ 0.25W D201 R208
275VAC 50V 1N4148 SW201
0.25W 1kΩ
ZD102 R207
FUSE 0.25W
12V 5.1kΩ
250V 0.25W
3.0A 1W C301
R204 Q202
2.2nF R206
Q201 KSC945
2.0kΩ 10kΩ
KA431LZ
0.25W 0.25W
2. Transformer Specifications
EER3540
1 18
N p1
N 24 V
2 17 Na
N18V
3 16
N p2
N 125V/2 N125V/2
4 15
Np2
N 125V/2
5 14
N12V
6 13
N24V
N 12V
7 12 N125V/2
Na
8 11 Np1
N 18V
9 10
Winding Specification
Electrical Characteristics
Experimental Verification
To show the validity of the design procedure presented in
this application note, we have built and tested the converter
in the design example. All the circuit components are used as
designed in the design example. The schematic and
transformer specifications are shown in Figure 20 and 21,
respectively.
The Figure 22 shows the FPS drain current and the DC link
voltage waveforms at the minimum input voltage and full
load condition. As shown, the minimum DC link voltage
(VDCmin) is about 90V, which is the same as the designed
value in STEP-2 of page 13.
Figure 23 shows the FPS drain current and voltage
waveforms at the minimum input voltage and full load
condition. As can be seen, the maximum peak drain current
(Idspeak) is about 3.9A and the minimum switching Figure 22. Waveforms of Drain Current and DC Link
Voltage at 85Vac and Full load Condition (Time:2ms/div)
frequency (fsmin) is 26kHz. The values in the design are
4.05A for Idspeak and 24kHz for fsmin as can be seen in
STEP-4 of page 14.
Figure 24 shows the FPS drain current and voltage
waveforms at the maximum input voltage and full load
condition. As calculated in STEP-3 of page 13, the nominal
drain voltage is about 500V.
Figures 25 and 26 show the waveforms of Vsync, drain
voltage and drain current at the maximum input voltage and
full load condition. As designed, the MOSFET drain fall
time is 2.3us and the MOSFET is turned on when the drain
voltage reaches its minimum value.
Figure 27 shows the waveforms of Vcc, drain voltage and
drain current. The measured startup time is 2.45s, which is
smaller than the calculated maximum startup time of 3.83s in
STEP-8 of page 15. When the typical value for the startup
current (25us) is used for the equation (19), the typical Figure 23. Waveforms of Drain Current and Voltage
startup time is calculated as at 85Vac and Full Load Condition (Time : 10us/div)
max V start
T str = C e ⋅ --------------------------------------------------
avg max
- = 2.91s
( I sup – I start )
Efficiency (%)
90
85
80
75
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