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RD2/AD10
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RD3/AD11
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RC0/AD0
• All single cycle instructions (121 ns), except for
RH1
RH0
VDD
RJ7
RJ6
VSS
NC
program branches and table reads/writes which
are two-cycle 1110 9 8 7 6 5 4 3 2 1 84 838281 807978777675
RH2 12 74 RJ5
• Operating speed: RH3 13 73 RJ4
RD1/AD9 14 72 RA0/INT
- DC - 33 MHz clock input RD0/AD8
RE0/ALE
15
16
71
70
RB0/CAP1
RB1/CAP2
RE1/OE 17 69 RB3/PWM2
- DC - 121 ns instruction cycle RE2/WR 18 68 RB4/TCLK12
RE3/CAP4 19 67 RB5/TCLK3
• 8 x 8 Single-Cycle Hardware Multiplier MCLR/VPP 20 66
65
RB2/PWM1
TEST 21 VSS
• Interrupt capability NC
VSS
22
23
PIC17C76X 64
63
NC
OSC2/CLKOUT
VDD 24 62 OSC1/CLKIN
• 16 level deep hardware stack RF7/AN11 25 61 VDD
RF6/AN10 26 60 RB7/SDO
• Direct, indirect, and relative addressing modes RF5/AN9
RF4/AN8
27
28
59
58
RB6/SCK
RA3/SDI/SDA
RF3/AN7 29 57 RA2/SS/SCL
• Internal/external program memory execution, RF2/AN6 30 56 RA1/T0CKI
RH4/AN12 31 55 RJ3
capable of addressing 64 K x 16 program memory RH5/AN13 32 54 RJ2
33343536373839404142434445 464748 49 50 51 52 53
space
RJ1
RH6/AN14
RH7/AN15
RJ0
AVSS
RG3/AN0/VREF+
VSS
RF1/AN5
RF0/AN4
AVDD
RG1/AN2
RG0/AN3
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
RG2/AN1/VREF-
NC
Memory
Device
Program (x16) Data (x8)
PIC17C752 8K 678
PIC17C756A 16 K 902
PIC17C762 8K 678 Special Microcontroller Features:
PIC17C766 16 K 902
• Power-on Reset (POR), Power-up Timer (PWRT)
Peripheral Features: and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
• Up to 66 I/O pins with individual direction control oscillator for reliable operation
• 10-bit, multi-channel Analog-to-Digital converter • Brown-out Reset
• High current sink/source for direct LED drive • Code protection
• Four capture input pins • Power saving SLEEP mode
- Captures are 16-bit, max resolution 121 ns • Selectable oscillator options
• Three PWM outputs (resolution is 1 to 10-bits)
• TMR0: 16-bit timer/counter with CMOS Technology:
8-bit programmable prescaler • Low power, high speed CMOS EPROM
• TMR1: 8-bit timer/counter technology
• TMR2: 8-bit timer/counter • Fully static design
• TMR3: 16-bit timer/counter • Wide operating voltage range (3.0V to 5.5V)
• Two Universal Synchronous Asynchronous • Commercial and Industrial temperature ranges
Receiver Transmitters (USART/SCI) with • Low power consumption
independent baud rate generators
- < 5 mA @ 5V, 4 MHz
• Synchronous Serial Port (SSP) with SPI™ and
- 100 µA typical @ 4.5V, 32 kHz
I2C™ modes (including I2C Master mode)
- < 1 µA typical standby current @ 5V
RD2/AD10
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RD3/AD11
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
68-Pin PLCC
VDD
VSS
NC
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
RD1/AD9 10 60 RA0/INT
RD0/AD8 11 59 RB0/CAP1
RE0/ALE 12 58 RB1/CAP2
RE1/OE 13 57 RB3/PWM2
RE2/WR 14 56 RB4/TCLK12
RE3/CAP4 15 55 RB5/TCLK3
MCLR/VPP 16 54 RB2/PWM1
TEST 17 PIC17C75X 53 VSS
NC 18 52 NC
VSS 19 51 OSC2/CLKOUT
VDD 20 50 OSC1/CLKIN
RF7/AN11 21 49 VDD
RF6/AN10 22 48 RB7/SDO
RF5/AN9 23 47 RB6/SCK
RF4/AN8 24 46 RA3/SDI/SDA
RF3/AN7 25 45 RA2/SS/SCL
RF2/AN6 26 44 RA1/T0CKI
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
RG3/AN0/VREF+
NC
AVSS
VSS
RF1/AN5
RF0/AN4
RG2/AN1/VREF-
AVDD
RG1/AN2
RG0/AN3
VDD
RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
RD2/AD10
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RD3/AD11
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
64-Pin TQFP
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RD1/AD9 1 48 RA0/INT
RD0/AD8 2 47 RB0/CAP1
RE0/ALE 3 46 RB1/CAP2
RE1/OE 4 45 RB3/PWM2
RE2/WR 5 44 RB4/TCLK12
RE3/CAP4 6 43 RB5/TCLK3
MCLR/VPP 7 42 RB2/PWM1
TEST 8
PIC17C75X 41 VSS
VSS 9 40 OSC2/CLKOUT
VDD 10 39 OSC1/CLKIN
RF7/AN11 11 38 VDD
RF6/AN10 12 37 RB7/SDO
RF5/AN9 13 36 RB6/SCK
RF4/AN8 14 35 RA3/SDI/SDA
RF3/AN7 15 34 RA2/SS/SCL
RF2/AN6 16 33 RA1/T0CKI
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RG3/AN0/VREF+
AVSS
VSS
RG2/AN1/VREF-
RG4/CAP3
RF1/AN5
RF0/AN4
AVDD
RG1/AN2
RG0/AN3
VDD
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
84-pin PLCC
RD2/AD10
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RD3/AD11
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RH1
RH0
VDD
VSS
RJ7
RJ6
NC
11 10 9 8 7 6 5 4 3 2 1 84 83828180 79787776 75
RH2 12 74 RJ5
RH3 13 73 RJ4
RD1/AD9 14 72 RA0/INT
RD0/AD8 15 71 RB0/CAP1
RE0/ALE 16 70 RB1/CAP2
RE1/OE 17 69 RB3/PWM2
RE2/WR 18 68 RB4/TCLK12
RE3/CAP4 19 67 RB5/TCLK3
66 RB2/PWM1
MCLR/VPP
TEST
20
21
PIC17C76X 65 VSS
NC 22 64 NC
VSS 23 63 OSC2/CLKOUT
VDD 24 62 OSC1/CLKIN
RF7/AN11 25 61 VDD
RF6/AN10 26 60 RB7/SDO
RF5/AN9 27 59 RB6/SCK
RF4/AN8 28 58 RA3/SDI/SDA
RF3/AN7 29 57 RA2/SS/SCL
RF2/AN6 30 56 RA1/T0CKI
RH4/AN12 31 55 RJ3
RH5/AN13 32 54 RJ2
333435363738394041424344 4546 4748 49 50 51 52 53
RJ1
RH6/AN14
RH7/AN15
RJ0
RF1/AN5
RF0/AN4
AVDD
RG1/AN2
RG0/AN3
VDD
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
AVSS
RG2/AN1/VREF-
VSS
RG7/TX2/CK2
RG3/AN0/VREF+
NC
80-Pin TQFP
RD2/AD10
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RD3/AD11
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RH1
RH0
VDD
VSS
RJ7
RJ6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2 1 60 RJ5
RH3 2 59 RJ4
RD1/AD9 3 58 RA0/INT
RD0/AD8 4 57 RB0/CAP1
RE0/ALE 5 56 RB1/CAP2
RE1/OE 6 55 RB3/PWM2
RE2/WR 7 54 RB4/TCLK12
RE3/CAP4 8 53 RB5/TCLK3
MCLR/VPP 9 52 RB2/PWM1
TEST 10
PIC17C76X 51 VSS
VSS 11 50 OSC2/CLKOUT
VDD 12 49 OSC1/CLKIN
RF7/AN11 13 48 VDD
RF6/AN10 14 47 RB7/SDO
RF5/AN9 15 46 RB6/SCK
RF4/AN8 16 45 RA3/SDI/SDA
RF3/AN7 17 44 RA2/SS/SCL
RF2/AN6 18 43 RA1/T0CKI
RH4/AN12 19 42 RJ3
RH5/AN13 20 41 RJ2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 3637 38 39 40
RJ0
RJ1
RG3/AN0/VREF+
RG7/TX2/CK2
RA5/TX1/CK1
RF1/AN5
RG5/PWM3
RG6/RX2/DT2
RA4/RX1/DT1
RG2/AN1/VREF-
RH6/AN14
RH7/AN15
RF0/AN4
AVDD
RG1/AN2
RG0/AN3
VDD
RG4/CAP3
AVSS
VSS
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
erature number) you are using.
The PIC17CXXX can address up to 64K x 16 of pro- Signed math can have greater than 7-bit values (mag-
gram memory space. nitude), if more than one byte is used. The overflow bit
only operates on bit6 (MSb of magnitude) and bit7 (sign
The PIC17C752 and PIC17C762 integrate 8K x 16 of bit) of each byte value in the ALU. That is, the overflow
EPROM program memory on-chip. bit is not useful if trying to implement signed math
The PIC17C756A and PIC17C766 integrate 16K x 16 where the magnitude, for example, is 11-bits.
EPROM program memory on-chip. If the signed math values are greater than 7-bits (such
A simplified block diagram is shown in Figure 3-1. The as 15-, 24-, or 31-bit), the algorithm must ensure that
descriptions of the device pins are listed in Table 3-1. the low order bytes of the signed value ignore the over-
flow status bit.
Program execution can be internal only (Microcontrol-
ler or Protected Microcontroller mode), external only Example 3-1 shows two cases of doing signed arith-
(Microprocessor mode), or both (Extended Microcon- metic. The Carry (C) bit and the Overflow (OV) bit are the
troller mode). Extended Microcontroller mode does not most important status bits for signed math operations.
allow code protection.
The PIC17CXXX can directly or indirectly address its EXAMPLE 3-1: 8-BIT MATH ADDITION
register files or data memory. All special function regis- Hex Value Signed Values Unsigned Values
ters, including the Program Counter (PC) and Working
FFh -1 255
Register (WREG), are mapped in data memory. The + 01h + 1 + 1
PIC17CXXX has an orthogonal (symmetrical) instruction = 00h = 0 (FEh) = 256 → 00h
set that makes it possible to carry out any operation on
any register using any addressing mode. This symmetri- C bit = 1 C bit = 1 C bit = 1
cal nature and lack of ‘special optimal situations’ make OV bit = 0 OV bit = 0 OV bit = 0
programming with the PIC17CXXX simple, yet efficient.
In addition, the learning curve is reduced significantly. DC bit = 1 DC bit = 1 DC bit = 1
Z bit = 1 Z bit = 1 Z bit = 1
One of the PIC17CXXX family architectural enhance-
ments from the PIC16CXX family, allows two file regis-
ters to be used in some two operand instructions. This
Hex Value Signed Values Unsigned Values
allows data to be moved directly between two registers
without going through the WREG register, thus increas- 7Fh 127 127
ing performance and decreasing program memory + 01h + 1 + 1
= 80h = 128 → 00h = 128
usage.
The PIC17CXXX devices contain an 8-bit ALU and C bit = 0 C bit = 0 C bit = 0
working register. The ALU is a general purpose arith- OV bit = 1 OV bit = 1 OV bit = 1
metic unit. It performs arithmetic and Boolean functions
between data in the working register and any register DC bit = 1 DC bit = 1 DC bit = 1
file. Z bit = 0 Z bit = 0 Z bit = 0
PORTA
Clock
RA0/INT Q1, Q2, Generator OSC1,
IR<16> Q3, Q4 OSC2
RA1/T0CKI WREG<8> BITOP Power-on
RA2/SS/SCL Reset
RA3/SDI/SDA
Brown-out VDD, VSS
RA4/RX1/DT1 Reset
RA5/TX1/CK1
Chip_reset Watchdog
& Other Timer MCLR, VPP
PORTB Control
8 x 8 mult ALU Signals
RB0/CAP1 Test Mode
RB1/CAP2 Select Test
RB2/PWM1
RB3/PWM2 PRODH PRODL Shifter IR Latch <16>
RB4/TCLK12
RB5/TCLK3
RB6/SCK 8 8
RB7/SDO
8
PORTC BSR <7:4> 16 F1
RC0/AD0 IR <7:0> Decode
F9
RC1/AD1 12 Read/Write
RC2/AD2 Instruction Decode
RC3/AD3 Decode for
RAM Registers
RC4/AD4 Address ROM Latch <16>
Mapped 8
RC5/AD5 Buffer in Data
RC6/AD6 Control Outputs Space
Data RAM
RC7/AD7
17C756A
902 x 8
PORTD 17C752
RD0/AD8 678 x 8
AD<15:0>
RD1/AD9 Data Latch PORTC,
RD2/AD10 PORTD
RD3/AD11 BSR Literal Table
RD4/AD12 Data Latch
16
Stack
PORTF PCH PCL
16 16 x 16
RF0/AN4
RF1/AN5
RF2/AN6 16
RF3/AN7 Data Bus<8>
RF4/AN8
RF5/AN9
RF6/AN10 10-bit
RF7/AN11 Timer0 Timer2 USART1 PWM1 PWM3 Capture2 A/D SSP
PORTG
RG0/AN3
RG1/AN2 Interrupt
Timer1 Timer3 USART2 PWM2 Capture1 Capture3 Capture4
RG2/AN1/VREF- Module
RG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
Interrupt 10-bit
SSP A/D Capture2 Capture3 Capture4
Module
The internal oscillator circuit is used to generate the In XT or LF modes, a crystal or ceramic resonator is con-
device clock. Four device clock periods generate an nected to the OSC1/CLKIN and OSC2/CLKOUT pins to
internal instruction clock (TCY). establish oscillation (Figure 4-2). The PIC17CXXX oscil-
lator design requires the use of a parallel cut crystal. Use
There are four modes that the oscillator can operate in. of a series cut crystal may give a frequency out of the
They are selected by the device configuration bits dur- crystal manufacturers specifications.
ing device programming. These modes are:
For frequencies above 24 MHz, it is common for the
• LF Low Frequency (FOSC ≤ 2 MHz) crystal to be an overtone mode crystal. Use of overtone
• XT Standard Crystal/Resonator Frequency mode crystals require a tank circuit to attenuate the
(2 MHz ≤ FOSC ≤ 33 MHz) gain at the fundamental frequency. Figure 4-3 shows
• EC External Clock Input an example circuit.
(Default oscillator configuration)
• RC External Resistor/Capacitor 4.1.3 OSCILLATOR/RESONATOR
(FOSC ≤ 4 MHz) START-UP
There are two timers that offer necessary delays on As the device voltage increases from Vss, the oscillator
power-up. One is the Oscillator Start-up Timer (OST), will start its oscillations. The time required for the oscil-
intended to keep the chip in RESET until the crystal lator to start oscillating depends on many factors.
oscillator is stable. The other is the Power-up Timer These include:
(PWRT), which provides a fixed delay of 96 ms (nomi- • Crystal/resonator frequency
nal) on POR and BOR. The PWRT is designed to keep
• Capacitor values used (C1 and C2)
the part in RESET while the power supply stabilizes.
With these two timers on-chip, most applications need • Device VDD rise time
no external RESET circuitry. • System temperature
SLEEP mode is designed to offer a very low current • Series resistor value (and type) if used
power-down mode. The user can wake from SLEEP • Oscillator mode selection of device (which selects
through external RESET, Watchdog Timer Reset, or the gain of the internal oscillator inverter)
through an interrupt. Figure 4-1 shows an example of a typical oscillator/
Several oscillator options are made available to allow resonator start-up. The peak-to-peak voltage of the
the part to better fit the application. The RC oscillator oscillator waveform can be quite low (less than 50% of
option saves system cost while the LF crystal option device VDD) when the waveform is centered at VDD/2
saves power. Configuration bits are used to select var- (refer to parameter #D033 and parameter #D043 in the
ious options. electrical specification section).
C1
SLEEP
XTAL SLEEP
RF
C2
OSC2 OSC2
(Note 1)
C2 To internal C3
logic L1
PIC17CXXX PIC17CXXX
0.1 µF
See Table 4-1 and Table 4-2 for recommended values of C1 To filter the fundamental frequency:
and C2. 1 = 2
Note 1: A series resistor (Rs) may be required for AT strip L1*C2 (2πf)
cut crystals. Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
C3 blocks DC current to ground.
10 kΩ
Clock from OSC1
XTAL
ext. system
PIC17CXXX
CLKOUT OSC2 10kΩ
(FOSC/4)
20 pF 20 pF
XTAL
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruc-
tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
External
Reset
MCLR
BOR Brown-out
Module Reset
WDT WDT
Module
Time_Out
Reset
VDD Rise
Detect S
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
OST R Q
† This RC oscillator is shared with the WDT when not in a power-up sequence.
VDD
D R
R1
MCLR
MCLR
C PIC17CXXX OSC2
TOSC1
TOST
Note 1: An external Power-on Reset circuit is OST TIME_OUT
required only if VDD power-up time is too
slow. The diode D helps discharge the capac-
PWRT TIME_OUT
itor quickly when VDD powers down.
2: R < 40 kΩ is recommended to ensure that the TPWRT
voltage drop across R does not exceed 0.2V
INTERNAL RESET
(max. leakage current spec. on the MCLR/
VPP pin is 5 µA). A larger voltage drop will This figure shows in greater detail the timings involved
degrade VIH level on the MCLR/VPP pin. with the oscillator start-up timer. In this example, the low
3: R1 = 100Ω to 1 kΩ will limit any current flow- frequency crystal start-up time is larger than power-up
ing into MCLR from external capacitor C in time (TPWRT).
the event of MCLR/VPP pin breakdown due to TOSC1 = time for the crystal oscillator to react to an oscil-
Electrostatic Discharge (ESD) or Electrical lation level detectable by the Oscillator Start-up Timer
Overstress (EOS). (OST).
TOST = 1024TOSC.
0 0 1 1 Power-on Reset
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
1 1 0 1 WDT Reset during normal operation
1 1 0 0 WDT Wake-up during SLEEP
1 1 1 1 MCLR Reset during normal operation
1 0 1 1 Brown-out Reset
0 0 0 x Illegal, TO is set on POR
0 0 x 0 Illegal, PD is set on POR
x x 1 1 CLRWDT instruction executed
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
TABLE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
Unbanked
PRODL 18h xxxx xxxx uuuu uuuu uuuu uuuu
PRODH 19h xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented, read as ’0’, q = value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.
Internal
RESET Greater of 96 ms
and 1024 TOSC
VDD
BVDD Max.
BVDD Min.
Internal < 96 ms
RESET Greater of 96 ms
and 1024 TOSC
VDD
BVDD Max.
BVDD Min.
Internal
RESET Greater of 96 ms
and 1024 TOSC
TMR1IF INTSTA
TMR1IE
Wake-up (If in SLEEP mode)
CA2IF T0IF or terminate long write
CA2IE T0IE
CA1IF INTF
CA1IE INTE
TX1IF Interrupt to CPU
TX1IE T0CKIF
RC1IF T0CKIE
RC1IE PEIF
SSPIF PEIE
SSPIE
BCLIF GLINTD (CPUSTA<4>)
BCLIE
PIR2/PIE2
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30289B-page 40
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PIC17C7XX
OSC1
OSC2
RA0/INT or
RA1/T0CKI
INTF or
T0CKIF
GLINTD
INT PIN/T0CKI PIN INTERRUPT TIMING
PC PC PC + 1 Addr (Vector) YY YY + 1 PC + 1
System Bus
Instruction PC Inst (PC) Addr Inst (PC+1) Addr Inst (PC+1) Addr Inst (Vector) Addr RETFIE Addr Inst (YY + 1)
Fetched
Instruction
Inst (PC) Dummy Dummy RETFIE Dummy
Executed
isters (SFRs). The operation of the SFRs that control Stack Level 16
the “core” are described here. The SFRs used to con-
RESET Vector 0000h
trol the peripheral modules are described in the section
discussing each individual peripheral module. INT Pin Interrupt Vector 0008h
User Memory
7.1.1 PROGRAM MEMORY OPERATION
Space(1)
The PIC17C7XX can operate in one of four possible 1FFFh
program memory configurations. The configuration is (PIC17C752
PIC17C762)
selected by configuration bits. The possible modes are:
• Microprocessor
• Microcontroller
• Extended Microcontroller
3FFFh
• Protected Microcontroller (PIC17C756A
PIC17C766)
The Microcontroller and Protected Microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data. The FDFFh
Protected Microcontroller mode also enables the code FOSC0 FE00h
Configuration Memory
PROGRAM SPACE
External 2000h
Program
Memory
External
Program
PIC17C752/762 Memory
DATA SPACE
120h 120h 120h
4000h
Program
Memory
External
Program
Memory
PIC17C756A/766
FFFFh FE00h Config. Bits
Test Memory
FFFFh
FFFFh Boot ROM
OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP
FFh 1FFh 2FFh 3FFh FFh 1FFh 2FFh 3FFh FFh 1FFh 2FFh 3FFh
Memory(3) Memory(3)
A15-A0 (MSB) (LSB)
AD7-AD0 373(3) Ax-A0 Ax-A0
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
3: 16-bit wide devices are now common and could be used instead of 8-bit wide devices.
Unbanked
18h PRODL
19h PRODH
1Ah General
Purpose
1Fh RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked
SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg-
ister reads ‘0’s.
4: Bank 8 is only implemented on the PIC17C76X devices.
Unbanked
00h INDF0 Uses contents of FSR0 to address Data Memory (not a physical register) ---- ---- ---- ----
01h FSR0 Indirect Data Memory Address Pointer 0 xxxx xxxx uuuu uuuu
02h PCL Low order 8-bits of PC 0000 0000 0000 0000
03h(1) PCLATH Holding Register for upper 8-bits of PC 0000 0000 uuuu uuuu
04h ALUSTA FS3 FS2 FS1 FS0 OV Z DC C 1111 xxxx 1111 uuuu
05h T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 — 0000 000- 0000 000-
06h(2) CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
07h INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
08h INDF1 Uses contents of FSR1 to address Data Memory (not a physical register) ---- ---- ---- ----
09h FSR1 Indirect Data Memory Address Pointer 1 xxxx xxxx uuuu uuuu
0Ah WREG Working Register xxxx xxxx uuuu uuuu
0Bh TMR0L TMR0 Register; Low Byte xxxx xxxx uuuu uuuu
0Ch TMR0H TMR0 Register; High Byte xxxx xxxx uuuu uuuu
0Dh TBLPTRL Low Byte of Program Memory Table Pointer 0000 0000 0000 0000
0Eh TBLPTRH High Byte of Program Memory Table Pointer 0000 0000 0000 0000
0Fh BSR Bank Select Register 0000 0000 0000 0000
Bank 0
RA5/TX1/ RA4/RX1/ RA3/SDI/ RA2/SS/
10h PORTA(4,6) RBPU — RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu
CK1 DT1 SDA SCL
11h DDRB Data Direction Register for PORTB 1111 1111 1111 1111
RB7/ RB6/ RB5/ RB4/ RB3/ RB2/ RB1/ RB0/
12h PORTB(4) xxxx xxxx uuuu uuuu
SDO SCK TCLK3 TCLK12 PWM2 PWM1 CAP2 CAP1
13h RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h RCREG1 Serial Port Receive Register xxxx xxxx uuuu uuuu
15h TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
16h TXREG1 Serial Port Transmit Register (for USART1) xxxx xxxx uuuu uuuu
17h SPBRG1 Baud Rate Generator Register (for USART1) 0000 0000 0000 0000
Bank 1
10h DDRC(5) Data Direction Register for PORTC 1111 1111 1111 1111
11h PORTC(4,5) RC7/AD7 RC6/AD6 RC5/AD5 RC4/AD4 RC3/AD3 RC2/AD2 RC1/AD1 RC0/AD0 xxxx xxxx uuuu uuuu
12h DDRD(5) Data Direction Register for PORTD 1111 1111 1111 1111
RD7/ RD6/ RD5/ RD4/ RD3/ RD2/
13h PORTD(4,5) RD1/AD9 RD0/AD8 xxxx xxxx uuuu uuuu
AD15 AD14 AD13 AD12 AD11 AD10
14h DDRE(5) Data Direction Register for PORTE ---- 1111 ---- 1111
RE3/
15h PORTE(4,5) — — — — RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu
CAP4
16h PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
Bank 2
10h TMR1 Timer1’s Register xxxx xxxx uuuu uuuu
11h TMR2 Timer2’s Register xxxx xxxx uuuu uuuu
12h TMR3L Timer3’s Register; Low Byte xxxx xxxx uuuu uuuu
13h TMR3H Timer3’s Register; High Byte xxxx xxxx uuuu uuuu
14h PR1 Timer1’s Period Register xxxx xxxx uuuu uuuu
15h PR2 Timer2’s Period Register xxxx xxxx uuuu uuuu
16h PR3L/CA1L Timer3’s Period Register - Low Byte/Capture1 Register; Low Byte xxxx xxxx uuuu uuuu
17h PR3H/CA1H Timer3’s Period Register - High Byte/Capture1 Register; High Byte xxxx xxxx uuuu uuuu
Bank 3
10h PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----
11h PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----
12h PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
14h CA2L Capture2 Low Byte xxxx xxxx uuuu uuuu
15h CA2H Capture2 High Byte xxxx xxxx uuuu uuuu
16h TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4
10h PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
12h Unimplemented — — — — — — — — ---- ---- ---- ----
13h RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h RCREG2 Serial Port Receive Register for USART2 xxxx xxxx uuuu uuuu
15h TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
16h TXREG2 Serial Port Transmit Register for USART2 xxxx xxxx uuuu uuuu
17h SPBRG2 Baud Rate Generator for USART2 0000 0000 0000 0000
Bank 5:
10h DDRF Data Direction Register for PORTF 1111 1111 1111 1111
RF7/ RF6/ RF5/ RF4/ RF3/ RF2/ RF1/ RF0/
11h PORTF(4) 0000 0000 0000 0000
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4
12h DDRG Data Direction Register for PORTG 1111 1111 1111 1111
RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/
13h PORTG(4) xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0 AN1 AN2 AN3
14h ADCON0 CHS3 CHS2 CHS1 CHS0 — GO/DONE — ADON 0000 -0-0 0000 -0-0
15h ADCON1 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
17h ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
Bank 6
10h SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode 0000 0000 0000 0000
11h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
12h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
13h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
14h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
15h Unimplemented — — — — — — — — ---- ---- ---- ----
16h Unimplemented — — — — — — — — ---- ---- ---- ----
17h Unimplemented — — — — — — — — ---- ---- ---- ----
Bank 7
10h PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----
11h PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
12h CA3L Capture3 Low Byte xxxx xxxx uuuu uuuu
13h CA3H Capture3 High Byte xxxx xxxx uuuu uuuu
14h CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu
15h CA4H Capture4 High Byte xxxx xxxx uuuu uuuu
16h TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
17h Unimplemented — — — — — — — — ---- ---- ---- ----
Bank 8(3)
10h(3) DDRH Data Direction Register for PORTH 1111 1111 1111 1111
RH7/ RH6/ RH5/ RH4/
11h(3) PORTH(4) RH3 RH2 RH1 RH0 xxxx xxxx uuuu uuuu
AN15 AN14 AN13 AN12
12h(3) DDRJ Data Direction Register for PORTJ 1111 1111 1111 1111
13h(3) PORTJ(4) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx uuuu uuuu
14h(3) Unimplemented — — — — — — — — ---- ---- ---- ----
15h(3) Unimplemented — — — — — — — — ---- ---- ---- ----
16h(3) Unimplemented — — — — — — — — ---- ---- ---- ----
17h(3) Unimplemented — — — — — — — — ---- ---- ---- ----
Unbanked
18h PRODL Low Byte of 16-bit Product (8 x 8 Hardware Multiply) xxxx xxxx uuuu uuuu
19h PRODH High Byte of 16-bit Product (8 x 8 Hardware Multiply) xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
0000 1:1
0001 1:2
0010 1:4
0011 1:8
0100 1:16
0101 1:32
0110 1:64
0111 1:128
1xxx 1:256
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
RAM
Note 1: There is not a status bit for stack under-
flow. The STKAV bit can be used to detect Instruction
the underflow which results in the stack Executed
pointer being at the Top-of-Stack.
Opcode Address
2: There are no instruction mnemonics
called PUSH or POP. These are actions
8
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc- File = INDFx
tions, or the vectoring to an interrupt
vector.
8 8
Instruction
3: After a RESET, if a “POP” operation Fetched
occurs before a “PUSH” operation, the
Opcode File FSR
STKAV bit will be cleared. This will
appear as if the stack is full (underflow
has occurred). If a “PUSH” operation
occurs next (before another “POP”), the 7.4.1 INDIRECT ADDRESSING
STKAV bit will be locked clear. Only a REGISTERS
device RESET will cause this bit to set. The PIC17C7XX has four registers for indirect address-
ing. These registers are:
After the device is “PUSH’d” sixteen times (without a • INDF0 and FSR0
“POP”), the seventeenth push overwrites the value • INDF1 and FSR1
from the first push. The eighteenth push overwrites the
Registers INDF0 and INDF1 are not physically imple-
second push (and so on).
mented. Reading or writing to these registers activates
indirect addressing, with the value in the corresponding
FSR register being the address of the data. The FSR is
an 8-bit register and allows addressing anywhere in the
256-byte data memory address range. For banked
memory, the bank of memory accessed is specified by
the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if INDF0
(or INDF1) is written to indirectly, the operation will be
equivalent to a NOP, and the status bits are not affected.
MOVLW 0x20 ;
MOVWF FSR0 ; FSR0 = 20h
BCF ALUSTA, FS1 ; Increment FSR
BSF ALUSTA, FS0 ; after access
BCF ALUSTA, C ; C = 0
MOVLW END_RAM + 1 ;
LP CLRF INDF0, F ; Addr(FSR) = 0
CPFSEQ FSR0 ; FSR0 = END_RAM+1?
GOTO LP ; NO, clear next
: ; YES, All RAM is
: ; cleared
FIGURE 7-8: PROGRAM COUNTER The read-modify-write only affects the PCL with the
USING THE CALL AND result. PCH is loaded with the value in the PCLATH. For
GOTO INSTRUCTIONS example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
15 13 12 8 7 0 PCLATH = 03h before instruction, PC = 0320h after the
From Instruction instruction. To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
PC<15:13> 5 the low value to PCL.
3 The following PC related operations do not change
54 8 PCLATH:
7 0
PCLATH a) LCALL, RETLW, and RETFIE instructions.
b) Interrupt vector is forced onto the PC.
8
c) Read-modify-write instructions on PCL
15 8 7 0
(e.g. BSF PCL).
PCH PCL
BSR
7 4 3 0
(2) (1)
Address
Range
0 1 2 3 4 5 6 7 8 15
10h SFR (Peripheral)
••• Banks
17h
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 15
0 1 2 3 4 15
20h GPR (RAM)
••• Banks
FFh
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 15
Note 1: For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank
is not recommended.
3: SFR Bank 8 is only implemented on the PIC17C76X.
The PIC17C7XX has four instructions that allow the TABLE POINTER
processor to move data from the data memory space to
TBLPTRH TBLPTRL
the program memory space, and vice versa. Since the
program memory space is 16-bits wide and the data TABLE LATCH (16-bit)
memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data TABLATH TABLATL
memory.
The TLWT t,f and TABLWT t,i,f instructions are
3 3
used to write data from the data memory space to the
TABLWT 1,i,f TABLWT 0,i,f
program memory space. The TLRD t,f and TABLRD
t,i,f instructions are used to write data from the pro-
gram memory space to the data memory space. Data
Memory Program Memory
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in Microprocessor or Extended
Microcontroller mode.
f
Figure 8-1 through Figure 8-4 show the operation of 1
these four instructions. The steps show the sequence
of operation. Prog-Mem
(TBLPTR)
2
FIGURE 8-1: TLWT INSTRUCTION
OPERATION
TABLE POINTER
TBLPTRH TBLPTRL
f
1
Step 1: 8-bit value from register ’f’, loaded into the high or low
byte in TABLAT (16-bit).
3 3
Data TABLRD 1,i,f TABLRD 0,i,f
Memory Program Memory
Data
Memory Program Memory
f
1
f
1
Prog-Mem
(TBLPTR)
2
Note 1: Programming requirements must be If a peripheral interrupt source is used to terminate the
met. See timing specification in electrical long write, the interrupt enable and flag bits must be
specifications for the desired device. set. The interrupt flag will not be automatically cleared
Violating these specifications (including upon the vectoring to the interrupt vector address.
temperature) may result in EPROM The GLINTD bit determines whether the program will
locations that are not fully programmed branch to the interrupt vector when the long write is ter-
and may lose their state over time. minated. If GLINTD is clear, the program will vector, if
2: If the VPP requirement is not met, the GLINTD is set, the program will not vector to the
table write is a 2-cycle write and the pro- interrupt address.
gram memory is unchanged.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
’1’
WR
Note: If external write and GLINTD = ’1’ and Enable bit = ’1’, then when ’1’ → Flag bit, do table write.
The highest pending interrupt is cleared.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0 PC PC+1 TBL1 Data out 1 PC+2 TBL2 Data out 2 PC+3
Instruction
Fetched TABLWT1 TABLWT2 INST (PC+2) INST (PC+3)
Instruction INST (PC-1) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 INST (PC+2)
Executed
Data write cycle Data write cycle
ALE
OE
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
’1’
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
OE
’1’
WR
FIGURE 8-9: ACCESSING EXTERNAL MEMORY WITH TABLRD AND TABLWT INSTRUCTIONS
TABLPTR
Program Memory
(In External Memory Space)
Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 33 MHz @ 16 MHz @ 8 MHz
(Words)
8 x 8 unsigned Without hardware multiply 13 69 8.364 µs 17.25 µs 34.50 µs
Hardware multiply 1 1 0.121 µs 0.25 µs 0.50 µs
8 x 8 signed Without hardware multiply — — — — —
Hardware multiply 6 6 0.727 µs 1.50 µs 3.0 µs
16 x 16 unsigned Without hardware multiply 21 242 29.333 µs 60.50 µs 121.0 µs
Hardware multiply 24 24 2.91 µs 6.0 µs 12.0 µs
16 x 16 signed Without hardware multiply 52 254 30.788 µs 63.50 µs 127.0 µs
Hardware multiply 36 36 4.36 µs 9.0 µs 18.0 µs
RD_PORTA
(Q2)
Q D
1 Q CK WR_PORTA
(Q4)
0 SCL Out
EN Data Bus
RD_PORTA
RD_PORTA
(Q2)
(Q2)
Q D
Serial Port Output Signals
SSP Mode
RBPU (PORTA<7>)
Weak
Pull-up Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Q
Data WR_PORTB (Q4)
CK
Note: I/O pins have protection diodes to VDD and VSS.
RBPU (PORTA<7>)
Weak
Pull-up Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D R
Port
Q
Data WR_PORTB (Q4)
CK
Peripheral_output
Peripheral_enable
RBPU (PORTA<7>)
Weak
Pull-up Match Signal
from other
port pins
RBIF
D Q Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
OE D
Q
WR_DDRB (Q4)
CK
Port
P Data
0
Q D
1
WR_PORTB (Q4)
Q CK
N
SPI Output
SPI Output Enable
RBPU (PORTA<7>)
Weak
Pull-up Match Signal
from other
port pins
RBIF
D Q Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE Q
WR_DDRB (Q4)
CK
P Port
0 Data SS Output Disable
Q D
1
WR_PORTB (Q4)
N Q CK
SPI Output
SPI Output Enable
Note: I/O pin has protection diodes to VDD and VSS.
Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’, q = value depends on condition. Shaded cells are not used by PORTB.
To D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
Port D
0 Q
Data
1 WR_PORTC
CK
RD_DDRC
Q D
WR_DDRC
CK
R S
EX_EN
FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)
To D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
Port D
0 Q
Data
1 WR_PORTD
CK
RD_DDRD
Q D
WR_DDRD
CK
R S
EX_EN
Data Bus
TTL
Input
Buffer
RD_PORTE
Port D
0 Q
Data WR_PORTE
1
CK
RD_DDRE
Q D
WR_DDRE
CK
R S
EX_EN
CNTL System Bus
DRV_SYS Control
Peripheral In
Data Bus
D Q
EN
EN
VDD
RD_PORTE
Q D
Port WR_PORTE
Data CK
Q
N
RD_DDRE
Q D
WR_DDRE
CK
Q S
RE0/ALE bit0 TTL Input/output or system bus Address Latch Enable (ALE) control pin.
RE1/OE bit1 TTL Input/output or system bus Output Enable (OE) control pin.
RE2/WR bit2 TTL Input/output or system bus Write (WR) control pin.
RE3/CAP4 bit3 ST Input/output or Capture4 input pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
15h, Bank 1 PORTE — — — — RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu
14h, Bank 1 DDRE Data Direction Register for PORTE ---- 1111 ---- 1111
14h, Bank 7 CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu
15h, Bank 7 CA4H Capture4 High Byte xxxx xxxx uuuu uuuu
16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
Data Bus
D Q
VDD
WR PORTF
CK Q
P
Data Latch
I/O pin
D Q
N
WR DDRF
CK Q VSS
DDRF Latch
ST
Input
RD DDRF Buffer
Q D
EN
EN
RD PORTF
PCFG3:PCFG0
To other pads
VAIN
CHS3:CHS0
To other pads
Data Bus
D Q
VDD
WR PORTG
CK Q
P
Data Latch
I/O pin
D Q
N
WR DDRG
CK Q VSS
DDRG Latch
ST
Input
RD DDRG Buffer
Q D
EN
EN
RD PORTG
PCFG3:PCFG0
To other pads
VAIN
CHS3:CHS0
To other pads
Peripheral Data In
Data Bus
D Q
EN
EN
RD_PORTG
D
VDD
WR_PORTG
CK
P Q
RD_DDRG
Q D
N
Q WR_DDRG
CK
Data Bus
D Q
NEN
RD_PORTG
Q D
Port
VDD WR_PORTG
Data CK
1 Q
P 0
RD_DDRG
Q D
N WR_DDRG
CK
Q R
OUTPUT
OUTPUT ENABLE
12h, Bank 5 DDRG Data Direction Register for PORTG 1111 1111 1111 1111
13h, Bank 5 PORTG RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/ xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0 AN1 AN2 AN3
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTG.
I/O pin
D Q
N
WR DDRH
CK Q VSS
DDRH Latch
ST
Input
RD DDRH Buffer
Q D
EN
EN
RD PORT
PCFG3:PCFG0
To other pads
VAIN
CHS3:CHS0
To other pads
Data Bus
D Q
EN
EN
RD_PORTH
VDD D
WR_PORTH
CK
P Q
RD_DDRH
Q D
N WR_DDRH
Q CK
10h, Bank 8 DDRH Data Direction Register for PORTH 1111 1111 1111 1111
RH7/ RH6/ RH5/ RH4/
11h, Bank 8 PORTH RH3 RH2 RH1 RH0 0000 xxxx 0000 uuuu
AN15 AN14 AN13 AN12
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged
Data Bus
D Q
EN
EN
RD_PORTJ
VDD D
WR_PORTJ
CK
P Q
RD_DDRJ
Q D
N WR_DDRJ
Q CK
Value on,
MCLR,
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
WDT
BOR
12h, Bank 8 DDRJ Data Direction Register for PORTJ 1111 1111 1111 1111
13h, Bank 8 PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged
I/O
VIL
C(1)
PORTx, PINy
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
FIGURE 12-2: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
Output
(PSOUT) (Note 3)
Sampled (Note 2)
Prescaler
Output
(Note 1)
Increment
TMR0
TMR0 T0 T0 + 1 T0 + 2
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: ↑ = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ALE
Fetch
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Instruction Write to TMR0L Read TMR0L Read TMR0L Read TMR0L
Executed
(Value = NT0) (Value = NT0) (Value = NT0 +1)
TMR0H
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
TMR0H 12 12 13 AB
TMR0L FE FF 56 57 58
Note: In this example, old TMR0 value is 12FEh, new value of AB56h is written.
05h, Unbanked T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 — 0000 000- 0000 000-
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
0Bh, Unbanked TMR0L TMR0 Register; Low Byte xxxx xxxx uuuu uuuu
0Ch, Unbanked TMR0H TMR0 Register; High Byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0', q = value depends on condition. Shaded cells are not used by Timer0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
FOSC/4 0
RESET
1 TMR1
Set TMR1IF
TMR1ON (PIR1<4>)
Comparator<8>
Comparator x8
(TCON2<0>) Equal
TMR1CS
(TCON1<0>) PR1
RB4/TCLK12
1
RESET
FOSC/4 0 TMR2
Set TMR2IF
TMR2ON (PIR1<5>)
(TCON2<1>) Comparator<8>
Comparator x8
Equal
TMR2CS
(TCON1<1>) PR2
1
RB4/TCLK12 0
FOSC/4
TMR1ON
(TCON2<0>)
MSB LSB
TMR1CS
(TCON1<0>) RESET
TMR2 x 8 TMR1 x 8
Comparator<8>
Comparator x16
Set Interrupt TMR1IF Equal
(PIR1<4>)
PR2 x 8 PR1 x 8
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
10h, Bank 2 TMR1 Timer1’s Register xxxx xxxx uuuu uuuu
11h, Bank 2 TMR2 Timer2’s Register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
14h, Bank 2 PR1 Timer1 Period Register xxxx xxxx uuuu uuuu
15h, Bank 2 PR2 Timer2 Period Register xxxx xxxx uuuu uuuu
10h, Bank 3 PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----
10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0', q = value depends on condition.
Shaded cells are not used by Timer1 or Timer2.
0 10 20 30 40 0 10 20 30 40 0
PWM
Output
period of PWM1 = [(PR1) + 1] x 4TOSC The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:
period of PWM2 = [(PR1) + 1] x 4TOSC or ADDWF PW1DCH. This may cause duty cycle outputs
[(PR2) + 1] x 4TOSC that are unpredictable.
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
10h, Bank 2 TMR1 Timer1’s Register xxxx xxxx uuuu uuuu
11h, Bank 2 TMR2 Timer2’s Register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
14h, Bank 2 PR1 Timer1 Period Register xxxx xxxx uuuu uuuu
15h, Bank 2 PR2 Timer2 Period Register xxxx xxxx uuuu uuuu
10h, Bank 3 PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ----
10h, Bank 7 PW3DCL DC1 DC0 TM2PW3 — — — — — xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on conditions.
Shaded cells are not used by PWM Module.
FIGURE 13-5: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
RB5/TCLK3 TMR3ON
(TCON2<2>)
Capture2
Edge select, Enable
Prescaler select
RB1/CAP2
2 CA2H CA2L
Capture3
Edge select, Enable
Prescaler select
RG4/CAP3
2 CA3H CA3L
Capture4
Edge select, Enable
Prescaler select
RE3/CAP4
2 CA4H CA4L
RB5/TCLK3 TMR3ON
TMR3CS (TCON2<2>)
(TCON1<2>)
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
12h, Bank 2 TMR3L Holding Register for the Low Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
13h, Bank 2 TMR3H Holding Register for the High Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
16h, Bank 2 PR3L/CA1L Timer3 Period Register, Low Byte/Capture1 Register, Low Byte xxxx xxxx uuuu uuuu
17h, Bank 2 PR3H/CA1H Timer3 Period Register, High Byte/Capture1 Register, High Byte xxxx xxxx uuuu uuuu
14h, Bank 3 CA2L Capture2 Low Byte xxxx xxxx uuuu uuuu
15h, Bank 3 CA2H Capture2 High Byte xxxx xxxx uuuu uuuu
12h, Bank 7 CA3L Capture3 Low Byte xxxx xxxx uuuu uuuu
13h, Bank 7 CA3H Capture3 High Byte xxxx xxxx uuuu uuuu
14h, Bank 7 CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu
15h, Bank 7 CA4H Capture4 High Byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are not used by Capture.
FIGURE 13-7: TIMER1, TIMER2 AND TIMER3 OPERATION (IN COUNTER MODE)
TCLK12
or TCLK3
WR_TMR
RD_TMR
TMRxIF
MOVWF MOVFP MOVFP
Instruction TMRx TMRx,W TMRx,W
Executed Write to TMRx Read TMRx Read TMRx
AD15:AD0
ALE
Instruction MOVWF MOVF MOVF MOVLB 3 BSF NOP BCF NOP NOP NOP NOP
Fetched TMR1 TMR1, W TMR1, W TCON2, 0 TCON2, 0
Write TMR1 Read TMR1 Read TMR1 Stop TMR1 Start TMR1
TMR1 04h 05h 03h 04h 05h 06h 07h 08h 00h
PR1
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1 TMR1
Reads 03h Reads 04h
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
BRG ÷4
Sync/Async Sync/Async
Sync/Async TSR
CK/TX ÷ 16
Clock
Start 0 1 • • • 7 8 Stop
Load
DT TXEN/
Write to TXREG
8 Bit Count
TXREG 0 1 ••• 7
Interrupt
TXSTA<0>
Data Bus
TXIE
OSC ÷4 Interrupt
BRG
Master/Slave Sync/Async
Sync Async/Sync
RCIE
Enable
Buffer
Logic Bit Count
CK ÷ 16
START
SPEN Detect SREN/
CREN/
Buffer Majority RSR Start_Bit
Clock
Logic Detect
RX MSb LSb
Data
Stop 8 7 • • • 1 0
FIFO
RX9 Logic
Async/Sync
RCREG
RX9D 7 ••• 1 0 Clk
FERR
FIFO
FERR RX9D 7 ••• 1 0
Data Bus
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
USART1
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
USART2
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Baud Rate Generator.
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(TX/CK pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit
Word 1
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
Write to TXREG
Word 1 Word 2
BRG output
(shift clock)
TX
(TX/CK pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0
Word 1 Word 2
TXIF bit
Word 1 Word 2
Transmit Shift Reg. Transmit Shift Reg.
TRMT bit
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 0 TXREG1 Serial Port Transmit Register (USART1) xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register (USART1) 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 Serial Port Transmit Register (USART2) xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register (USART2) 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous transmission.
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Samples
RX START bit
(RX/DT pin)
x16 CLK
First rising edge of x16 clock after RX pin goes low
Q2, Q4 CLK
RX sampled low
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous reception.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for synchronous master transmission.
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
TRMT
’1’
TXEN
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
Once Synchronous mode is selected, reception is 1. Initialize the SPBRG register for the appropriate
enabled by setting either the SREN (RCSTA<5>) bit or baud rate. See Section 14.1 for details.
the CREN (RCSTA<4>) bit. Data is sampled on the RX/ 2. Enable the synchronous master serial port by
DT pin on the falling edge of the clock. If SREN is set, setting bits SYNC, SPEN, and CSRC.
then only a single word is received. If CREN is set, the 3. If interrupts are desired, then set the RCIE bit.
reception is continuous until CREN is reset. If both bits 4. If 9-bit reception is desired, then set the RX9 bit.
are set, then CREN takes precedence. After clocking 5. If a single reception is required, set bit SREN.
the last bit, the received data in the Receive Shift For continuous reception set bit CREN.
Register (RSR) is transferred to RCREG (if it is empty).
6. The RCIF bit will be set when reception is com-
If the transfer is complete, the interrupt bit RCIF is set.
plete and an interrupt will be generated if the
The actual interrupt can be enabled/disabled by set-
RCIE bit was set.
ting/clearing the RCIE bit. RCIF is a read only bit which
is reset by the hardware. In this case, it is reset when 7. Read RCSTA to get the ninth bit (if enabled) and
RCREG has been read and is empty. RCREG is a dou- determine if any error occurred during reception.
ble buffered register; i.e., it is a two deep FIFO. It is 8. Read the 8-bit received data by reading
possible for two bytes of data to be received and trans- RCREG.
ferred to the RCREG FIFO and a third byte to begin 9. If any error occurred, clear the error by clearing
shifting into the RSR. On the clocking of the last bit of CREN.
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve Note: To terminate a reception, either clear the
the two bytes in the FIFO. The OERR bit has to be SREN and CREN bits, or the SPEN bit.
cleared in software. This is done by clearing the CREN This will reset the receive logic so that it will
bit. If OERR is set, transfers from RSR to RCREG are be in the proper state when receive is re-
inhibited, so it is essential to clear the OERR bit if it is enabled.
set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
SREN bit
CREN bit ’0’ ’0’
RCIF bit
Read
RCREG
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for synchronous master reception.
16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
16h, Bank 4 TXREG2 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for synchronous slave transmission.
16h, Bank1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for synchronous slave reception.
SSPBUF reg
FIGURE 15-3: I2C MASTER MODE
BLOCK DIAGRAM
SSPSR reg Internal
Data Bus
SDI bit0 Shift
Clock Read Write
SSPADD<6:0>
SDO 7
Baud Rate Generator
SS Edge Shift
Select Clock
SSPSR reg
2
SDA MSb LSb
Clock Select
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (in I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit AKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 2 PEN: STOP Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 0 SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle.
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
SDO SDI
SDI SDO
Shift Register Shift Register
(SSPSR) (SSPSR)
PROCESSOR 1 PROCESSOR 2
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
SCK modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
14h, Bank 6 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
13h, Bank 6 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
FIGURE 15-10: I2C SLAVE MODE BLOCK Match Detect Addr Match
DIAGRAM
Internal SSPADD reg
Data Bus
Read Write START and STOP bit Set/Clear S bit
and
Detect/Generate Clear/Set P, bit
SSPBUF reg (SSPSTAT reg)
SCL
and Set SSPIF
Shift
Clock Two pins are used for data transfer. These are the SCL
SSPSR reg
pin, which is the clock and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
SDA MSb LSb
ured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
Match Detect Addr Match SSPEN (SSPCON1<5>).
The MSSP module has six registers for I2C operation.
SSPADD reg
These are the:
• SSP Control Register1 (SSPCON1)
START and Set, Reset • SSP Control Register2 (SSPCON2)
STOP bit Detect S, P bits
(SSPSTAT reg) • SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I 2C oper-
ation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I 2C modes to be selected:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I 2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate DDR bits. Selecting an I 2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I 2C mode.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF
BF (SSPSTAT<0>)
Cleared in software From SSP Interrupt
SSPBUF is written in software Service Routine
CKP (SSPCON1<4>)
Receive First Byte of Address R/W = 0 Receive Second Byte of Address Receive First Byte of Address R/W=1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software Bus Master
terminates
transfer
BF (SSPSTAT<0>)
DS30289B-page 147
PIC17C7XX
FIGURE 15-15:
DS30289B-page 148
Bus Master
PIC17C7XX
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte
R/W = 0 R/W = 1
ACK ACK
SDA 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF Read of SSPBUF
contents of SSPSR
I2C SLAVE-RECEIVER (10-BIT ADDRESS)
UA (SSPSTAT<1>)
FIGURE 15-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in Software
SSPBUF is Read
SSPOV (SSPCON1<6>) ’0’
07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0000 000- 0000
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
10h. Bank 6 SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h, Bank 6 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
12h, Bank 6 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
13h, Bank 6 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode.
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Cntl
Acknowledge
Generate
SCL
SDA DX DX-1
BRG decrements
(on Q2 and Q4 cycles).
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
SSPEN = 1,
SSPCON1<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Yes
No
Yes No No BRG
SCL= 0? SDA = 0? Rollover?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit.
No No BRG
SCL = 0? Rollover?
Yes
Yes
Reset BRG
Force SCL = 0,
START Condition Done,
Clear SEN
and set SSPIF
1st Bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here
End of Xmit
TBRG
SCL TBRG
Sr = Repeated Start
Start
Idle Mode,
B SSPEN = 1,
SSPCON1<3:0> = 1000
RSEN = 1
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
BRG No
Rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Bus Collision,
No
Set BCLIF, SDA = 1?
Release SDA,
Clear RSEN
Yes
C A
B
C
A
Yes
No No No BRG
SCL = 1? SDA = 0? Rollover?
Yes Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S
No No BRG
SCL = ’0’? Rollover?
Yes Yes
Force SCL = 0,
Reset BRG Repeated Start
condition done,
Clear RSEN,
Set SSPIF.
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Release SDA so
Yes
Num_Clocks Slave can drive ACK,
= 8? Force BF = 0
No
Load BRG with
Load BRG with SSPADD<6:0>,
SSPADD<6:0>, start BRG count
Start BRG Count,
SDA = Current Data bit
BRG No
Rollover?
BRG No
Rollover?
Yes
Yes
Yes
Read SDA and place into
ACKSTAT bit (SSPCON2<6>)
No No No
BRG SDA = Yes
Rollover? SCL = 0? Data bit?
Force SCL = 0,
Yes
Set SSPIF
Yes Reset BRG
Num_Clocks
= Num_Clocks + 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPSTAT<0>)
PEN
R/W
I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS30289B-page 161
PIC17C7XX
PIC17C7XX
15.2.12 I2C MASTER MODE RECEPTION 15.2.12.1 BF Status Flag
Master mode reception is enabled by programming the In receive operation, BF is set when an address or data
receive enable bit, RCEN (SSPCON2<3>). byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
Note: The SSP Module must be in an IDLE
STATE before the RCEN bit is set, or the 15.2.12.2 SSPOV Status Flag
RCEN bit will be disregarded.
In receive operation, SSPOV is set when 8 bits are
The baud rate generator begins counting and on each received into the SSPSR, and the BF flag is already set
rollover, the state of the SCL pin changes (high to low/ from a previous reception.
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable 15.2.12.3 WCOL Status Flag
flag is automatically cleared, the contents of the If the user writes the SSPBUF when a receive is
SSPSR are loaded into the SSPBUF, the BF flag is set, already in progress (i.e., SSPSR is still shifting in a data
the SSPIF is set and the baud rate generator is sus- byte), then WCOL is set and the contents of the buffer
pended from counting, holding SCL low. The SSP is are unchanged (the write doesn’t occur).
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an acknowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
Idle Mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
Start Count
BRG No
Rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Sample SDA,
Shift Data into SSPSR
BRG No SCL = 0? No
Rollover?
Yes Yes
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move Contents of SSPSR
into SSPBUF,
Clear RCEN.
DS30289B-page 164
Write to SSPCON2<4>
to Start Acknowledge Sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1)
Begin START Condition ACK from Master Set ACKEN, Start Acknowledge Sequence
Master Configured as a Receiver SDA = ACKDT = 0 SDA = ACKDT = 1
PIC17C7XX
Bus Master
ACK is Not Sent Terminates
Transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data Shifted in on Falling Edge of CLK Set SSPIF at End
of Receive Set SSPIF Interrupt
Set SSPIF interrupt at End of Acknow-
Set SSPIF Interrupt ledge sequence
at end of receive
at End of Acknowledge
SSPIF Sequence
Set P bit
Cleared in Software Cleared in software Cleared in software Cleared in Software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU Software and SSPIF
Responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Idle Mode
Set ACKEN
Force SCL = 0
BRG Yes
Rollover?
No
No
SCL = 0?
Yes
No BRG
Rollover?
Yes
SDA = 1?
Yes
No
Force SCL = 1
Yes
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG.
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
Force SDA = 0
SCL Doesn’t Change
BRG No
Rollover?
Yes
No
SDA = 0? Release SDA,
Start BRG
Yes
Start BRG
BRG No
Rollover?
BRG No Yes
Rollover?
Bus Collision Detected,
No
Yes P bit Set? Set BCLIF,
Clear PEN
De-assert SCL,
SCL = 1
Yes
Yes
SCL
SDA
SDA
BCLIF
SDA
SCL
Set SEN, enable START SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1. SSP module reset into IDLE state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software.
SSPIF
SDA = 0, SCL = 1
TBRG TBRG
SDA
FIGURE 15-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SDA SDA pulled low by other master.
Reset BRG and assert SDA.
SCL S
SCL pulled low after BRG
Time-out.
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1.
BCLIF ’0’
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF. in software.
SDA
SCL
RSEN
BCLIF
Cleared in software.
S ’0’ ’0’
TBRG TBRG
SDA
SCL
S ’0’ ’0’
PEN
BCLIF
P ’0’ ’0’
SDA
PEN
BCLIF
P ’0’
SSPIF ’0’
The supply voltage limits the minimum value of resistor The SMP bit is the slew rate control enabled bit. This bit
Rp due to the specified minimum sink current of 3 mA is in the SSPSTAT register and controls the slew rate of
at VOL max = 0.4V for the specified output stages. For the I/O pins when in I2C mode (master or slave).
DEVICE
Rp Rp
Rs Rs
SDA
SCL
Cb = 10 - 400 pF
Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is
also connected.
// Function declarations
void main(void);
void WritePORTD(static unsigned char data);
void ByteWrite(static unsigned char address,static unsigned char data);
unsigned char ByteRead(static unsigned char address);
void ACKPoll(void);
// Main program
void main(void)
{
static unsigned char address; // I2C address of 24LC01B
static unsigned char datao; // Data written to 24LC01B
static unsigned char datai; // Data read from 24LC01B
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PCFG3:PCFG0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
000x A A A A A A A A A A A A A A A A
001x D A A A A A A A D A A A A A A A
010x D D A A A A A A D D A A A A A A
011x D D D A A A A A D D D A A A A A
100x D D D D A A A A D D D D A A A A
101x D D D D D A A A D D D D D A A A
110x D D D D D D A A D D D D D D A A
111x D D D D D D D D D D D D D D D D
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1011
AN15(1)
1011
AN14(1)
1011
AN13(1)
1011
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
VIN AN5
0100
(Input Voltage) AN4
0011
AN3
A/D 0010
Converter AN2
0001
AN1/VREF-
PCFG0 0000
AN0/VREF+
VREF-
(Reference AVSS
Voltage)
VREF+
AVDD
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
VDD
Sampling
Switch
VT = 0.6V
RS ANx RIC ≤ 1k SS RSS
CHOLD
VA CPIN I leakage = DAC capacitance
5 pF VT = 0.6V ± 500 nA = 120 pF
VSS
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
8TOSC 00 5
32TOSC 01 20
64TOSC 10 33
RC 11 —
Note: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
TABLE 16-2: TAD vs. DEVICE OPERATING FREQUENCIES (EXTENDED VOLTAGE DEVICES (LC))
8TOSC 00 2.67
32TOSC 01 10.67
64TOSC 10 21.33
RC 11 —
Note: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
Note 1: When reading the port register, any pin Note: The GO/DONE bit should NOT be set in
configured as an analog input channel will the same instruction that turns on the A/D.
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana- Clearing the GO/DONE bit during a conversion will
log input. Analog levels on a digitally abort the current conversion. The A/D result register
configured input will not affect the conver- pair will NOT be updated with the partially completed A/
sion accuracy. D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
2: Analog levels on any pin that is defined as completed conversion (or the last value written to the
a digital input (including the AN15:AN0 ADRESH:ADRESL registers). After the A/D conversion
pins), may cause the input buffer to con- is aborted, a 2TAD wait is required before the next
sume current that is out of the devices acquisition is started. After this 2TAD wait, acquisition
specification. on the selected channel is automatically started.
In Figure 16-4, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts.
Holding capacitor is disconnected from analog input (typically 100 ns).
Set GO bit
Next Q4: ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
No No
No No
Wait 2TAD
10-Bit Result
ADFM = 1 ADFM = 0
7 2107 0 7 0765 0
0000 00 RESULT RESULT 0000 00
10-bits 10-bits
1023.5 LSb
1022 LSb
1023 LSb
0.5 LSb
1.5 LSb
2.5 LSb
1 LSb
2 LSb
3 LSb
POR,
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCLR, WDT
BOR
06h, unbanked CPUSTA — — STAKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
07h, unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
10h, Bank 5 DDRF Data Direction Register for PORTF 1111 1111 1111 1111
RF7/ RF6/ RF5/ RF4/ RF3/ RF2/ RF1/ RF0/
11h, Bank 5 PORTF 0000 0000 0000 0000
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4
12h, Bank 5 DDRG Data Direction register for PORTG 1111 1111 1111 1111
RG7/ RG6/ RG5/ RG4/ RG3/ RG2/ RG1/ RG0/
13h, Bank 5 PORTG xxxx 0000 uuuu 0000
TX2/CK2 RX2/DT2 PWM3 CAP3 AN0/VREF+ AN1/VREF- AN2 AN3
14h, Bank 5 ADCON0 CHS3 CHS2 CHS1 CHS0 — GO/DONE — ADON 0000 -0-0 0000 -0-0
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h, Bank 5 ADRESL A/D Result Low Register xxxx xxxx uuuu uuuu
17h, Bank 5 ADRESH A/D Result High Register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note: Other (non power-up) RESETS include: external RESET through MCLR and Watchdog Timer Reset.
Low (L) Table Read Addr. U-x U-x R/P-1 U-x R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
FE07h - FE00h — — PM1 — PM0 WDTPS1 WDTPS0 FOSC1 FOSC0
bit 15 bit 8 bit 7 bit 0
bits 7H, 6L, 4L PM2, PM1, PM0: Processor Mode Select bits
111 = Microprocessor mode
110 = Microcontroller mode
101 = Extended Microcontroller mode
000 = Code Protected Microcontroller mode
bit 6H BODEN: Brown-out Detect Enable
1 = Brown-out Detect circuitry is enabled
0 = Brown-out Detect circuitry is disabled
bits 3L:2L WDTPS1:WDTPS0: WDT Postscaler Select bits
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
bits 1L:0L FOSC1:FOSC0: Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator
Shaded bits (—) Reserved
Bit Address
FOSC0 FE00h
FOSC1 FE01h
WDTPS0 FE02h
WDTPS1 FE03h
PM0 FE04h
PM1 FE06h
BODEN FE0Eh
PM2 FE0Fh
4 - to - 1 MUX WDTPS1:WDTPS0
WDT Enable
— Config See Figure 17-1 for location of WDTPSx bits in Configuration Word. (Note 1) (Note 1)
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
Legend: - = unimplemented, read as '0', q = value depends on condition. Shaded cells are not used by the WDT.
Note 1: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
GLINTD bit
Processor
INSTRUCTION FLOW in SLEEP
Instruction
Fetched Inst (PC) = SLEEP Inst (PC+1) Inst (PC+2)
Instruction Inst (PC+1) Dummy Cycle
Executed Inst (PC-1) SLEEP
To place the device into the Serial Programming Test VPP MCLR/VPP
mode, two pins will need to be placed at VIHH. These TEST CNTL TEST
are the TEST pin and the MCLR/VPP pin. Also, a Dev. CLK RA1/T0CKI
sequence of events must occur as follows:
Data I/O RA4/RX1/DT1
1. The TEST pin is placed at VIHH. Data CLK RA5/TX1/CK1
2. The MCLR/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that
must be met.
After this sequence, the Program Counter is pointing to
program memory address 0xFF60. This location is in VDD
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this, the device must To Normal
be clocked. The device clock source in this mode is the Connections
RA1/T0CKI pin. After delaying to allow the USART/SCI
to initialize, commands can be received. The flow is
shown in these 3 steps:
1. The device clock source starts.
2. Wait 80 device clocks for Boot ROM code to
configure the USART/SCI.
3. Commands may now be sent.
During Programming
Name Function Type Description
RA4/RX1/DT1 DT I/O Serial Data
RA5/TX1/CK1 CK I Serial Clock
RA1/T0CKI OSCI I Device Clock Source
TEST TEST I Test mode selection control input, force to VIHH
MCLR/VPP MCLR/VPP P Master Clear Reset and Device Programming Voltage
VDD VDD P Positive supply for logic and I/O pins
VSS VSS P Ground reference for logic and I/O pins
Literal and control operations Note: Status bits that are manipulated by the
15 8 7 0
device (including the interrupt flag bits) are
set or cleared in the Q1 cycle. So, there is
OPCODE k (literal)
no issue on doing R-M-W instructions on
k = 8-bit immediate value registers which contain these bits
TOSC
TSTFSZ f Test f, skip if 0 1 (2) 0011 0011 ffff ffff None 6,8
XORWF f,d Exclusive OR WREG with f 1 0000 110d ffff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f,b Bit Clear f 1 1000 1bbb ffff ffff None
BSF f,b Bit Set f 1 1000 0bbb ffff ffff None
BTFSC f,b Bit test, skip if clear 1 (2) 1001 1bbb ffff ffff None 6,8
BTFSS f,b Bit test, skip if set 1 (2) 1001 0bbb ffff ffff None 6,8
BTG f,b Bit Toggle f 1 0011 1bbb ffff ffff None
LITERAL AND CONTROL OPERATIONS
ADDLW k ADD literal to WREG 1 1011 0001 kkkk kkkk OV,C,DC,Z
ANDLW k AND literal with WREG 1 1011 0101 kkkk kkkk Z
CALL k Subroutine Call 2 111k kkkk kkkk kkkk None 7
Description: The contents of WREG are added to Encoding: 0000 111d ffff ffff
the 8-bit literal ’k’ and the result is Description: Add WREG to register ’f’. If ’d’ is 0 the
placed in WREG. result is stored in WREG. If ’d’ is 1 the
:RUGV result is stored back in register ’f’.
&\FOHV Words: 1
ADDWFC ADD WREG and Carry bit to f ANDLW And Literal with WREG
Syntax: [ label ] ADDWFC f,d Syntax: [ label ] ANDLW k
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255
d ∈ [0,1] Operation: (WREG) .AND. (k) → (WREG)
Operation: (WREG) + (f) + C → (dest) Status Affected: Z
Status Affected: OV, C, DC, Z Encoding: 1011 0101 kkkk kkkk
Encoding: 0001 000d ffff ffff
Description: The contents of WREG are AND’ed with
Description: Add WREG, the Carry Flag and data the 8-bit literal 'k'. The result is placed in
memory location ’f’. If ’d’ is 0, the result is WREG.
placed in WREG. If ’d’ is 1, the result is Words: 1
placed in data memory location ’f’.
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity:
Decode Read literal Process Write to
Q1 Q2 Q3 Q4 'k' Data WREG
Decode Read Process Write to
register ’f’ Data destination
Example: ANDLW 0x5F
Before Instruction
Example: ADDWFC REG 0
WREG = 0xA3
Before Instruction After Instruction
Carry bit = 1
WREG = 0x03
REG = 0x02
WREG = 0x4D
After Instruction
Carry bit = 0
REG = 0x02
WREG = 0x50
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process No Q1 Q2 Q3 Q4
register ’f’ Data operation Decode Read Process No
register ’f’ Data operation
If skip:
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
operation operation operation operation
Description: Decrement register ’f’. If ’d’ is 0, the Encoding: 0001 011d ffff ffff
result is stored in WREG. If ’d’ is 1, the Description: The contents of register ’f’ are decre-
result is stored back in register ’f’. mented. If ’d’ is 0, the result is placed in
Words: 1 WREG. If ’d’ is 1, the result is placed
back in register ’f’.
Cycles: 1 If the result is 0, the next instruction,
Q Cycle Activity: which is already fetched is discarded
and a NOP is executed instead, making
Q1 Q2 Q3 Q4
it a two-cycle instruction.
Decode Read Process Write to
register ’f’ Data destination Words: 1
Cycles: 1(2)
Q Cycle Activity:
Example: DECF CNT, 1
Q1 Q2 Q3 Q4
Before Instruction
CNT = 0x01 Decode Read Process Write to
register ’f’ Data destination
Z = 0
After Instruction If skip:
CNT = 0x00 Q1 Q2 Q3 Q4
Z = 1
No No No No
operation operation operation operation
Description: The contents of register ’f’ are incre- Encoding: 0001 111d ffff ffff
mented. If ’d’ is 0, the result is placed in Description: The contents of register ’f’ are incre-
WREG. If ’d’ is 1, the result is placed mented. If ’d’ is 0, the result is placed in
back in register ’f’. WREG. If ’d’ is 1, the result is placed
Words: 1 back in register ’f’.
If the result is 0, the next instruction,
Cycles: 1 which is already fetched is discarded
Q Cycle Activity: and a NOP is executed instead, making
it a two-cycle instruction.
Q1 Q2 Q3 Q4
Decode Read Process Write to Words: 1
register ’f’ Data destination Cycles: 1(2)
Q Cycle Activity:
Example: INCF CNT, 1 Q1 Q2 Q3 Q4
Before Instruction Decode Read Process Write to
register ’f’ Data destination
CNT = 0xFF
Z = 0 If skip:
C = ?
Q1 Q2 Q3 Q4
After Instruction
No No No No
CNT = 0x00
operation operation operation operation
Z = 1
C = 1
Example: MOVLR 5
Before Instruction
BSR register = 0x22
After Instruction
BSR register = 0x52
Example: RETFIE
Example: CALL TABLE ; WREG contains table
After Interrupt ; offset value
PC = TOS ; WREG now has
; table value
GLINTD = 0 :
TABLE
ADDWF PC ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of k7
RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry
Syntax: [ label ] RLNCF f,d Syntax: [ label ] RRCF f,d
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
d ∈ [0,1] d ∈ [0,1]
Operation: f<n> → d<n+1>; Operation: f<n> → d<n-1>;
f<7> → d<0> f<0> → C;
Status Affected: None C → d<7>
Description: The contents of register ’f’ are rotated Encoding: 0001 100d ffff ffff
one bit to the left. If ’d’ is 0, the result is Description: The contents of register ’f’ are rotated
placed in WREG. If ’d’ is 1, the result is one bit to the right through the Carry
stored back in register ’f’. Flag. If ’d’ is 0, the result is placed in
WREG. If ’d’ is 1, the result is placed
register f
back in register ’f’.
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity:
Decode Read Process Write to
register ’f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
register ’f’ Data destination
Example: RLNCF REG, 1
Before Instruction
C = 0 Example: RRCF REG1,0
REG = 1110 1011 Before Instruction
After Instruction REG1 = 1110 0110
C = C = 0
REG = 1101 0111 After Instruction
REG1 = 1110 0110
WREG = 0111 0011
C = 0
Q1 Q2 Q3 Q4 Before Instruction
WREG = 1
Decode No Process Go to
C = ?
operation Data sleep
After Instruction
WREG = 1
Example: SLEEP C = 1 ; result is positive
Z = 0
Before Instruction Example 2:
TO = ?
PD = ? Before Instruction
WREG = 2
After Instruction C = ?
TO = 1†
PD = 0 After Instruction
† If WDT causes wake-up, this bit is cleared WREG = 0
C = 1 ; result is zero
Z = 1
Example 3:
Before Instruction
WREG = 3
C = ?
After Instruction
WREG = FF ; (2’s complement)
C = 0 ; result is negative
Z = 0
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register 'f' Data destination Decode Read Process Write to
register 'f' Data destination
After Instruction
RAM = 0xAF
TBLAT = 0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t = 1
RAM = ?
TBLAT = 0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM = 0x00
TBLAT = 0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Program Data
Memory 15 0
Memory
TBLPTR
15 8 7 0
16 bits 8 bits
TBLAT
Description: The contents of WREG are XOR’ed Encoding: 0000 110d ffff ffff
with the 8-bit literal 'k'. The result is Description: Exclusive OR the contents of WREG
placed in WREG. with register 'f'. If 'd' is 0, the result is
Words: 1 stored in WREG. If 'd' is 1, the result is
stored back in the register 'f'.
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity:
Decode Read Process Write to
literal 'k' Data WREG Q1 Q2 Q3 Q4
Decode Read Process Write to
register 'f' Data destination
Example: XORLW 0xAF
Before Instruction
WREG = 0xB5 Example: XORWF REG, 1
After Instruction Before Instruction
WREG = 0x1A REG = 0xAF 1010 1111
WREG = 0xB5 1011 0101
After Instruction
REG = 0x1A 0001 1010
WREG = 0xB5
The PRO MATE II device programmer has program- 19.12 PICDEM 2 Low Cost PIC16CXX
mable VDD and VPP supplies, which allow it to verify Demonstration Board
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem-
and error messages, keys to enter commands and a onstration board that supports the PIC16C62,
modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74
package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft-
device programmer can read, verify, or program ware is included to run the basic demonstration pro-
PICmicro devices. It can also set code protection in this grams. The user can program the sample
mode. microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
19.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and
Development Programmer easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro-
easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and
nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of
Integrated Development Environment software makes the features include a RS-232 interface, push button
using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a
The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus
ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD
count devices, such as the PIC16C92X and module and a keypad.
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
24CXX/
25CXX/
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
MPLAB® Integrated
TABLE 19-1:
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB® C17 C Compiler
á á
á á
MPLAB® C18 C Compiler
MPASMTM Assembler/
Software Tools
MPLINKTM Object Linker á
á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
ICEPICTM In-Circuit Emulator á á á
á
á
á
á
á
á
á
á
MPLAB® ICD In-Circuit
* *
Debugger
á
á
á
PICSTART® Plus Entry Level
Development Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PRO MATE® II
Universal Device Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PICDEMTM 2 Demonstration † †
Board
á
á
á
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEMTM 3 Demonstration
Board
á
á
PICDEMTM 17 Demonstration
Board
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
DS30289B-page 237
PIC17C7XX
6.0 V
5.5 V
5.0 V PIC17C7XX-33
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
33 MHz
Frequency
6.0 V
5.5 V
5.0 V PIC17C7XX-16
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
Frequency
6.0 V
5.5 V
5.0 V
4.5 V
Voltage
PIC17LC7XX-08
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
8 MHz
Frequency
6.0 V
5.5 V
5.0 V PIC17C7XX/CL
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
8 MHz 33 MHz
Frequency
Note 1: When using the Table Write for internal programming, the device temperature must be less than 40°C.
2: For In-Circuit Serial Programming (ICSP), refer to the device programming specification.
Data in invalid
0.9 VDD
0.1 VDD
Rise Time Fall Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4
4
2
OSC2 †
Q4 Q1 Q2 Q3
OSC1
10 11
22
OSC2 † 23
13 12
18
14 19 16
I/O Pin
(input)
17 15
VDD
MCLR
30
Internal
POR/BOR
33
PWRT
Time-out
OSC 32
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
35
Address/
Data
TABLE 20-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
Sym Characteristic Min Typ† Max Units Conditions
No.
RA1/T0CKI
40 41
42
TCLK12
or
TCLK3
45 46
47
48
48
TMRx
CAP pin
(Capture mode)
50 51
52
PWM pin
(PWM mode)
53 54
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
Note: Refer to Figure 20-5 for load conditions.
82
SS
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb IN BIT6 - - - -1 LSb IN
74
Note: Refer to Figure 20-5 for load conditions.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
90 Tsu:sta START condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns Only relevant for
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — — Repeated Start condition
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
91 Thd:sta START condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns After this period, the first
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — — clock pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
92 Tsu:sto STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
93 Thd:sto STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — —
1 MHz mode(1) 2(TOSC)(BRG + 1) — —
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
SDA
Out
Note: Refer to Figure 20-5 for load conditions.
TX/CK
pin 121 121
RX/DT
pin
120 122
TX/CK
pin 125
RX/DT
pin
126
RX START bit
(RX/DT pin)
121A
x16 CLK
Q2, Q4 CLK
120A
123A
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
125A 126A
Samples
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
ALE
OE
151
WR
150 154
AD<15:0> addr out data out addr out
152 153
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
166
ALE 164
168
OE 160
165 161
AD<15:0> Addr out Data in Addr out
150 162
151 163
’1’ 167 ’1’
WR
1.10
REXT ≥ 10 kΩ
1.08 CEXT = 100 pF
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0 10 20 25 30 40 50 60 70
T(°C)
4.0
3.5
3.0 R = 10k
2.5
FOSC (MHz)
2.0
1.5
CEXT = 22 pF, T = +25°C
1.0
0.5
0.0 R = 100k
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
4.0
3.5
R = 3.3k
3.0
2.5
FOSC (MHz)
R = 5.1k
2.0
1.5
1.0 R = 10k
CEXT = 100 pF, T = +25°C
0.5 R = 100k
0.0
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
2.0
1.8
1.6
1.4 R = 3.3k
1.2
R = 5.1k
FOSC (MHz)
1.0
0.8
R = 10k
0.6
0.4
CEXT = 300 pF, T = +25°C
0.2
R = 160k
0.0
4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
Average
CEXT REXT
FOSC @ 5V, +25°C
22 pF 10k 3.33 MHz ± 12%
100k 353 kHz ± 13%
100 pF 3.3k 3.54 MHz ± 10%
5.1k 2.43 MHz ± 14%
10k 1.30 MHz ± 17%
100k 129 kHz ± 10%
300 pF 3.3k 1.54 MHz ± 14%
5.1k 980 kHz ± 12%
10k 564 kHz ± 16%
160k 35 kHz ± 18%
500
450
400
350
Max @ -40°C
300
gm(µA/V)
Typ @ +25°C
250
200
150
Min @ +85°C
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
20
18
Max @ -40°C
16
14
Typ @ +25°C
12
gm(mA/V)
10
6
Min @ +85°C
4
2
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1.2
5.5V
0.8
5.0V
I DD (mA)
4.5V
0.6
4.0V
3.5V
0.4
3.0V
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
F OSC (M Hz)
FIGURE 21-8: MAXIMUM IDD vs. FOSC OVER VDD (LF MODE)
1.2
0.8
4.5V
4.0V
IDD (mA)
0.6
3.5V
3.0V
0.4
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
F OSC (M Hz )
16
5.5V
Ty pic al: statistical
Typical: s tatis tic al mean
mean@ 25°C
@ 25°C
14 Max imum: mean + 3σ (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C) 5.0V
Minimum: mean – 3s (-40°C to 125°C)
12
4.5V
10
IDD (mA)
4.0V
3.5V
2
3.0V
0
0 5 10 15 20 25 30 35
F OSC (M Hz )
FIGURE 21-10: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
18
5.5V
Typical: statistical
Typic al: statis mean
tical mean @ 25°C
@ 25°C
16 Max imum: mean
Maximum: mean + 3σ+(-40°C to 125°C)
3s (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.0V
14
4.5V
12
10
IDD (mA)
4
4.0V
3.5V
2
3.0V
0
0 5 10 15 20 25 30 35
F OSC (M Hz)
6.0
4.0
I PD (uA)
3.0
2.0
Typ
1.0
0.0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
FIGURE 21-12: TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, BOR ENABLED, -40°C to
+125°C)
2.0
1.4
1.2
M ax Res et
IDD (mA)
1.0
0.8
Ty p Reset (25C)
0.6
0.2
Max S leep
Ty p S leep (25C)
0.0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
18
16
14
12
M ax
10
IPD (uA)
Ty p
8
0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
FIGURE 21-14: TYPICAL AND MAXIMUM ∆IRBPU vs. VDD (MEASURED PER INPUT PIN,
-40°C TO +125°C)
300
Typical: statistical
Ty pic al: s tatis tic al mean mean
@ 25°C @ 25°C
250 Maximum:
Max imum: mean mean + 3σ + 3s (-40°C
(-40°C to 125°C)
to 125°C)
Minimum: mean –
Minimum: mean – 3s (-40°C 3σ (-40°C to 125°C)
to 125°C)
M ax im um
200
∆ I (uA)
150
Typical (25C)
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
40
Ty pic al:
Typical: s tatis tic almean
statistical mean @
@25°C
25°C
35 Max imum: mean + 3σ (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
30
M ax (125C)
25
WDT Period (ms)
20
15
Typ (25C)
10
M in (-40C)
5
0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
FIGURE 21-16: TYPICAL WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)
30
25
20
125C
WDT Period (ms)
85C
15
25C
10
-40C
0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V)
5.0
4.5
Max
4.0
Ty p (25C)
3.5
3.0
VOH (V)
2.5
M in
2.0
1.5
0.0
0 5 10 15 20 25
I OH (-m A)
FIGURE 21-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)
1 .6
1 .2
1 .0
VOL (V)
0 .8
T yp (2 5 C )
0 .6
M in ( - 4 0 C )
0 .4
0 .2
0 .0
0 5 10 15 20 25
IO L (m A)
3.0
2.0
V OH (V)
1.5
M in M ax
1.0
Ty p (25C)
0.5
0.0
0 5 10 15 20 25
I OH (-m A)
FIGURE 21-20: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)
2 .0
1 .8
1 .2
Ma x (1 2 5 C )
VOL (V)
1 .0
0 .8
0 .6
Typ (2 5 C )
0 .4
Min (-4 0 C )
0 .2
0 .0
0 5 10 15 20 25
I OL (m A)
1.8
1.6
Max
1.4
Ty p (25C)
Min
1.2
1.0
VIN (V)
0.8
0.6
0.2
0.0
3.0 3.5 4.0 4.5 5.0 5.5
V DD (V )
FIGURE 21-22: MAXIMUM AND MINIMUM VIN vs. VDD (ST Input, -40° C to +125°C)
3 .5
2 .5
Ma x Fa llin g
2 .0
VIN (V)
1 .5
Min Fa llin g
1 .0
0 .5
0 .0
3 .0 3 .5 4 .0 4 .5 5 .0 5 .5
V DD (V )
4 .0
3 .0
Min R is in g
2 .5
VIN (V)
2 .0
Ma x Fa llin g
Min Fa llin g
1 .5
1 .0
0 .5
0 .0
3 .0 3 .5 4 .0 4 .5 5 .0 5 .5
V DD (V )
XXXXXXXXXX PIC17C752
XXXXXXXXXX -08I/PT
XXXXXXXXXX
YYWWNNN 0017CAE
XXXXXXXXXXXXXXXXX PIC17C756A-08/L
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN 0048CAE
XXXXXXXXXXXX PIC17C762
XXXXXXXXXXXX -08I/PT
YYWWNNN 0017CAE
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XXXXXXXXXXXXXXXXX PIC17C766-08/L
XXXXXXXXXXXXXXXXX
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XXXXXXXXXXXXXXXXX
YYWWNNN 0048CAE
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