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Understand essentials

in high-speed PCB designs


By William Sun cessing technology of the
Principal Services AE PCB and define its cascade
Cadence Design Systems Inc. parameters.
E-mail: wanping@cadence.com 3. Research thoroughly on the
topological structure of the
The rapid development of su- signal cable, confirm the ter-
per-large-scale IC and com- minal connection strategies
puter technologies leverages and define the constraint
the system design trend toward rules of the signal cable.
high-speed devices and minia- 4. Drive the layout routing ac-
turization, as well as empha- cording to the constraint
sizes the problems of signal in- rules of the signal cable.
tegrity, power supply integrity 5. Perform sufficient verifica-
and electromagnetic compat- tion analysis after routing.
ibility (EMC/EMI) in the PCB
design. The cause of these prob- High-speed digital circuit
lems is the development of IC design gives emphasis on the
techniques that make the con- characteristics of passive de- Figure 3: Reference parameters will be input to the constraint manager
version speed of the IC port sig- vices, which include connec- of the Cadence PCB SI 610, and the system will compute automatically.
nal become faster. tion lines between the devices’
As the switch speed becomes LVTTL, GTLP and ECL. It is
faster, the high-frequency har- important to know the charac-
monics of digital signals make teristic parameters of digital IC
passive devices become com- devices and high-speed PCB de-
plex carriers. This is due to the signs such as the voltage mar-
parasitic parameters that cre- gin—the difference between the
ate a complicated passive net- output of the digital IC device
work on the signal transmission driver and the sensitivity of the
path. High-speed digital design digital IC devices receiver in the
should focus on the effects on worst condition. It is also the ba-
the signal transmission quality sis in setting the noise margin of
Figure 1: The voltage-level parameters are input to the constraint in passive devices (ringing and the digital IC devices receiver in
manager of the Cadence PCB SI 610, which carries out the layout routing. reflection), as well as crosstalk the process of high-speed PCB
and EMI. design. The rise/fall time of the
In digital systems design, I/O ports, PCBs and physical output signal would also help
the signal transmission on the encapsulations of the devices. If Device characteristics confirm the existence of high-
PCB is affected by parasitic pa- the digital signal switch oper- The first essential step for engi- speed effects in the system.
rameters (capacitance, induc- ates at a low speed, the passive neers dealing with high-speed DC characteristics are im-
tance and resistance) of the devices are the only carriers of PCB design is to understand the portant references when defin-
transmission paths or the the signal. These passive de- manufacturing and material ing the noise margin and up/
printed circuit line. Receiving vices will not affect transmis- technology of the digital IC they down overshoot. We may obtain
a severely distorted digital sig- sion quality of the digital signal. will use, such as CMOS, TTL, some related reference param-
nal causes instability or system eters such as VIL (low-level in-
abnormality. Signal integrity, put voltage), VIH (high-level in-
power supply integ rity and Chipset (receiver) put voltage), VOL (low-level out-
EMC/EMI problems should be put voltage) and V OH (high-
considered in high-speed sys- Qc Output from core level output voltage) from the
tem design. After considering datasheet, which are needed to
and analyzing signal integrity clk compute the noise margin and
Tflt_clkA Dc
in the design, simulation re- Tco_clkA
Clk
up/down overshoot.
sults may differ a lot from the When computing for the
actual, primarily because Clk in Tflt
noise margin, we need to know
analysis parameters in the tools Tco_data the minimum V IL and the
do not match the actual PCB Tco_clkB
Clk
maximum V IH thresholds of
Qp
parameters. There are five the digital device’s receiver,
steps engineers should take in Tflt_clkB and the minimum VOH and the
dealing with high-speed PCB clk Dp Input from core maximum V OL of the driver.
design: Because the input terminals of
1. Fully identify the technology Processor (driver) digital logic circuits always
and the AC/DC characteris- have two switch margins in the
tic of the devices, IBIS model process of the high-low level
collection and verification. Figure 2: Shown here is a synchronous clock example. Computing conversion:
2. Fully identify the basic pro- methods involved are not the same for different data signal timing modes. Low-level input switch mar-
VDD + 0.3V give a uniform reference point
Down overshoot = V IL_MIN between the AC parameters of
= 0.3V the device and the signal-integ-
rity analysis results to precisely
The parameters will be di- analyze the transmission delay
rectly input to the constraint caused by the line connection.
manager of the Cadence PCB SI When analyzing the timing,
610, which will carry out the we are primarily concerned
layout routing (Figure 1). about the following timing
AC characteristics of the parameters:
digital IC devices will guide us • TCYCLE—Clock frequency;
in system timing control, timing • TCO_MAX—After the clock sig-
parameters computation and nal uprising edge takes ef-
timing margin definition. We fect, the data signal out-
Figure 4: If the port driving ability choice is ignored in the FPGA applica- need to understand the AC tim- put will take effect after de-
tion, there can be problems such as additional high-speed effects. ing parameters in the device laying the maximum TCO_MAX
datasheet to know which param- (driver);
gin = max. VIL threshold – min. (Table 1). eters are needed by the PCB tool. • TCO_MIN—After the clock sig-
VIL threshold In the datasheet: The device datasheet shows nal uprising edge takes ef-
High-level input switch mar- VIL_MAX = max. VIL threshold the waveform relation between fect, the data signal output
gin = max. VIH threshold – min. VIH_MIN = min. VIH threshold the functions and timing pa- will be of no effect after delay-
VIH threshold rameters, as well as the AC pa- ing the minimum T CO_MIN
When applied in the rameters related to the I/O tim- (driver);
The logic input signal could computations: ing of the device. The measure- • T Setup_min —Minimum setup
be identified in the worst condi- High-level noise margin ment of the AC parameters is time of the data signal receiv-
tion. The following are used to (MIN_NOISE_MARGIN) = done in a special testing load ing (receiver);
compute for the theoretical VOH_MIN - VIH_MIN = 2.4V - 2V condition. Also, the IC device • THold_min—Minimum holding
value of the high- and low-level = 0.4V manufacturer gives the rela- time of the data signal receiv-
noise margins of special devices: Low-level noise margin ted testing condition in the ing (receiver).
High-level noise margin = (MIN_NOISE_MARGIN) = datasheet. The timing param-
min. VOH - max. VOH threshold > 0 VIL_MAX - VOL_MAX = 0.8V - 0.4V eters provided in the device In Table 2: TCO_MAX = tCD,
Low-level noise margin = = 0.4V datasheet usually include two TCO_MIN = tCDC, the data signal
min. VIL threshold – max. VOL > 0 parts: one created by the inner output maximum and mini-
The computation of the up/ logic delay of the device, the mum delay.
However, the minimum VIL down overshoot index is com- other created by the output In Table 3: TSetup_min = tSA or
threshold and maximum V IH monly based on the VIH_MAX and driver. Signal-integrity analysis tHD, the minimum setup time in
threshold are not provided in VIL_MIN found in Table 1; then tools deal with the interaction receiving the data signal;
the datasheet and appear as a we obtain: between the output driver and Thold_min = tHA or tHD, the mini-
high-/low-level input range Up overshoot = V IH_MAX = the transmission lines. We must mum holding time in receiving
the data signal.
While defining the system
data signal timing, we usually
Pulse type reflection Pulse type reflection pay attention to whether we will
4 0
adopt a synchronous or asyn-
3
5
chronous clock, since the com-
puting methods involved are
Voltage (V)

4
Voltage (V)

2 3 different. An example for the


1 2 synchronous clock is shown in
1
Figure 2. We first ascertain the
0 clock topological structure and
0
data signal direction to help
-1 -1
0 10 20 30 0 10 20 30 with the computation of the
Time(ns) Time (ns) timing parameters with the fol-
Design 102.1 Design 102.1 lowing formula:

TFLT ≥ THO_MAX + TCLK_SKEW – TCO_MIN + TADI


Figure 5: Results show that the right choice of driving ability of the I/O port will reduce high-speed effects.
(Compute the setup time)
Parameter condition Symbol Min Max Units Notes
TFLT ≤ TCYCLE + TCLK_SKEW – TCLK_JITTER –
Supply voltage Vdd , VddQ 3 3.6 V
– TCO_MAX – TSU_MIN – TADI
Input high voltage: Logic 1; All inputs Vh 2 Vdd + 0.3 V 22
(Compute the holding time)
Input low voltage: Logic 0; All inputs VIL -0.3 0.8 V 22
Input leakage current: Any input 0V ≤ Vin ≤ Vdd IL -5 5 A
Reference parameters such
(All other pins not under test = 0V)
as T CYCLE , T CO_MAX , T CO_MIN,
Output leakage current: DQs are disabled; Ioz -5 5 A
T Setup_min , T Hold_min from the
0V ≤ Vout ≤ VddQ
datasheet will be input to the
Output levels: Voh 2.4 - V
constraint manager of the Ca-
Output high voltage (Iout = -4mA)
VOL - 0.4 V dence PCB SI 610, and the sys-
Output low voltage (Iout = 4mA)
tem will compute automatically
Table 1: The minimum low-level input voltage threshold and maximum high-level input voltage threshold (Figure 3).
appear as high- and low-level input ranges in the datasheet. The IBIS model is the core of
consider matching the transmis-
sion line impedance. The dis-
tance between the transmission
line and the reference plane, and
the width of the transmission
line shall determine the target
impedance. Computed results,
however, usually differ from the
measurement of the transmis-
sion lines of the actual PCBs.
This is mainly due to lack of
understanding of the PCB pro-
cess technology, as well as igno-
rance of the error brought by
the process.
Figure 6: The actual signal frequency can be used to compute for the characteristic impedance needed.
Because of the tolerable
high-speed design analysis. The driving ability of the I/O ports 2.280e-010 1.769e+000/ manufacturing error in the pro-
accuracy and veracity of the is prog rammable according 1.520e-010 cess, the results of the formula
model will decide the correct- to different applications and dV/dt_f 1.578e+000/ (simplified model) are not pre-
ness of the design. It is an inter- interfaces. 2.660e-010 1.256e+000/ cise. The materials used in
national standard describing The I/O ports of Altera’s 4.180e-010 1.713e+000/ manufacturing have different
the IC device’s I/O characteris- Cyclone series have different 1.900e-010 thicknesses, tolerances and di-
tics. Commonly-used IBIS voltage levels, such as 1.5-, electric constants. The thick-
model standards are versions 1.8-, 2.5- and 3.3V that are With the above parameters, ness of the material changes
1.0, 2.1 and 3.2. Versions 1.0 implemented for various inter- the up/down switch speed of an before and after laminating it.
and 2.1 are commonly applied face technologies, such as I/O port with an 8mA driving There is a change in the dielec-
in early IC devices, while ver LVCMOS, LVTTL, SSTL, PCI, ability is larger than that of an tric constant when different
3.2 is used for new IC devices. LVDS and RSDS. The interface I/O port with a 2mA driving materials are mixed. There is
The IBIS model describes the application with LVCMOS and ability. If the port driving abil- also a difference between the
characteristics of the digital IC LVTTL has a variety of port ity choice is ignored in the real etch line width and the de-
I/O units and pins in the form driving ability choices such as FPGA application, there would sign line width. The thickness
of I/V and V/T tables. Most 2-, 4-, 8-, 12-, 16- and 24mA. be problems such as additional increase of the microstrip (top
digital IC manufacturers pro- Different port drive abilities high-speed effects and effects and bottom layer) changes after
vide the corresponding IBIS reflect different I/O character- on stability and reliability. We manufacturing and shaping.
model for the chips. istics—weak driving ability with can construct the point-to- These will all affect the preci-
The IBIS model librar y low working frequency, and point topological structure sion of the impedance calcula-
should be updated regularly as strong driving ability with the with the port of LVCMOS 3.3V, tion. At present, the usual ma-
digital IC manufacturers often high working frequency. The 2mA and 8mA driving ability terials of the PCBs are FR4, the
amend their IBIS model accord- switch speed parameters of the (Figure 4), with the working dielectric constant of which
ing to the changes in the IC LVCMOS 3.3V with port-driv- frequency set at 50MHz and changes with the signal fre-
manufacturing technology. ing abilities of 2mA and 8mA 2,000mil transmission lines quency. It is important to know
Adopting the old IBIS model are as follows: (50Ω impedance). The receiv- the manufacturing technology
may produce problems in the ing waveforms with 2mA and of the PCBs and obtain the
design results. 2mA: 8mA driving abilities are shown changes in material manufac-
There may be some inaccu- [Ramp] in Figure 5. turing parameters. Also, dur-
racies in the IBIS model pro- dV/dt_r 8.050e-001/ Simulation results show that ing analysis, the simulation cas-
vided by manufacturers, so 1.266e-009 5.180e-001/ the right choice of the driving cade parameters set by the ana-
verification should be carried 1.646e-009 9.473e-001/ ability of the I/O port shall lyzers do not take into account
out before simulation analysis. 8.862e-010 avoid and reduce the high- the manufacturing error, re-
Because of the wide applica- dV/dt_f 6.822e-001/ speed effects of PCBs. But in sulting in a big difference in
tion of FPGAs, more board- 1.646e-009 4.561e-001/ many applications of chips terms of precision in the simu-
level high-speed effects occur 2.279e-009 9.083e-001/ similar to FPGA, selection of lation and actual results.
on the PCBs. The reason for 1.393e-009 the driving ability of the I/O In the process of high-speed
this is that FPGA chip manu- port is usually neglected when PCB design, we should under-
facturers want to widen the ap- 8mA: using default values provided stand the technology, the lami-
plication range by working on [Ramp] by chip manufacturers. nating type of the PCB manu-
either low or high frequency to dV/dt_r 1.262e+000/ In the process of high-speed facturers, the PCB specifica-
obtain good adaptability. The 1.520e-010 1.153e+000/ PCB design, we usually have to tions, the parameter change

AC electrical characteristics (Vdd = 2.5V +/-5%, Ta = 0 to 70°C)


225MHz 200MHz 166MHz 150MHz 133MHz 100MHz
Symbol Parameter Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Output parameters
__ __ __ __ __ __
ICD Clock high to valid data 3.0 3.2 3.5 3.8 4.2 5 ns
__ __ __ __ __ __
ICDC Clock high to data change 1.0 1.0 1.0 1.5 1.5 1.5 ns

Table 2: TCO_MAX is equal to tCD, while TCO_MIN is equal to tCDC, the data signal output maximum and minimum delay.
before and after the process, matter which connection mode edge and delay of the receiver enough routing room in the
the relative parameter between is used, the connection conduc- signal. When signals are de- layout, since it needs more
the dielectric constants, char- tors between the input and the layed in the transmission pro- than the daisy-chain topologi-
acteristic impedance and the output are no longer simple cess, source signals overlap the cal structure. When routing,
working frequency. Process the conductors, but are now trans- reflection signal, which then the DRC online check in the
design with actual signal fre- mission lines. When signals causes the waveform distortion PCB edit environment should
quency in an entirely same switch between high and low of the receiver signals. These be opened. The constraint
setup as the PCB cascade in the states or come across imped- problems can be solved by manager will then ensure that
Allegro PCB Design 610 or PCB ances that do not match the changing the topological struc- the routing matches the rules.
SI 610 design environments transmission line impedance, ture of the signals.
and then compute for the char- signal integrity problems occur. After changing the topologi- Post-routing verification
acteristic impedance needed. After realizing the cause of cal structure of the signals in the Verification analysis after rout-
The simulation environment the signal integrity problems, symmetric routing, we can ob- ing is a necessary part of high-
result is close to the actual situ- we have to choose methods to tain an improvement in wave- speed design. The transmission
ation (Figure 6). eliminate these high-speed ef- form quality—problems of high- line assumes no dielectric loss,
fects. Problems can be identi- speed effects are almost elimi- but the signal transmission is
Signal cables fied by analysis with the point- nated. Proper topological struc- processed on actual PCBs that
In the process of PCB design, we to-multipoint multimode—Ad- ture analysis and definition of have transmission lines with
primarily consider key signals dress signal: highest frequency the signal cable are very impor- dielectric loss.
such as clock, data, address and = 62.5MHz; four receivers con- tant because they define the lay- Consequently, we need to de-
read-write signals. Before rout- nected, characteristic imped- out-routing rules. fine the topological structure of
ing the layout, we should pro- ance = 60Ω; topological struc- Lastly, layout-routing rules the key signal router after rout-
cess the topological structure ture = daisy-chain. can be def ined in the con- ing, then analyze and verify if
research on key signal lines, de- Although the characteristic straint manager. In this pro- the constraint rules and the pa-
fine the constraint rules of the impedance of the transmission cess, the constraint manager rameter setup of the virtual PCB
key signal cable properly, and lines is 60Ω, this does not can help the designer ensure environment meet the analysis
input instructions in the layout- match the input impedance of that the devices are in proper requirements. The topological
routing tool. There are several the receivers. In the waveform position. With the symmetry structure after the address line
connection modes for the key distortions of the signals at the topological-structure routing routing and the simulation
signal lines such as point-to- four receivers, the problems are modes defined in the process waveform match the results
point, point-to-multipoint and overshoot, attenuation, oscilla- of the topological structure of the analysis, satisfying the
multipoint-to-multipoint. No tion, non-monotonous signal analysis, there should be design requirements.