Isscc2008 Nand Tutorial

ISSCC 2008 Tutorial T7
NAND successful as a media for SSD
Ken Takeuchi
Graduate School of Frontier Sciences
Dept. of Electronics Engineering
University
y of Tokyo
y
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
http://www.lsi.t.u-tokyo.ac.jp
p y jp
Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 1

Definition of SSD
SSD : Solid State Drive

SSD can be anything.
: MP3 players
players, Camcorders
Camcorders, PC
PC, USB drive and …
Define SSD as a mass storage for PC application
in this tutorial.
SSD consists of NAND and NAND controller(+RAM)
J. Elliott, WinHEC 2007, SS-S499b_WH07.

Key Design Challenge of SSD
Need to understand of the device especially about

the reliability such as endurance, data retention,
and disturb.
disturb
Require co-design off NAND and NAND controllers

to best optimize both NAND and NAND controllers.
Also,, SW support
pp such as driver and OS essential.

Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
NAND Controller Circuit Design
Operating System for SSD
Summary

Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

NAND Overview
NAND Architecture
NAND Density Trend
NAND Performance
e o a ce Trende d
NAND Operation Principle

NAND Flash Cell Array
Page : program/read unit Block : Erase unit
Bitline
Bitline
Bitline
2 Select-gate 2 Select-gate
32 Word-lines Source-line 32 Word-lines
Memory cells are sandwiched by select gates.

Contactless structure : ideal 4F2 cell size
F.Masuoka, IEDM 1987, pp.552-555.

Top View of NAND Flash Cell Array
Source-line
S li
Bitline (second metal) (first metal)
STI
Active area
SGD SGD SGS SGS

Contact to bitline Word-lines Contact to source-line
Simple structure : High scalability,

scalability High yield
K. Imamiya, ISSCC 1999, pp.112-113.

MLC vs. SLC
SLC : Single-level cell or 1bit/cell
MLC : Multi-level cell or >2bit/cell
2bit/cell : Long production record since 2001
3bit/cell or 4bit/cell : R&D but may be commercialized in
the near future (2008?)
Existing SSD uses SLC but some manufactures
announce to produce MLC based SSD.
(Single level cell)
SLC (Single-level MLC (M lti le el cell)
(Multi-level
Number of memory cells Number of memory cells

0
“0” 1
“1” 0
“0” “1”
1 2
“2” 3
“3”
Vth Vth

NAND Density Trend
100
m]
2
ensity [[MB/mm
10
55% growth / year

1
Memory de
0.1
0.01
1994 1996 1998 2000 2002 2004 2006
Year ISSCC paper
MLC (Multi
(Multi-level
level cell) NAND flash
SLC (Single-level cell) NAND flash
K. Takeuchi, ISSCC 2006,pp.144-145.

NAND Program Speed Trend
12
ISSCC paper
MLC (Multi-level cell) NAND flash
SLC (Single-level cell) NAND flash
c]
10
m speed [MB/sec
FTTH
5M-pixel 5photos/sec
8 HDTV 60fps
6
Program
4M pixel 3photos/sec
4M-pixel
4
2
P
Motion JPEG VGA 30fps

MPEG2 VGA 30fps
0
1994 1996 1998 2000 2002 2004 2006
Year
MLC performance is comparable with SLC

SLC.

Chip Architecture
56nm 8Gbit NAND Flash Memory

Memory Core Circuit
Page buffer
Even & Odd bit-lines share one page
buffer and are alternatively selected.
Contain two latches to store two bit
data for MLC operation.

NAND Operation Principle
Read
Number of memory cells
Bit-line (0.8VÆ0V) “0” “1”
Vread (4.5V)
Selected word-line Vth
((Read voltage
g : 0V))
Read voltage
Bit-line voltage
Vread (4.5V)
“1”
“0”
Vread ((4.5V)) Time
0V
9 After precharging, bit-lines are discharged through the memory cell.

9 Unselected cells are biased to the pass voltage, Vread.
9 Small cell read current (~1uA) Æ Slow random access (~50us)
9 Serial access : 30-50ns Æ Fast read = 20-30MB/sec
NAND Operation Principle (Cont’)
Program : Electron injection
18V
0V 0V
9 Channel-FN tunneling
9 High reliability
0V
9 Low
L currentt consumption
ti
Erase : Electron ejection (~pA/cell)
0V 9 Page based parallel program
20V 20V
Typical page size : 2-4kB
20V
S. Aritome, IEDM 1990, pp.111-114.

NAND Operation Principle (Cont’)
P
Page based
b d parallel
ll l programming
i
Bit-line
Row dec
Page Page : 2-4KBytes
coder ・・・
P
Page b ff
buffer
Page buffer
Memory cell array T.Tanaka, Symp. on VLSI
Circuits 1990, pp.105-106.
All memory cells in a page are
programmed at the same time.
Program speed = Page size / Programming time

= 8KByte / 800us
= 10MByte/sec (56nm MLC) K. Takeuchi, ISSCC 2006,pp.144-145.

Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

SSD Overview
SSD Market Projection

SSD C
Costt T
Trendd
SSD Reliability
SSD Performance
SSD Power Consumption

SSD Market Projection
PC expected as the next killer application of NAND.
Gartner Dataquest
I. Cohen, Flash Memory Summit 2007.

Cost Trend of NAND and HDD
Anal st e
Analyst expectation
pectation
O Balaban,
O. B l b Fl hM
Flash Memory S
Summitit 2007
2007.
NAND will replace HDD in PC in 2009-2012 if the cost

continues decreasing.
Unclear scaling scenario e.g. double exposure vs. EUV,
floating gate vs. MONOS, and 2D vs. 3D cell.
SSD Reliability
SSD is robust.
No mechanical parts.
But need to be careful in PC application
Portable consumer electronics application
pp
(Digital still cameras, MP3 players, Camcorders)
Effective data retention time << 10years
Data quickly transferred to PC or DVD
th
through h USB d i and
drive d memory cards.
d
Most probably data backup in PC
PC application
Higher reliability required w.o. backup
Need longer data retention time : 5-10 years
SSD Reliability (Cont’)
Failure mechanism of NAND
Program disturb
During programming, electrons are injected to
unselected memory y cells.
Read disturb
During read,
read electrons are injected to unselected
memory cells.
W it /E
Write/Erase d
endurance D t retention
& Data t ti
As the Write/Erase cycles increase, damage of
the tunnel oxide causes a leakage of stored
charge.

“Classic” program disturb
Program inhibit Program
Bi li (Vcc)
Bitline (V ) Bitline
i i (0V)
(0 )
Vcc
Vpgm
(18V)
Vpass
(10V)
Vpass disturb cell
Vpgm disturb cell 10V
18V
V
Vpass
(10V) D S
0V
D S 0V
～8V
V
Vcc
Both selected and unselected cells suffer from the disturb.

K. D. Suh, ISSCC 1995, pp.128-129.

“Modern” program disturb
J. D. Lee, NVSMW 2006, pp. 31-33.

K T Park SSDM 2006,
K.T.Park, 2006 pp.298-299.
pp 298 299
Hot carriers g
generated at the select gate
g edge
g inject
j
into the memory cell causing a Vth shift.
The Vth shift can be reduced byy increasingg SG-WL
space.
“Modern” program disturb (Cont’)
S l t Tr.
Select T Dummy
D T WL0
Tr.
The Vth shift can be reduced by adding dummy WL.
K.T.Park, SSDM 2006, pp.298-299.

Read disturb
Bitline (0.8VÆ0V)
Vread (4.5V)
4.5V
5
Selected word-line
(0V)
D 0V S
Vread (4.5V)
Weak program bias condition

Vread (4.5V)
Unselected word-lines suffer
0V
from the read disturb.

Program disturb and read disturb summary
Program disturb and read Page assignment of MLC
disturb is a “bit error” not a
“burst
burst error
error”. X1
X1
Two bits in MLC are assigned to X2
different pages. X2
Even if one MLC cell fails, one bit in
two pages fails. 2-level cell 4-level cell
K Takeuchi,
K. Takeuchi Symp.
Symp on VLSI Circuits
ECC(Error correcting code) 1997, pp. 67-68.
effectively corrects the bit error.

Existing ECC corrects 4
4-8bit
8bit errors per
512Byte sector.

Write/Erase Endurance & Data Retention
Endurance
E d : how
h many times
ti data
d t are written
itt
Data retention : how long the data remains valid
Clear correlation between endurance and data
retention
Damages to the tunnel oxide during write and
erase cause the data retention problems.
Traps are generated during write and erase.
The unlucky cell with traps results in a leakage
path, causing the charge transfer.
The leakage current is called SILC (Stress
Induced
I d d Leakage
L k Current).
C t)
To guarantee data retention, Write/Erase cycles
K. Prall, NVSMW 2007, pp. 5-10.
are limited to 100K (SLC) or 10K (MLC).

100K (SLC) or 10K(MLC) W/E cycles acceptable?
W/E cycles estimation
32GB SSD
Usage
g scenario : 2~5GB/day y (#)
Service for 5years
100% efficient wear levelingg
(365 days/year) x 5years / (32GB / 2~5GB/day)
= 114~285 W/E cycles
y
114~285 cycles are far below the NAND limitation
of 100K for SLC or 10K for MLC.
Actual W/E cycles are higher for the file
management such as garbage collection.
(#) W.Akin, IDF 2007_4, MEMS003.
Y.Kim, Flash Memory Summit 2007.

SSD Performance
Random access
[Data transfer size in PC application]
OS changes such as
directory entry and file
system metadata
Application S/W change
50% of data is < 4KB.
R d
Random access mainly
i l
decides the performance
of PC. K Grimsrud IDF2006
K.Grimsrud, IDF2006, MEMS004
MEMS004.
Sequential
q access
Boot
Hibernation

SSD Performance (Cont’)
Random access
Read Write Erase

NAND (SLC) 25us 300us 1ms
NAND (MLC) 50us 800us 1ms
HDD 3ms 3ms N.A.
Erase are hidden by operating the erase during the idle period.
Read : SSD with SLC and MLD has a great advantage over HDD.
Write : SSD still has a performance advantage. But the write
performance can be an issue in the future if the NAND
performance degrades by scaling the memory cell or increasing
the number of bits pper cell.

S
Sequential
ti l access
NAND : Single chip operation NAND : 4 chip interleaving
R d
Read W it
Write R d
Read W it
Write
NAND (SLC) 25MB/sec 20MB/sec 100MB/sec 80MB/sec
NAND (MLC)
NAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/sec
HDD 80MB/sec 80MB/sec ‐ ‐
[Block diagram of SSD w
w. interleaving function]
SSD (SLC) : Comparable read and

write performance with HDD
HDD.
SSD (MLC) : Comparable read
performance. By
p y introducingg 8chip
p
interleaving, the write performance
can be comparable with HDD.
C. Park, NVSMW 2006, pp.17-20.

Actual performance results
[PC-mark05]
[Bootvis]
[Sandra]
SSD (SLC) has superior performance over HDD.

Ken Takeuchi 33
SSD Power Consumption
Power consumption
NAND : Single chip operation NAND : 4 chip interleaving
Read Write Read Write
NAND (SLC) 20mA 20mA 80mA 80mA
NAND (MLC) 20mA 20mA 80mA 80mA
HDD >300mA >300mA ‐ ‐
In SSD, additional current (~100mA) are consumed in the

NAND controller, RAM and IO.
A t l Power
Actual P C ti
Consumption

In all modes
modes, the power consumption of SSD is smaller
than HDD.
Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

NAND Circuit Design
Random Access
High Speed Programming
High Speed Read
Sequential Access
High Speed Programming
Hi h Speed
High S d Read
R d

Random Access : High Speed Programming
Bit-by-bit Program Verify

f SScheme
Program pulse
Program Algorithm 18V
0V 0V
Data load
Program pulse 0V
FN tunneling
Bit-line
No Verify‐read
Page
All cells
programmed ?
・・・
Yes
End
Page
g buffer
During the verify-read, the program data in the page buffer

is
s updated so tthat
at tthe
epprogram pulse
og a pu se is applied
s app ed O ONLY to
insufficiently programmed cells. T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.

Random Access : High Speed Programming (Cont’)
Incremental Program Voltage Scheme
Word-line waveform
Program
g pulse
p Program voltage, Vpgm
increases by ⊿Vpgm.
⊿
⊿Vpgm
Verify read Constant electric field

across the tunnel oxide.
Tpulse Tvfy
Constant tunnel current.
1 cycle
# off program pulses:
l N
Npulse
l cycles
l
Vth shift is constant at ⊿Vpgm.
Programming time, Tprog = (Tpulse+Tvfy)×Npulse
Program
g characteristics
Vth
Npulse = ⊿Vth0/⊿Vpgm
Fastest cell
Achieve both fast Verify Slowest cell
g
voltage ⊿Vth0
programming
i and
d Npulse
(Time)
precise Vth control.
(⊿Vth0/⊿Vpgm) cycles
G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.

K. D. Suh, ISSCC 1995, pp.128-129.

Problems off MLC

C programming
“0” “1” “2” “3”
Vth
Y1 Y2 Y1 Y2
MLC SLC 2‐level cell 4‐level cell
“1”-program “1”-program
& ”1”verify & ”1”verify Two bits in a cell are assigned
to two column addresses.
“2”-program 3 operations (“1”-, “2”- and
& ”2”verify
“3”-program) required.
Long programming.
“3”-program
& ”3”verify

Solution : Multi-page Cell Architecture
1st page program

X1
X1
“0” “1”
X2
X2
Vth
1st page data : “1” “0”
2-level cell 4-level cell
2nd page program

Two bits in a cell are
“0” “1” “2” “3” assigned
i d to
t two
t row
addresses.
Vth
1stt page data
d : “1” “0” “0” “1”
In average, 1.5 operations.
2nd page data : “1” “0” Twice faster than
conventional scheme.
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

Program Voltage Optimization

O
WL0, 31 : Higher capacitive coupling with word-lines.

Initial program voltage is set lower.
Optimized program voltage accelerates the programming.
T. Hara, ISSCC 2005, pp. 44-45.

Problems : FG-FG
G G interference
f
FG FG coupling
FG-FG li hift the
shifts th Vth off a memory cell ll as the
th
neighboring cell are programmed.
To tighten the Vth distribution, ⊿Vpgm is decreased,
causing a slow programming.
The Vth modulation becomes significant as the memory
cell is scaled down. J.D. Lee, EDL 2002, pp. 264-266.
M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90.

S
Solution : FG-FG
G G Coupling
C C
Compensation
[3-step programming] [Programming order]
Step 1
Step2
Step3
p
Step 1. The memory cell is ROUGHLY programmed.

Cells are programmed BELOW the target Vth.
Step 2. Neighboring cells are programmed.
Step 3
3. The memory cell is PRECISELY programmed.
programmed
FG-FG coupling is suppressed by 90%.

Large ⊿Vpgm enables a fast programming.
N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.

Random Access : High Speed Read
Problems off MLC
C read
“0” “1” “2” “3”
Vth
Y1 Y2 Y1 Y2
① ② ③
MLC SLC Two bits in a cell are assigned

“1” read
“1”-read “1” read
“1”-read t ttwo column
to l addresses.
dd
3 operations (“1”-, “2”- and
“2”-read “3”-read)
3 read) required.
Long random read.
“3”-read

Random Access : High Speed Read (Cont’)
S
Solution : Multi-page Cell
C Architecture
“0” “1” “2” “3”
X1
X1
X2
Vth X2
1st page data : “1” “0” “0” “1”
2nd page data
d t : “1” “0”
Two bits in a cell are
② ① ③
assigned
g to two row
1st page read : ②, ③ Æ EXOR addresses.
In average, 1.5 operations.
2nd page read : ①
Twice faster than
conventional scheme.
K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

S. Lee, ISSCC 2004, pp.52-53.

Sequential Access : High Speed Programming
Parallel Operation
Increase page size
Multi-page operation
Multi-chip operation (Interleaving)
T be
To b discussed
di d in
i “NAND C
Controller
t ll Circuit
Ci it Design”
D i ” section
ti
Pipeline Operation
Write/Read Cache
Cache Page Copy

Parallel Operation : Increase Page Size
Page size trend
By increasing the word-line length, the page size has been
extended
t d d to
t increase
i the
th write
it andd readd throughput.
th h t
4500
Bit-line
4000
3500
Page
Page size (Byte)
3000
2500 ・・・
2000
1500 Page buffer
1000
500
0
0.25um 0.16um 0.13um 90nm 70nm 50nm
Design rule
But, the large page size also causes problems.
Noise issue due to the large RC delay of a word-line

Parallel Operation : Increase Page Size (Cont’)
Problems : SG-WL
SG noise
[Conventional read/verify-read]
Bit-line
SG-WL
SG WL capacitive
SGD coupling
Selected 1.5V
WL31
WL bounce
WL0
SGS Read failure
Bit-line Bit-line
precharge
h di h
discharge

S l ti
Solution : Raise
R i neighboring
i hb i SG BEFORE bit-line
bit li discharge
di h

Problems : WL-WL noise

Solution

Parallel Operation : Multi-page Operation
Multi-page operation
Operate multi-page simultaneously to increase the write/read
throughput.
th h t
[Multi page operation]

[Multi-page 0 25um 256Mb NAND
0.25um
K. Imamiya, ISSCC 1999, pp.112-113.

Pipeline Operation : Write/Read Cache
Pipelining off data-in/out
/ & cell read/write
/
Implement data cache in NAND
Input
I t /output
/ t t data
d t to
t the
th data
d t cache
h during
d i cell
ll read/program
d/
[Write Cache Example : 0.13um 1Gbit NAND]
Data Cache H. Nakamura, ISSCC 2002, pp.106-107.

Pipeline Operation : Cache Page Copy
S
System performance
f degradation off a large block
[Frequent block copy]
70nm 8G MLC 56nm 8G MLC
(ISSCC2005) (This work)
(ISSCC2006)
Old block
32WLs 32WLs
① Cell read
New block
③ Cell program
4KB page (max) 8KB page (max)
512KB block 1MB block Page buffer
② Data-out,
ECC, Data-in NAND
System performance controller
degradation
Block copy time
= (T_Cell read+T_Data_out+TECC+T_Cell program)
Fast block copy required ×(# of pages per block)
= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.

Pipeline Operation : Cache Page Copy (Cont’)
Solution : Fast block copy
Step1 Step2 Step3 Step4
Old block Old block Old block Old block

Page i
Page i+1
Cell Read Cell read

New block New block New block New block
Cell program
Page buffer Page buffer Page buffer

Page buffer
Data-out Data-out
NAND ECC NAND NAND ECC NAND
controller controller
ll controller controller
Step
p 4 : Pipelining
p g of programming
p g g Page
g i
and data out / ECC of Page i+1.
Fast block copy


Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

HW Architecture
SW Architecture
High speed technology
Interleaving
High reliability technology
Wear Leveling
Bad Block Management
ECC
SLC/MLC Combo
HW Architecture
Block diagram (Single channel)
HDD-like architecture : DRAM buffer to hide NAND random access

High power consumption
Hi h costt
High

HW Architecture (Cont’)
Block diagram (Multi-channel)
DRAM eliminated :
Random access of NAND
is faster than HDD.
Low p p
power consumption
Low cost
Multi-channel
Parallel operation
High bandwidth

SW Architecture
H t and
Host d SSD SW structure
t t
Host I/F : SATA, PATA, PCIe,
USB LBA
USB, LBA, BA
BA, SD
SD, MMC
MMC…
NAND I/F : Low level driver to
access NAND through NAND
controller.
FTL ((Flash
as Translation
a s at o Layer)
aye )
Main part of SSD.
Address translation from
logical address to physical
address of NAND.
File management such as bad
block management and wear
l
leveling.
li

High Speed Technology
Interleaving : Sequential
S Parallel Write
2-channel 4-way interleaving

Max write throughput : 80MB/sec for MLC.
di
HW driven t ti operation.
automatic ti

High Reliability Technology (Cont’)
Wear-leveling
Problem
W it /E
Write/Erase cycle
l off NAND iis li
limited
it d tto 100K ffor SLC and d 10K
for MLC.
Solution
Write data to be evenly distributed over the entire storage.
Count # of Write/Erase cycles of each NAND block.
Based on the Write/Erase count, NAND controller re-map
the logical address to the different physical address.
W l li is
Wear-leveling i done
d b the
by th NAND controller t ll (FTL)
(FTL), nott by
b
the host system. Block : Erase unit
Bitline
Bitline
Bitline

Example of wear-leveling
If the block is occupied with old data, data is programmed
to a new block.
If there is no free block, the invalid block are erased.
Block 1 Block 1
Block 2 Block 2
Bl k 3
Block Bl k 3
Block
Old file Block 4 Block 4 Block 4 Æ Invalid
Block 5 Block 5
Block 6 Block 6
Block 7 Rewrite Block 7
Block 8 Block 8
Block 9 old file
Block 9
Empty block New File Write new file to

an empty block

Static data
Data that does not change such as system data
(OS, application SW).
D
Dynamic i data
d t
Data that are rewritten often such as user data.
Dynamic wear-leveling
Wear-level only over empty and dynamic data.
g
Static wear-leveling
Wear-level over all data including static data.

Dynamic wear-leveling
Red : Static data such as system data.
Write/Erase count Blue : Dynamic data such as user data
Physical block address
Block with static data is NOT used for wear-leveling.

wear leveling.
Write and erase concentrate on the dynamic data block.
N.Balan, MEMCON2007.
SiliconSystems, SSWP02.

Static wear-leveling
Write/Erase count Red : Static data such as system data.
Blue : Dynamic data such as user data
Physical block address

Wear-level more effectively than dynamic wear-leveling.
Search for the least used physical block and write the data to
the
th location.
l ti If that
th t location
l ti
Is empty, the write occurs normally.
Contains static data, the static data moves to a heavily
N.Balan, MEMCON2007.
used block and then the new data is written. SiliconSystems, SSWP02.
Bad Block Management
Program/Erase characteristics vs. endurance
As
A the
h W Write/Erase
i /E cycles
l increases,
i erase failure
f il occurs,
resulting in a bad block.
The NAND controller detects and isolates the bad block
block.
Y.R. Kim, Flash Memory Summit 2007.

ECC (Error Correcting Code)
To overcome read disturb,
program disturb and data
retention failure,, ECC have to
be applied.
Since failure pattern is
random, BCH is sufficient.
Existing NAND controller
can correct 4-8bit error per
512Byte sector.
NAND with embedded ECC is
also published. R. Micheloni, ISSCC2006, pp.142-143.

MLC/SLC Combo
Future Direction : Hybrid SSD with SLC and MLC
Concept : Right device for the right use.
Enjoy the Benefit of both SLC and MLC.
SLC : Fast and highly reliable but low capacity.
Use SLC as a cache or system data storage
storage.
MLC : Large capacity but slow. Use MLC as user data storage.
Toshiba LBA-NAND
Samsung Combo SSD J. Elliott, WinHEC2007. http://www1.toshiba.com/taec/index.jsp
http://www1 toshiba com/taec/index jsp
SATA-III
MLC SATA-II 48/64/128/256/512GB
32/48/64/128/256GB
(Multi Level Cell) SATA-II
16/32/48/64/96/128GB SATA-III
56/112/224/336/448GB
SATA-II
28/56/112/168/224GB
SATA-III
SATA-II 32/64/128/192/256GB
14/28/56/84/112GB Spansion MirroBit Eclipse
Combo SATA-II http://www.spansion.com/products/MirrorBit_Eclipse.html
16/32/64/96/128GB
(SLC+MLC)
SATA-I SATA-II
8/16/32/48/64GB
PATA
8/16/32/48/64GB
SLC
4/8/16/32GB (Single Level Cell)
R/W Speed: 57/32 64/45 100/80 160/160 800/800 1300/1300
2006 2007 2008 2009 2010

Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

Performance Optimization
Sector Size Optimization
Reliability Optimization
EWF (Enhanced
(E h d Write
W it Filter)
Filt )
SMART (Self-Monitoring, Analysis and
Reporting Technology)

Future Perspective
Motivation
Existing OS is optimized for magnetic drives.

Current SSD based PC uses the conventional
OS and jjust replace
p HDD with SSD.
To achieve the best performance and
SSD OS especially file system
reliability of SSD,
should be optimized.

Performance Optimization
Sector size optimization
Minimum write/read unit of NAND is a page.
Typical page size is 4-8KByte.
A page is written only ONCE to avoid the
Page
program disturbance
disturbance.
With current OS having 512Byte sector , one
sector write wastes >80% of data in a page.
p g
・・・
1 sector Remaining
g portion
p
write becomes garbage.
LBD(Long Block Data) sector standard :
4KByte sector size fits better with SSD
SSD.
Considering the page size increases as NAND
is shrinking,
g larger
g sector size such as
16KByte or 32KByte is preferred.
Reliability Optimization
Enhanced Write Filter (Windows Embedded)
Control the file allocation to store frequently rewritten file in

DRAM and not to access NAND.
D
Decrease write/erase
it / cycles
l off NAND,
NAND extending
t di the
th NAND
lifetime.
Enhanced Write Filter (EWF) is located between file system
and low level driver interfacing with SSD.
Enhance
Application Write Filter
SSD
File System Low-level Driver
http://msdn2.microsoft.com/en-us/library/ms912909.aspx

Reliability Optimization (Cont’)
SMART
(Self-Monitoring, Analysis and Reporting Technology)
Monitor the storage and report/predict the failure.

SMART for HDD is NOT smart because it is very difficult to
predict the mechanical failure.
(Google report,
report http://209.85.163.132/papers/disk_failures.pdf)
http://209 85 163 132/papers/disk failures pdf)
SMART for SSD can be really smart.

Product lifetime can be predicted because the failure rate is
highly correlated with the write/erase cycles.
Predict
P di t the
th SSD lifetime
lif ti by
b monitoring
it i the
th write/erase
it /
cycles and replace SSD before the fatal failure occurs.
http://www.tdk.co.jp/tefe02/ew_007.pdf

Outline
NAND Overview
SSD Overview
NAND CCircuit
cu t Design
es g
Summary

Summary
Market & Cost : NAND will replace HDD in PC in 2009-2012.
Key issue : Is scaling sustainable?

Unclear scaling scenario e.g. double exposure vs. EUV,
floating gate vs
vs. MONOS
MONOS, and 2D vs
vs. 3D cell
cell.
MLC is a MUST for the cost reduction.

Existing 2bit/cell satisfies performance, reliability and power
consumption requirements.
>2bit/cell or scaled MLC may face performance/reliability

challenges.
challenges
Key breakthrough of NAND circuit or NAND controller circuit
such as SLC/MLC Combo required.
Optimization of OS will also help.

Th k you!!
Thank
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
p y jp
http://www.lsi.t.u-tokyo.ac.jp

References
• F Masuoka,
F. Masuoka M. M Momodomi,
Momodomi Y Y. Iwata and RR. Shirota
Shirota, "New ultra high density EPROM and flash EEPROM with NAND
structured cell," in IEDM Tech. Dig., 1987, pp.552-555.
• K. Imamiya, Y. Sugiura, H. Nakamura, T. Himeno, K. Takeuchi, T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K.
Shimizu, K. Hatakeyama and K. Sakui “ A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology”, ISSCC
Digest of Technical Papers , 1999, pp.112-113.
• K. Takeuchi, Y. Kameda, S. Fujimura, H. Otake, K. Hosono, H. Shiga, Y. Watanabe, T. Futatsuyama, Y. Shindo, M. Kojima, M.
Iwai, M. Shirakawa, M. Ichige, K. Hatakeyama, S. Tanaka, T. Kamei, J.Y. Fu, A. Cernea, Y. Li, M. Higashitani, G. Hemink, S.
Sato, K. Oowada, S.C. Lee, N. Hayashida, J. Wan, J. Lutze, S. Tsao, M. Mofidi, K. Sakurai, N. Tokiwa, H. Waki, Y. Nozawa,
K. Kanazawa and S. Ohshima, “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10Mbyte/sec Program
Throughput,” in International Solid-State
Throughput, Solid State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2006, pp.144
pp.144-
145.
• S. Aritome, R. Shirota, R. Kirisawa, T. Endoh, R. Nakayama, K. Sakui, and F. Masuoka, “A reliable bi-polarity write/erase
technology in flash EEPROMs,” in IEDM Tech. Dig., 1990, pp.111-114.
• T. Tanaka, M. Momodomi, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi and F. Masuoka, “A 4-Mbit NAND-
EEPROM with Tight Programmed Vt Distribution,
Distribution ” in Symp.
Symp VLSI Circuits Dig
Dig. Tech
Tech. Papers
Papers, June 1990
1990, pp
pp.105-106.
105 106
• J. Elliott, “SSD:The Next Wave In NAND Flash”WinHEC 2007,” WinHEC, 2007, SS-S499b_WH07.
• I. Cohen, “Is There a Killer Application for Flash Memory,” Flash Memory Summit, 2007.
• O. Balaban, “Bringing Solid State Drives to Mainstream Notebooks,” Flash Memory Summit, 2007.
• Kang-Deog Suh, Byung-Hoon Suh, Young-Ho Um, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, Suk-Chon
Kwon, Byung-Soon Choi, Jin-Sun Yum, Jung-Hyuk Choi, Jang-Rae Kim and Hyung-Kyu Lim, “A 3.3 V 32 Mb NAND flash
memory with incremental step pulse programming scheme”, in ISSCC Digest of Technical Papers, Feb., 1995, pp.128-129.
• Jae-Duk Lee, Chi-Kyung Lee, Myung-Won Lee, Han-Soo Kim, Kyu-Charn Park and Won-Seong Lee,”A New Programming
Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current,” in Non-
volatile Semiconductor Memoryy Workshop p ((NVSMW)) Dig.g Tech. Papers,
p , 2006,, pp
pp. 31-33.
• K. T. Park, S. C. Lee, J. Sel, J. Choi and K. Kim, “Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm
NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell,” in International Conference on Solid State
Devices and Materials (SSDM) Dig. Tech. Papers, 2006, pp.298-299.
• K. Takeuchi, T. Tanaka and T. Tazawa, “A multi-page cell architecture for high-speed programming multi-level NAND flash
memories ” in Symp.
memories, Symp VLSI Circuits Dig
Dig. Tech
Tech. Papers
Papers, June 1997
1997, pp
pp.67-68.
67 68
• K. Prall , “Scaling Non-Volatile Memory Below 30nm,” in Non-volatile Semiconductor Memory Workshop (NVSMW) Dig. Tech.
Papers, 2007, pp. 5-10.

References (Cont’)
• W. Akin, ”SSDs for IA Segments,” Intel Developer Forum (IDF), 2007, April, MEMS003.
• Y. Kim, Flash Memory Summit 2007, “Solid State Drives Moving into Design,” Flash Memory Summit, 2007.
• K. Grimsrud and R. Coulson, “Platform NV Memory Solutions for Storage Enhancement,” ,” Intel Developer Forum (IDF),
2006, MEMS004.
• Chanik Park,
Park Prakash Talawar
Talawar, Daesik Won
Won, MyungJin Jung
Jung, JungBeen Im Im, Suksan Kim and Youngjoon Choi
Choi, “A A High
Performance Controller for NAND Flash-based Solid State Disk (NSSD),” in Non-volatile Semiconductor Memory Workshop
(NVSMW) Dig. Tech. Papers, 2006, pp.17-20.
• T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodaira, S. Aritome, R. Shirota and F. Masuoka, "A quick intelligent program
architecture for 3V-only NAND EEPROMs," Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp.20-21.
• GJH i k T
G.J.Hemink, T.Tanaka,
T k T.Endoh,
T E d h S.Aritome
S A it anddR R.Shirota,
Shi t “F “Fastt and
d accurate
t programming
i method
th d ffor multi-level
lti l l NAND
flash EEPROM’s”, in Symp. VLSI Technology Dig. Tech. Papers, June 1995, pp.129-130.
• T.Hara, K.Fukuda, K.Kanazawa, N.Shibata, K.Hosono, H.Maejima, M.Nakagawa, T.Abe, M.Kojima, M.Fujiu, Y.Takeuchi,
K.Amemiya, M.Morooka, T.Kamai, H.Nasu, K.Kawano, C.M.Wang, K.Sakurai, N.Tokiwa, H.Waki, T.Maruyama, S.Yoshikawa,
M.Higashitani, T.D.Pham and T.Watanabe, “A 146mm2 8Gb NAND flash memory with 70nm COMS technology”, in ISSCC
Digest of Technical Papers, 2005, pp.44-45.
• Jae-Duk Lee, Sung-Hoi Hur and Jung-Dal Choi, “Effects of Floating-Gate Interference on NAND Flash Memory Cell
Operation,” Electron Device Letters, vol. 23, no. 5, 2002, pp. 264-266.
• M. Ichige, Y. Takeuchi, K. Sugimae, A. Sato, M. Matsui, T. Kamigaichi, H. Kutsukake, Y. Ishibashi, M. Saito, S. Mori, H.
Meguro S
Meguro, S. Miyazaki
Miyazaki, T
T. Miwa
Miwa, S
S. Takahashi
Takahashi, TT. Iguchi
Iguchi, N.
N Kawai,
Kawai S.S Tamon,
Tamon N.N Arai,
Arai HH. Kamata
Kamata, T
T. Minami
Minami, H
H. Iizuka
Iizuka, M
M.
Higashitani, T. Pham, G. Hemink, M. Momodomi and R. Shirota, “A novel self-aligned shallow trench isolation cell for 90nm
4Gbit NAND Flash EEPROMs,” in Symp. on VLSI Technologies Dig. Tech. Papers, 2003, pp.89-90.
• Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu,
Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue,
Toshiyuki Takahashi,
Takahashi Toshifumi Shano
Shano, Yukio Komatsu
Komatsu, Katsushi Nagaba
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References (Cont’)
• H. Nakamura, K. Imamiya, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K.
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• http://www.tdk.co.jp/tefe02/ew_007.pdf

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ISSCC 2008 Tutorial T7

NAND successful as a media for SSD

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 1

SSD : Solid State Drive

J. Elliott, WinHEC 2007, SS-S499b_WH07.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 2

Need to understand of the device especially about

Require co-design off NAND and NAND controllers

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 3

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 4

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 5

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 6

Memory cells are sandwiched by select gates.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 7

SGD SGD SGS SGS

Simple structure : High scalability,

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 8

Number of memory cells Number of memory cells

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 9

55% growth / year

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 10

Motion JPEG VGA 30fps

MLC performance is comparable with SLC

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 11

K. Takeuchi, ISSCC 2006,pp.144-145.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 12

K. Takeuchi, ISSCC 2006,pp.144-145.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 13

9 After precharging, bit-lines are discharged through the memory cell.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 15

Program speed = Page size / Programming time

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 16

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 17

SSD Market Projection

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 18

I. Cohen, Flash Memory Summit 2007.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 19

NAND will replace HDD in PC in 2009-2012 if the cost

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 22

Both selected and unselected cells suffer from the disturb.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 23

J. D. Lee, NVSMW 2006, pp. 31-33.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 25

Weak program bias condition

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 26

effectively corrects the bit error.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 27

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 28

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 29

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 30

Read Write Erase

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 31

SSD (SLC) : Comparable read and

C. Park, NVSMW 2006, pp.17-20.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 32

SSD (SLC) has superior performance over HDD.

In SSD, additional current (~100mA) are consumed in the

C. Park, NVSMW 2006, pp.17-20.

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 35

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 36

Bit-by-bit Program Verify

During the verify-read, the program data in the page buffer

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 37