CHAPTER 1

INTRODUCTION

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 The aim of this project is to provide the security. Now a day’s security system is must for
every organization. Access control system is one system that is used for security purpose in many
organizations. The main aim of this project is to provide access only if the password of particular
user is matched. So, every user is given a unique password. So, that access is denied to
unauthorized persons.
This system can be used in military areas, bank security and security for important
documents.
Our system has intelligent of allowing only valid passwords. This is 89C52
microcontroller based project which is interfaced to keypad, LCD- display and Stepper motor. We
used a 4x3 matrix keypad to have an access to system. An LCD (16X2) and a stepper motor to
open or close the door. We have used KEIL for microcontroller programming. The software
prompts user to enter a password and checks its validity .If it’s valid the door is opened using
Stepper motor.

• HARDWARE COMPONENTS:

89C52 MICROCONTROLLER
1.

2. ULN 2003 DRIVER IC

3. STEPPER MOTOR.

4. LCD DISPLAY.

5. KEY PAD.

• SIMULATION:

TOOL : KEIL MICROVISION

PLATFORM : WINDOWS
LANGUAGE : EMBEDDED ‘C’

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 BLOCK DIAGRAM

LCD
ULN STEPPER
DRIVER MOTOR
AT 89C52
DISPLAY

MICRO
CONTROLLER

4x3
MATRIX

KEYPAD

Figure 1.1: Block Diagram

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 CHAPTER 2
MICROCONTROLLER

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2.1 A BRIEF HISTORY OF 8051
In 1981, Intel Corporation introduced an 8 bit microcontroller called 8051. This
microcontroller had 128 bytes of RAM, 4K bytes of chip ROM, two timers, one serial port,
and four ports all on a single chip. At the time it was also referred as “A SYSTEM ON A
CHIP”.

The 8051 is an 8-bit processor meaning that the CPU can work only on 8 bits data at a
time. Data larger than 8 bits has to be broken into 8 bits pieces to be processed by the CPU.
The 8051 has a total of four I\O ports each 8 bit wide.

There are many versions of 8051 with different speeds and amount of on-chip ROM
and they are all compatible with the original 8051. This means that if you write a program for
one it will run on any of them.

The 8051 is an original member of the 8051 family. There are two other members in
the 8051 family of microcontrollers. They are 8052 and 8031. All the three microcontrollers
will have the same internal architecture, but they differ in the following aspects.
 8031 has 128 bytes of RAM, two timers and 6 interrupts.
 89S51 has 4KB ROM, 128 bytes of RAM, two timers and 6 interrupts.
 89S52 has 8KB ROM, 128 bytes of RAM, three timers and 8 interrupts.

Of the three microcontrollers, 89C51 is the most preferable. Microcontroller supports

both serial and parallel communication.

In the concerned project 89C52 microcontroller is used. Here microcontroller used is

AT89C52, which is manufactured by ATMEL laboratories.

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2.2 DESCRIPTION OF 89C52 MICROCONTROLLER
The AT89C52 provides the following standard features: 8Kbytes of Flash, 256 bytes
of RAM, 32 I/O lines, three 16-bit timer/counters, six-vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is
designed with static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power down
Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions
until the next hardware reset.

By combining a versatile 8-bit CPU with Flash on a monolithic chip, the AT89C52 is
a powerful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.

Features of Microcontroller (89C52)

• Compatible with MCS-51 Products

• 8 Kbytes of In-System Reprogrammable Flash Memory
• Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 256 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-Bit Timer/Counters
• Eight vector two level Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes

In addition, the AT89C52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes.

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 The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port
and interrupt system to continue functioning. The Power down Mode saves the RAM
contents but freezes the oscillator disabling all other chip functions until the next hardware
reset.

2.3 BLOCK DIAGRAM OF MICROCONTROLLER

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 Figure 2.1: Block Diagram of Micro Controller
2.4 PIN CONFIGURATIONS

Figure 2.2: Pin Configuration

Pin Description

• Vcc
Pin 40 provides Supply voltage to the chip. The voltage source is +5v.

• GND.
Pin 20 is the ground.

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 • Port 0
Port 0 is an 8-bit open drain bidirectional I/O port from pin 32 to 39. As an output
port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high-impedance inputs. Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external program and data memory. In this mode P0
has internal pull-ups.
Port 0 also receives the code bytes during Flash programming, and outputs the code
bytes during program verification. External pull-ups are required during program verification.

• Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups from pin 1 to 8. The Port
1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in
following table.
Port 1 also receives the low-order address bytes during Flash programming and
program verification.

• Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups from pin 21 to 28. The
Port 2 output buffers can sink / source four TTL inputs. When 1s are written to Port 2 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins
that are externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that uses 16-bit addresses (MOVX @

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DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses
to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of
the P2 Special Function Register. Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

• Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups from pin 10 to 17. The
Port 3 output buffers can sink / source four TTL inputs. When 1s are written to Port 3
pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source current (IIL) because of the
pull-ups.
Port 3 also serves the functions of various special features of the AT89C52 as listed
below:

Figure 2.3: Special Features of Port 3

Port 3 also receives some control signals for Flash programming and programming
verification.

• RST
Pin 9 is the Reset input. It is active high. Upon applying a high pulse to this pin, the
microcontroller will reset and terminate all activities. A high on this pin for two machine
cycles while the oscillator is running resets the device.

• ALE/PROG

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 Address Latch is an output pin and is active high. Address Latch Enable output pulse
for latching the low byte of the address during accesses to external memory. This pin is
also the program pulse input (PROG) during Flash programming. In normal operation
ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for
external timing or clocking purposes.
• PSEN
Program Store Enable is the read strobe to external program memory. When the
AT89S52 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to external
data memory.

• EA/VPP
External Access Enable EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH. Note,
however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should
be strapped to VCC for internal program executions. This pin also receives the 12-volt
programming enable voltage (VPP) during Flash programming when 12-volt programming is
selected.

• XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

• XTAL2
Output from the Inverting oscillator amplifier.

• Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an on chip oscillator, as shown in Figure 2.a. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.b.

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 Figure 2.4 Crystal Connections Figure 2.5 External Clock Drive
Configuration

There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.

• Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain
active. The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be terminated by
any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated
by a hardware reset, the device normally resumes program execution, from where it left off,
up to two machine cycles before the internal reset algorithm takes control.

• Power down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes
power down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the power down mode is terminated. The only exit from
power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is restored to its normal operating level
and must be held active long enough to allow the oscillator to restart and stabilize.

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 Figure 2.6 Status Of External Pins During Idle and Power Down Mode

• Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed (U) or can be
programmed (P) to obtain the additional features listed in the table 2.3. When lock bit 1 is
programmed, the logic level at the EA pin is sampled and latched during reset. If the device is
powered up without a reset, the latch initializes to a random value, and holds that value until
reset is activated. It is necessary that the latched value of EA be in agreement with the current
logic level at that pin in order for the device to function properly.

Figure 2.7 Lock Bit Protection Modes

2.5 TIMERS

• Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in
the AT89S51.
Register pairs (TH0, TL1), (TH1, TL1) are the 16-bit counter registers for
timer/counters 0 and 1.

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 • Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three
operating modes: capture, auto-reload (up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 2.4. Timer 2 consists of two 8-bit
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12
of the oscillator frequency.

Figure 2.8 Timer 2 Operating Modes

In the Counter function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the transition was detected. Since two
machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the
maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is
sampled at least once before it changes, the level should be held for at least one full machine
cycle.
There are no restrictions on the duty cycle of external input signal, but it should for at
least one full machine to ensure that a given level is sampled at least once before it changes.

• Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 =
0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit
can then be used to generate an interrupt. IfEXEN2 = 1, Timer 2 performs the same
operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2
and TL2 to be captured into RCAP2H andRCAP2L, respectively. In addition, the transition at

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T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, likeTF2, can generate an
interrupt.

• Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-
reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the
SFR T2MOD (see Table 2.5). Upon reset, the DCEN bit is set to 0 so that timer 2 will default
to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the
T2EX pin.

Figure 2.9: T2MOD-Timer 2 Mode Control Register

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2.6 INTERRUPTS
The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts
are all shown in Figure2.c.
Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA which
disables all interrupts at once.
Note that Table 2.7 shows that bit position IE.6 is unimplemented. In the AT89C51,
bit position IE.5 is also unimplemented.

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 Figure 2.10 interrupt sources
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in
register T2CON. Neither of these flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2
that generated the interrupt, and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which
the timers overflow. The values are then polled by the circuitry in the next cycle. However,

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the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer
overflows.

2.7 SPECIAL FUNCTION REGISTERS

Special function registers are the areas of memory that control specific functionality
of the 89c52 microcontroller.

a) Accumulator (0E0h)
As its name suggests, it is used to accumulate the results of large no. of instructions. It
can hold 8 bit values.

b) B register (0F0h)
The B register is very similar to accumulator. It may hold 8-bit value. The B register
is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte of the
products gets stored in B register. In DIV AB the quotient gets stored in B with the remainder
in A.

c) Stack pointer (081h)

The stack pointer holds 8-bit value. This is used to indicate where the next value to be
removed from the stack should be taken from. When a value is to be pushed on to the stack,
the 8052 first store the value of SP and then store the value at the resulting memory location.
When a value is to be popped from the stack, the 8052 returns the value from the memory
location indicated by SP and then decrements the value of SP.

d) Data pointer (Data pointer low/high, address 82/83h)

The SFRs DPL and DPH work together to represent a 16-bit value
called the data pointer. The data pointer is used in operations regarding external RAM and
some instructions code memory. It is a 16-bit SFR and also an addressable SFR.

e) Program counter
The program counter is a 16 bit register, which contains the 2 byte address, which
tells the next instruction to execute to be found in memory. When the 8052 is initialized PC

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starts at 0000h and is incremented each time an instruction is executes. It is not addressable
SFR.

f) PCON (power control, 87h)

The power control SFR is used to control the 8052’s power control modes. Certain
operation modes of the 8052 allow it to go into a type of “sleep mode” which consumes low
power.
SMOD ---- --- ---- GF1 GF0 PD IDL

g)TCON(Timer control, 88h)

The timer mode control SFR is used to configure and
modify the way in which the 8052’s two timers operate. This SFR controls whether each of
the two timers is running or stopped and contains a flag to indicate that each timer has
overflowed. Additionally, some non-timer related bits are located in TCON SER. These bits
are used to configure the way in which the external interrupt flags are activated, which are set
when an external interrupt occur.

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

h)TMOD(Timer Mode,89h)
The timer mode SFR is used to configure the mode of operation of each of the two
timers. Using this SR your program may configure each timer to be a 16-bit timer, or 13 bit
timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the
timers to only count when an external pin is activated or to count “events” that are indicated
on an external pin.
‌ ‌
Gate C/ T M1 M0 Gate C/ T M1 M0

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 TIMER1 TIMER0

i) T0 (Timer 0 low/ high, address 8A/ 8C h)

These two SFRs together represent timer 0. Their exact behavior depends on how the
timer is configured in the TMOD SFR; however, these timers always count up. What is
configurable is how and when they increment in value.

j) T1 (Timer 1 low/ high, address 8B/ 8D h)

These two SFRs together represent timer 1. Their exact behavior depends on how the
timer is configured in the TMOD SFR; however, these timers always count up. What is
configurable is how and when they increment in value.

k) P0 (Port 0, address 80h, bit addressable)

This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of
port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

l) P1(Port 1, address 90h, bit addressable)

This is port 1 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 1 is first written on P1 register. For e.g., bit 0 of
port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

m) P2 (Port 2, address 0A0h, bit addressable)

This is port 2 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 2 is first written on P2 register. For e.g., bit 0 of
port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

n) P3 (Port 3, address 0B0h, bit addressable)

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 This is port 3 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 3 is first written on P3 register. For e.g., bit 0 of
port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

o) IE (Interrupt Enable, 0A8h)

The interrupt enable SFR is used to enable and disable specific interrupts. The low 7
bits of the SFR are used to enable/disable the specific interrupts, where the MSB bit is used to
enable or disable all the interrupts. Thus, if the high bit of IE 0 all interrupts are disabled
regardless of whether an individual interrupt is enabled by setting a lower bit.

___
EA ET2 ES ET1 EX1 ET0 EX0

p) IP (Interrupt Priority, 0B8h)

The interrupt priority SFR is used to specify the relative priority of each interrupt. On
8052, an interrupt may be either low or high priority. An interrupt may interrupt interrupts.
For e.g., if we configure all interrupts as low priority other than serial interrupt. The serial
interrupt always interrupts the system; even if another interrupt is currently executing. No
other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt
routine has the highest priority.

___ ___
PT2 PS PT1 PX1 PT0 PX0

q)PSW (Program Status Word, 0D0h)

The Program Status Word is used to store a number of important bits that are set and
cleared by 8052 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag,
the parity flag and the overflow flag. Additionally, it also contains the register bank select
flags, which are used to select, which of the “R” register banks currently in use.

CY AC F0 RS1 RS0 OV ---- P

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r) SBUF (Serial Buffer, 99h)
SBUF is used to hold data in serial communication. It is physically two registers. One
is write only and is used to hold data to be transmitted out of 8052 via TXD. The other is read
only and holds received data from external sources via RXD. Both mutually exclusive
registers use address 99h.

2.8 MEMORY ORGANISATION

The total memory of 89C52 system is logically divided in Program memory and Data
memory. Program memory stores the programs to be executed, while data memory stores the
data like intermediate results, variables and constants required for the execution of the
program. Program memory is invariably implemented using EPROM, because it stores only
program code which is to be executed and thus it need not be written into. However, the data
memory may be read from or written to and thus it is implemented using RAM.

Further, the program memory and data memory both may be categorized as on-chip
(internal) and external memory, depending upon whether the memory physically exists on the
chip or it is externally interfaced. The 89C52 can address 8Kbytes on-chip memory whose
map starts from 0000H and ends at 1FFFH. It can address 64Kbytes of external program
memory under the control of PSEN (low) signal.

The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. That means the upper 128bytes have
the same addresses as the SFR space but are physically separate from SFR space. When an
instruction accesses an internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions that use direct addressing access SFR space. For example, the following
direct addressing instruction accesses the SFR at location 0A0H (which is P2).

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MOV 0A0H, #data
Instructions that use indirect addressing, access the upper128 bytes of RAM. For
example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the
data byte at address 0A0H, rather than P2 (whose address is 0A0H)
.MOV @R0, #data

CHAPTER 3
REGULATED POWER SUPPLY

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 3.1 DESCRIPTION:

A variable regulated power supply, also called a variable bench power supply, is one
where you can continuously adjust the output voltage to your requirements. Varying the
output of the power supply is the recommended way to test a project after having double
checked parts placement against circuit drawings and the parts placement guide. This type of
regulation is ideal for having a simple variable bench power supply. While a dedicated supply
is quite handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially
for testing. Most digital logic circuits and processors need a 5 volt power supply. To use these
parts we need to build a regulated 5 volt source. To make a 5 volt power supply, we use a
LM7805 voltage regulator IC.

Simply connect the positive lead of your unregulated DC power supply (anything from
9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then
when you turn on the power, you get a 5 volt supply from the Output pin.

Circuit Features:

Brief description of operation: Gives out well regulated +5V output, output current
capability of 100 mA.

• Circuit protection: Built-in overheating protection shuts down output when

regulator IC gets too hot.
• Circuit complexity: Very simple and easy to build.

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 • Circuit performance: Very stable +5V output voltage, reliable operation.
• Availability of components: Easy to get, uses only very common basic
components.
• Design testing: Based on datasheet example circuit, I have used this circuit
successfully as part of many electronics projects.
• Applications: Part of electronics devices, small laboratory power supply.
• Power supply voltage: Unregulated DC 8-18V power supply.
• Power supply current: Needed output current + 5 mA.
• Component costs: Few dollars for the electronics components + the input
transformer cost.

3.2 BLOCK DIAGRAM:

Figure 3.1: Block diagram of power supply

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3.3 CIRCUIT DIAGRAM:

Basic Power Supply Circuit:

Above is the circuit of a basic unregulated dc power supply. A bridge rectifier D1 to
D4 rectifies the ac from the transformer secondary, which may also be a block rectifier such
as WO4 or even four individual diodes such as 1N4004 types. (See later re rectifier ratings).
The principal advantage of a bridge rectifier is you do not need a centre tap on the
secondary of the transformer. A further but significant advantage is that the ripple frequency
at the output is twice the line frequency (i.e. 50 Hz or 60 Hz) and makes filtering somewhat
easier.
As a design example consider we wanted a small unregulated bench supply for our
projects. Here we will go for a voltage of about 12 - 13V at a maximum output current (IL) of
500ma (0.5A). Maximum ripple will be 2.5% and load regulation is 5%.
Now the RMS secondary voltage (primary is whatever is consistent with your area)
for our power transformer T1 must be our desired output Vo PLUS the voltage drops across
D2 and D4 (2 * 0.7V) divided by 1.414.
This means that Vsec = [13V + 1.4V] / 1.414 which equals about 10.2V. Depending on the
VA rating of your transformer, the secondary voltage will vary considerably in accordance

26
with the applied load. The secondary voltage on a transformer advertised as say 20VA will be
much greater if the secondary is only lightly loaded.
If we accept the 2.5% ripple as adequate for our purposes then at 13V this becomes 13
* 0.025 = 0.325 Vrms. The peak to peak value is 2.828 times this value. Vrip = 0.325V X
2.828 = 0.92 V and this value is required to calculate the value of C1. Also required for this
calculation is the time interval for charging pulses. If you are on a 60Hz system it it 1/ (2 *
60) = 0.008333 which is 8.33 milliseconds. For a 50Hz system it is 0.01 sec or 10
milliseconds.
Remember the tolerance of the type of capacitor used here is very loose. The
important thing to be aware of is the voltage rating should be at least 13V X 1.414 or 18.33.
Here you would use at least the standard 25V or higher (absolutely not 16V).With our
rectifier diodes or bridge they should have a PIV rating of 2.828 times the Vsec or at least
29V. Don't search for this rating because it doesn't exist. Use the next highest standard or
even higher. The current rating should be at least twice the load current maximum i.e. 2 X
0.5A or 1A. A good type to use would be 1N4004, 1N4006 or 1N4008 types.
These are rated 1 Amp at 400PIV, 600PIV and 1000PIV respectively. Always be on
the lookout for the higher voltage ones when they are on special.

3.4 IC VOLTAGE REGULATORS:

Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the
circuitry for reference source, comparator amplifier, control device, and overload protection
all in a single IC. Although the internal construction of the IC is somewhat different from that
described for discrete voltage regulator circuits, the external operation is much the same. IC
units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an
adjustably set voltage.

Three-Terminal Voltage Regulators:

Fixed Positive Voltage Regulators:

Vin IN OUT Vout

78XX

C1 GND C2

27
 Fig shows the basic connection of a three-terminal voltage regulator IC to a load. The
fixed voltage regulator has an unregulated dc input voltage Vi, applied to one input terminal,
a regulated output dc voltage, Vo from a second terminal, with the third terminal connected
to ground. While the input voltage may vary over some permissible voltage range, and the
output load may vary over some acceptable range, the output voltage remains constant within
specified voltage variation limits.

TABLE: Positive Voltage Regulators in 7800 series

IC No. Output voltage(v) Maximum input voltage(v)

7805 +5
7806 +6 35V
7808 +8
7810 +10
7812 +12
7815 +15
7818 +18
7824 +24 40V

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CHAPTER 4
ULN 2003

29
 ULN is mainly suited for interfacing between low-level circuits and multiple
peripheral power loads. The series ULN20XX high voltage, high current Darlington arrays
feature continuous load current ratings. The driving circuitry in- turn decodes the coding and
conveys the necessary data to the stepper motor, this module aids in the movement of the arm
through steppers.

4.1 PIN CONNECTION

4.2 DESCRIPTION
The driver makes use of the ULN2003 driver IC, which contains an array of 7 power
Darlington arrays, each capable of driving 500mA of current.
The device has base resistors, allowing direct connection to any common logic family.
All the emitters are tied together and brought out to a separate terminal. Output protection
diodes are included; hence the device can drive inductive loads with minimum extra

30
components. Typical loads include relays, solenoids, stepper motors, magnetic print
hammers, multiplexed LED, incandescent displays and heaters.

Note that the first pin is connected to D0 of the parallel port. Each successive pin
of the stepper motor is connected to successive data lines on the parallel port. If this order is
not correct, the motor will not rotate, but will wiggle around from side to side. The clamp
circuit shown does not connect the clamp directly to the supply voltage. Instead, it uses a
zener diode. This ensures that the decaying current in the coils are not abruptly cut off, which
produces a lot of heat.

It is simple, it involves setting the bits on the port on and off in a specific
sequence. The step sequence is given below for full step and half steps. At any time only one
pin is active in the full step.

Full Step Half Step

Step No. D0 D1 D2 D3 Step No. D0 D1 D2 D3
1 1 0 0 0 1 1 0 0 0
2 0 1 0 0 2 1 1 0 0
3 0 0 1 0 3 0 1 0 0
4 0 0 0 1 4 0 1 1 0
5 0 0 1 0
6 0 0 1 1
7 0 0 0 1
8 1 0 0 1

The difference between half step and full step is that for the same step rate, half-step gives
you half the speed, twice the resolution, and roughly twice the power consumption. It also

31
gives you twice the torque. To reverse the direction of the motor, send the sequence in
reverse order.

The main features of ULN2003 are as follows:

• Seven Darlington per package
• Output current 500ma per driver (600ma peak)
• Output voltage 50v.
• Integrated suppression diodes for inductive loads
• Outputs can be paralleled for high current TTL/CMOS/DTL compatible inputs
• Inputs pinned opposite outputs to simplify layout.
• Transient protected outputs
• Dual In-Line plastic package or small-Outline IC package.

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CHAPTER 5
LCD

33
5.1 DESCRIPTION
To send any of the commands from given table to the lcd, make pin RS =0.For data,
make RS=1, then send a high to low pulse to the E pin to enable the internal latch of the
LCD. As shown in figure for LCD connections.

34
 5.2 PIN CONNECTION

Pin
Symbol Level I/O Function
number
1 Vss - - Power supply (GND)
2 Vcc - - Power supply (+5V)
3 Vee - - Contrast adjust
0 = Instruction input
4 RS 0/1 I
1 = Data input
0 = Write to LCD module
5 R/W 0/1 I
1 = Read from LCD module
6 E 1, 1->0 I Enable signal
7 DB0 0/1 I/O Data bus line 0 (LSB)
8 DB1 0/1 I/O Data bus line 1
9 DB2 0/1 I/O Data bus line 2
10 DB3 0/1 I/O Data bus line 3
11 DB4 0/1 I/O Data bus line 4
12 DB5 0/1 I/O Data bus line 5
13 DB6 0/1 I/O Data bus line 6
14 DB7 0/1 I/O Data bus line 7 (MSB)

Pin
Symbol Level I/O Function
number
1 DB7 0/1 I/O Data bus line 7 (MSB)
2 DB6 0/1 I/O Data bus line 6
3 DB5 0/1 I/O Data bus line 5

35
Pin
Symbol Level I/O Function
number
4 DB4 0/1 I/O Data bus line 4
5 DB3 0/1 I/O Data bus line 3
6 DB2 0/1 I/O Data bus line 2
7 DB1 0/1 I/O Data bus line 1
8 DB0 0/1 I/O Data bus line 0 (LSB)
9 E1 1, 1->0 I Enable signal row 0 & 1 (1stcontroller)
0 = Write to LCD module
10 R/W 0/1 I
1 = Read from LCD module
0 = Instruction input
11 RS 0/1 I
1 = Data input
12 Vee - - Contrast adjust
13 Vss - - Power supply (GND)
14 Vcc - - Power supply (+5V)
15 E2 1, 1->0 I Enable signal row 2 & 3 (2ndcontroller)
16 n.c.

36
 CHAPTER 6

STEPPER MOTOR

37
 6.1 DESCRIPTION:

A stepper motor is an electromechanical device which converts electrical pulses into discrete
mechanical movements. The stepper motor is used for position control in applications like disk drives
and robotics.

The name stepper is used because this motor rotates through a fixed angular step in
response to each input current pulse received by its controller. Their popularity is due to the
fact that they can be controlled directly by computers, microprocessors and programmable
controllers.

A stepper motor's shaft has permanent magnets attached to it. Around the body of the
motor is a series of coils that create a magnetic field that interacts with the permanent
magnets. When these coils are turned on and off the magnetic field causes the rotor to move.
As the coils are turned on and off in sequence the motor will rotate forward or reverse.

6.2 BACK EMF

A motor is a machine which converts electric energy into mechanical energy. Its
action is based on the principle that when a current carrying conductor is placed in a magnetic
field, it experiences a mechanical force whose direction is given by Fleming’s left hand rule.

The ULN2003 / MC1413 is a 7-bit 50V 500mA TTL-input NPN darlington driver.
This is more than adequate to control a four phase unipolar stepper motor such as the
KP4M4-001.

38
It is recommended to connect a 12v zener diode between the power supply and VDD (Pin 9)
on the chip, to absorb reverse (or "back") EMF from the magnetic field collapsing when
motor coils are switched off.

6.3 DRIVING A STEPPER MOTOR

The four leads of the stator winding are controlled by the four bits of the 8051 port
(p1.0-p1.3). However, since the 8051 lacks sufficient current to drive the stepper motor
windings, we must use a driver such as uln2003a to energize the stator. However, notice that
if transistors are used as drivers, we must also use diodes to take care of inductive current
generated when the coil is turned off. One reason that the uln2003a is preferable to the use of
transistors as drivers is that the uln2003 has as internal diode to take care of back emf.

39
CHAPTER 7
KEYPAD

40
 At the lowest level, keyboards are organized in a matrix of row and columns. The
CPU access both rows and columns through ports therefore, with two bit ports, an 4x3 matrix
of keys can be connected to the microprocessor. When a key is pressed, a row and column
make contact; otherwise there is no connection between rows and columns.
Figure shows 4x4 matrixes connected to two ports. The rows are connected to out port
and columns are connected to an input port. If no key has been pressed, reading the port will
yield 1s for all column since all they are connected to high (Vcc). If all the rows are grounded
and key is pressed provides the path to the ground. It is the function of the microcontroller to
scan the keyboard continuously to detect and identify the key is pressed.

Figure 7.1 keypad interface

41
 CHAPTER 8
KEIL SOFTWARE

42
 8.1 SOFTWARE DESCRIPTION:

1. Click on the Keil uVision Icon on Desktop

2. The following fig will appear

3. Click on the Project menu from the title bar

4. Then Click on New Project

43
5. Save the Project by typing suitable project name with no extension in u r own
folder sited in either C:\ or D:\

6. Then Click on Save button above.

7. Select the component for u r project. i.e. Atmel……
8. Click on the + Symbol beside of Atmel

9. Select AT89C51 as shown below

44
10. Then Click on “OK”
11. The Following fig will appear

12. Then Click either YES or NO………mostly “NO”

13. Now your project is ready to USE

45
14. Now double click on the Target1, you would get another option “Source group 1”
as shown in next page.

15. Click on the file option from menu bar and select “new”

16. The next screen will be as shown in next page, and just maximize it by double
clicking on its blue boarder.

46
17. Now start writing program in either in “C” or “ASM”
18. For a program written in Assembly, then save it with extension “. asm” and for
“C” based program save it with extension “ .C”

19. Now right click on Source group 1 and click on “Add files to Group Source”

47
20. Now you will get another window, on which by default “C” files will appear.

21. Now select as per your file extension given while saving the file
22. Click only one time on option “ADD”
23. Now Press function key F7 to compile. Any error will appear if so happen.

48
24. If the file contains no error, then press Control+F5 simultaneously.
25. The new window is as follows

26. Then Click “OK”

27. Now Click on the Peripherals from menu bar, and check your required port as
shown in fig below

49
 28. Drag the port a side and click in the program file.

29. Now keep Pressing function key “F11” slowly and observe.
You are running your program successfully

50
 CHAPTER 9
SOURCE CODING

51
 FLOW CHART:
ON
Power supply
SUPPLY

Displays:
Enter
password

Type Password from

keypad

Display:

Valid password
Welcome

False
If
Password

Buzzer sound
True

Door opens and closes

With given time delay
Display:
Invalid
password
STOP

52
#include<reg51.h>
#include<string.h>
#define COL P2 //LOWER PINS OF PORT 2 :0,1,2
#define ROW P3 //LOWER PINS OF PORT 3 :0,1,2,3

sfr LCDDATA=0X90;//PORT 1;

sbit RS=P2^5;
sbit RW=P2^6;
sbit EN=P2^7;
sbit BUZZER=P2^3;
KEYPAD1();
lcdcmd(unsigned char);
lcddata();
serail();
lcddata1();
lcddata2();
lcddata3();
lcddata4();
lcddata5();
lcddata6(unsigned char);
lcdready();
strngcmp();
stepmotor();
delay(unsigned int);
int i,j,r ;
char passwd[4]="1234";
unsigned char keypad[4][3]=
{'1', '2', '3',
'4', '5', '6',
'7', '8', '9',
'*', '0', '#'};
char a[5];
main()
53
{
BUZZER=0;
lcdcmd(0x38);
lcdcmd(0x0E);
lcdcmd(0x01);
lcdcmd(0x06);
lcdcmd(0x81);
lcddata();
while(1)
{
serail();
strngcmp();
}//while(1)
}// MAIN CLOSE...........
///////////////////////////////////////////////////////////////////
strngcmp()
{
if((strcmp(passwd,a) ==0))
{
lcddata2();
lcdcmd(0xc3);
lcddata4();
stepmotor();
}
else
{
lcddata3();
lcdcmd(0xc3);
lcddata5();
BUZZER=1;
}
}// closing strcmp
serial()
{
54
 for(i=0;i<4;i++)
{
a[i]=KEYPAD1();
lcddata6('*');
}
}
////////////////////////////////////////////////
lcddata()
{
unsigned char s;
unsigned char temp[14]="ENTER PASSWORD";
lcdready();
for(s=0;s<14;s++)
{
LCDDATA=temp[s];

RS=1;
RW=0;
EN=1;
delay(1);
EN=0;
}
}
//////////////////////////////////////////////////////////////////
lcddata2()
{
unsigned char s;
unsigned char temp[12]=" VALID ";
lcdready();
for(s=0;s<12;s++) //DATA2
{
LCDDATA=temp[s];
RS=1;
RW=0;
55
EN=1;
delay(1);
EN=0;
}
}
///////////////////////////////////////////////////////////////////
lcddata3()
{
unsigned char s;
unsigned char temp[12]=" IN VALID ";
lcdready();
//DATA3
for(s=0;s<12;s++)
{
LCDDATA=temp[s];

RS=1;
RW=0;
EN=1;
delay(1);
EN=0;
}
}
/////////////////////////////////////////////////////////////////
lcddata4()
{
unsigned char s;
unsigned char temp[12]=" WELCOME ";
lcdready();
//DATA4
for(s=0;s<12;s++)
{
LCDDATA=temp[s];
RS=1;
56
RW=0;
EN=1;
delay(1);
EN=0;
}}
////////////////////////////////////////////////////////////////////////////
lcddata5()
{
unsigned char s;
unsigned char temp[12]=" SORRY ";
lcdready();

for(s=0;s<12;s++)
{ //DATA5
LCDDATA=temp[s];

RS=1;
RW=0;
EN=1;
delay(1);
EN=0;
}}
//////////////////////////////////////////////////////////////
lcdcmd(unsigned char value)
{
lcdready();
LCDDATA=value;
RS=0;
RW=0;
EN=1;
delay(1);
EN=0;
return;
}
57
//////////////////////////////////////////////////
lcdready()
{
BUSY=1;
RS=0;
RW=1;
while(BUSY==1)
{
EN=0;
delay(1);
EN=1;
}
return;
}
/////////////////////////////////////////////////////////////
lcddata6(unsigned char value)
{
LCDDATA=value;
RS=1;
RW=0;
EN=1;
delay(1);
EN=0;
delay(1);
return;
}
/////////////////////////////////////////////////////////////
delay(unsigned int time)
{
unsigned int i,j;
for(i=0;i<time;i++)
for(j=0;j<1275;j++);
}
KEYPAD1()
58
 {
char colloc, rowloc;
COL=0xFF;
while(1)
{
do
{
ROW=0x00;
colloc=COL;
colloc&=0x07;
}
while(colloc!=0x07);
do
{
do
{
delay(1);
colloc=COL;
colloc &= 0x07;
}
while(colloc==0x07);
delay(1);
colloc=COL;
colloc&=0x07;
}
while(colloc==0x07);
while(1)
{
ROW=0xFE;
colloc=COL;
colloc&=0x07;
if (colloc != 0x07)
{
rowloc=0;
59
break;
}
ROW=0xFD;
colloc=COL;
colloc&=0x07;
if (colloc != 0x07)
{
rowloc=1;
break;
}
ROW=0xFB;
colloc=COL;
colloc&=0x07;
if (colloc != 0x07)
{
rowloc=2;
break;
}
ROW=0xF7;
colloc=COL;
colloc&=0x07;
if (colloc != 0x07)
{
rowloc=3;
break;
}
}
if (colloc== 0x06)
return(keypad[rowloc][0]);
else if(colloc==0x05)
return(keypad [rowloc][1]);
else
return(keypad [rowloc][2]);
}
60
}
stepmotor()
{
P0=0X11;
delay(20);
P0=0X22;
delay(20);
P0=0X44;
delay(20);
P0=0X88;
delay(20);
P0=0X11;
delay(20);
P0=0X22;
delay(20);
P0=0X44;
delay(20);
P0=0X88;
delay(20);
P0=0X11;
delay(20);
P0=0X22;
delay(20);
P0=0X44;
delay(20);
P0=0X88;
delay(20);
P0=0X44;
delay(20);
P0=0X22;
delay(20);
P0=0X11;
delay(20);
P0=0X88;
61
delay(20);
P0=0X44;
delay(20);
P0=0X22;
delay(20);
P0=0X11;
delay(20);
P0=0X88;
delay(20);
P0=0X44;
delay(20);
P0=0X22;
delay(20);
P0=0X11;
delay(20);
}

62
CHAPTER 10
INTERFACING

63
10.1 INTERFACING ULN2003 AND STEPPER MOTOR:

64
10.2 INTERFACING KEYPAD,MICROCONTROLLER AND LCD:

65
CONCLUSION:
Embedded systems are emerging as a technology with high potential. In the past
decades micro processor based embedded system ruled the market. The last decade witnessed the
revolution of Microcontroller based embedded systems. This project deals with providing access
only if the password of particular user is matched. So, every user is given a unique password. So
that access is denied to unauthorized persons.
This system can be used in military areas, bank security and security for important
documents.

FUTURE SCOPE:
This system is a rapidly growing field and there are new and improved
strategies popping up all the time. For the most part these systems are all built around the
Passwords, so that access is denied to unauthorized persons.
This system is best for guiding the offices, banks or a business center the points
where an intruder would enter the building. This project provides an efficient and economical
security system. This system finds applications in industries, banks and homes.

66
REFERENCES
BOOKS:
1. The 8051 Microcontroller and Embedded Systems by Muhammad Ali Mazidi.
2. Fundamentals of Embedded Software by Daniel W Lewis.

WEB SITES: DATASHEETS:

1. www.howsstuffworks.com 1. Datasheets of Microcontroller

AT89S52
2. www.alldatasheets.com 2. Datasheets of stepper motor
3. www.electronicsforu.com 3. Datasheets of ULN2003
4. www.8051 projectsinfo.com

67