1.

INTRODUCTION

The term Video Graphics Array (VGA) refers specifically to the display
hardware first introduced with the IBM. VGA is referred to as an "array"
instead of an "adapter" because it was implemented from the start as a single
chip replacing the dozens of discreet logic chips.
The VGA Controller provides a simple, interface between a host processor
and any VGA-compatible monitor.
Taking a processor-generated picture (pixilated) from memory space, the
Controller provides digital RGB values for each pixel, as well as horizontal
and vertical synchronization signals, in order to correctly display the picture on
a connected monitor.

1
 2. HISTORY

The term Video Graphics Array (VGA) refers specifically to the display
hardware first introduced with the IBM PS/2 line of computers in 1987, but
through its widespread adoption has also come to mean either an analog
computer display standard, the 15-pin D-subminiature VGA connector or the
640×480 resolution itself. While this resolution has been superseded in the
personal computer market, it is becoming a popular resolution on mobile
devices.

Video Graphics Array (VGA) was the last graphical standard introduced by
IBM that the majority of PC clone manufacturers conformed to, making it
today (as of 2009) the lowest common denominator that all PC graphics
hardware supports, before a device-specific driver is loaded into the computer.
For example, the MS-Windows splash screen appears while the machine is still
operating in VGA mode, which is the reason that this screen always appears in
reduced resolution and color depth.

VGA was officially superseded by IBM's XGA standard, but in reality it was
superseded by numerous slightly different extensions to VGA made by clone
manufacturers that came to be known collectively as "Super VGA".

2.1. VGA compared to other standard resolutions.

VGA is referred to as an "array" instead of an "adapter" because it was

implemented from the start as a single chip (an ASIC), replacing the Motorola
6845 and dozens of discrete logic chips that covered the full-length ISA boards
of the MDA, CGA, and EGA. Its single-chip implementation also allowed the
VGA to be placed directly on a PC's motherboard with a minimum of
difficulty (it only required video memory, timing crystals and an external
RAMDAC), and the first IBM PS/2 models were equipped with VGA on the
motherboard.

2
 2.2 The VGA specifications are as follows:

• 256 KB Video RAM (The very first cards could be ordered with 64KB or
128KB of RAM at the cost of losing some video modes).
• 16-color and 256-color modes
• 262,144-value color palette (six bits each for red, green, and blue)
• Selectable 25.175 MHz or 28.322 MHz master clock
• Maximum of 800 horizontal pixels
• Maximum of 600 lines
• Refresh rates at up to 70 Hz
• Vertical blank interrupt
• Packed-pixel mode: 256 colors
• Hardware smooth scrolling support

The VGA supports both All Points Addressable graphics modes, and
alphanumeric text modes. Standard graphics modes are:

• 640×480 in 16 colors
• 640×350 in 16 colors
• 320×200 in 16 colors
• 320×200 in 256 colors

3
 3. DESCRIPTION ARCHITECTURE

3.1 VGA display device

VGA display device used for displaying the images taken from the
processor in an exact format. It can be used for displaying the output of any
projects. Analog, graphs etc… can be directly displayed on the VGA display
monitor.

3.1 VGA (Video Graphics Array) Controller:

Image or video
processing VGA Display
system Controller

VGA controller controls the image to be exactly displayed on the display

device. It acts as an interface between processing system and display device, so
called as interface controller.

4
 4. CONTROLLER DESIGN

For this first we should know how the display device works. Consider an
image below,

640x480

Original image

5
 Pixels of image
Display device also have pixels. Display resolution (640*480) is a
standard resolution of display.

Pixel

This article is about the picture element. For other uses, see Pixel
(disambiguation).

This example shows an image with a portion greatly enlarged, in which the
individual pixels are rendered as little squares and can easily be seen.

6
 4.2 A photograph of sub-pixel display elements on a laptop's LCD screen

[1]
In digital imaging, a pixel (or picture element ) is a single point in a raster
image. The pixel is the smallest addressable screen element, it is the smallest
unit of picture which can be controlled. Each Pixel has its address. The address
of a pixel corresponds to its coordinate. Pixels are normally arranged in a 2-
dimensional grid, and are often represented using dots or squares. Each pixel is
a sample of an original image, where more samples typically provide more-
accurate representations of the original. The intensity of each pixel is variable.
In color image systems, a color is typically represented by three or four
component intensities such as red, green, and blue, or cyan, magenta, yellow,
and black.

Color refreshing rate:

Color refreshing rate =60Hz

• Color refreshing rate represents the number of frames that are transmitted per
second.

• Minimum number of frames that can be transmitted per second by VGA

controller is 60.

7
 5. Hardware Description

5.1 Block Diagram:

5.1 VGA Synchronization Unit:

8
 The Synchronization Unit provides the horizontal and vertical
synchronization signals – HSYNC and VSYNC – that are required to correctly
display a picture frame within the confines of a monitor’s display area.
These synchronization signals are used as control inputs by the
monitor’s horizontal and vertical deflection circuits. These circuits deflect the
electrons emitted by the three primary color electron guns (Red, Green, Blue)
left to right and from top to bottom, respectively. HSYNC provides the start
and stop times for the horizontal deflection circuit, so that a line of pixels is
correctly drawn across the screen display. VSYNC provides the start and stop
times for the vertical deflection circuit, so that the lines of a frame are correctly
drawn from the top to the bottom of the screen display.
The resolution for the display is defined by the level on the
RESOLUTION input. If High, the 640x480 resolution is used (VGA). If Low,
the 800x600 resolution (SVGA) is used.
Although the resolution determines the area of a monitor’s screen
within which an image can be displayed, the full extents of the chosen
resolution do not have to be used. The actual extents of the image display area
on the screen can be controlled by the use of the DISPSIZE_H and
DISPSIZE_V inputs. These inputs determine the total number of pixels to be
used in a line and the total number of lines in a frame, respectively.

5.2 Blank pixel generation

The total number of viewable pixels in a line and viewable lines in a

frame is determined by the display resolution chosen through the
RESOLUTION input (1= 640x480; 0 = 800x600) and the values received on
the DISPSIZE_H and DISPSIZE_V buses. Whether the full extent of the
chosen display resolution is used or not, the areas of the monitor screen to the
top, bottom, left and right of the viewable frame area are blanked, by putting
black pixels at the required line-pixel positions. This has the effect of centering
the image on the screen.

9
 The color generated for a pixel in the Pixel Unit depends on whether
the particular pixel requires to be blanked or not. The Synchronization Unit
provides a signal to the Pixel Unit for this very reason. This is the line display
enable signal - en. The signal is checked on each rising edge of the external
clock signal (CLK) and is set as follows:
If (HCOUNT ≥ PixTotal) or (VCOUNT ≥ LinTotal) then
en = 0 (pixel requires to be blanked – set color to be black)
Else
en = 1 (pixel is a viewable pixel – generate RGB color accordingly).

6. SIGNALS IN VGA CONTROLLER

For most common VGA mode 640x480 "60 Hz" non-interlaced the horizontal
timings are:

Parameter Value Unit

Clock frequency 25.175 MHz
Horizontal pixels 640
Horizontal sync polarity Negative
Total time for each line 31.77 µs
Front porch (A) 0.94 µs
Sync pulse length (B) 3.77 µs
Back porch (C) 1.89 µs
Active video (D) 25.17 µs

(Total horizontal sync time 6.60 µs)

10
 6.1 The vertical timings are:

Parameter Value Unit

Vertical lines 480
Vertical sync polarity Negative
Vertical frequency 59.94 Hz
Front porch (E) 0.35 ms
Sync pulse length (F) 0.06 ms
Back porch (G) 1.02 ms
Active video (H) 15.25 ms

(Total vertical sync time 1.43 ms)

640 x 400 @ 70 Hz is video mode used for booting most x86 personal
computers.

640 x 480 @ 60 Hz is the default MS-Windows graphics mode with 16 colors.

It should be noted that the actual timings vary slightly. For example for
640x480 @ 60fps a 25,17 µs active video time with a pixel frequency of
25,174 MHz gives 633 pixels rather than the expected 640 pixels.

6.2 Generation of the horizontal synchronization signal – HSYNC:

11
 The HSYNC signal is High (inactive) after an external reset signal
(RST) is received by the VGA Controller. The signal is updated on each rising
edge of the external clock signal (CLK).
The state of the HSYNC signal depends on the value stored in the horizontal
counter and is driven low when:
HCOUNT ≥ (PixTotal + BlankingLeft)
and remains low while:
HCOUNT < (PixTotal + BlankingLeft + TLSync)
Vertical (Frame) Period :

6.3 Generation of the vertical synchronization signal - VSYNC :

The VSYNC signal is High (inactive) after an external reset signal

(RST) is received by the VGA Controller. The signal is updated after every
line of pixels is completed (i.e. on each rising edge of the HSYNC signal).
The state of the VSYNC signal depends on the value stored in the vertical
counter and is driven low when:
VCOUNT ≥ (LinTotal + BlankingLeft)
and remains low while:
VCOUNT < (LinTotal + BlankingLeft + TFSync)

Address Counter (MEMADDR):

The address counter is used to store the position of the next consecutive
pixel in the frame. Its value is passed to the Pixel Unit on the internal bus
signal hvcnt, which is then used to provide the ADDR_PIXEL signal, to obtain
the next pixel from picture memory.
The counter is reset to zero when the VGA Controller receives an external
reset signal (RST). The size of the counter depends on the values chosen for
DISPSIZE_H and DISPSIZE_V, as the range is simply:
0 to (PixTotal x LinTotal) - 1

12
 Taking the maximum number of pixels in a line and lines in a frame, for each
of the supported display resolutions, the maximum ranges for the counter are:
• 640x480: 0 to 307199
• 800x600: 0 to 479999.
The counter has 19-bit resolution.

While the value in the horizontal counter (HCOUNT) is less than the
total number of viewable pixels in a line (PixTotal, the integer value of
DISPSIZE_H), the counter is incremented on the rising edge of the external
clock signal (CLK). Pixel addressing within the frame is consecutive. When
the counter reaches the last pixel in a line, its incremented value is the first
pixel in the next line down.
The address counter will continue to be incremented until the value in the
vertical counter (VCOUNT) is greater than or equal to the total number of
viewable lines in a frame (LinTotal, the integer value of DISPSIZE_V). At this
point, it will be rolled over to zero.

13
 7. VGA Controller
The VGA Controller provides a simple, 8-bit interface, between a host
microcontroller and any VGA-compatible monitor. This variant of the
Controller provides six modes of display, depending on the resolution chosen
(640x480 (VGA) or 800x600 (SVGA)) and the color palette (either Black &
White, 16 Colors, or 64 Colors).

7.1 VGA Controller Tasks:-

1) To display the frames at minimum 60hz refreshing rate
For 1sec = 60 frames
1 frame = max. 1/60 sec
1 pixel = 1/60 sec = 50ns
307200
Max. Time for 1 pixel = 40ns
2) To send information for each and every pixel of a frame by means of
RGB signals.

3) After completely displaying 1 row information, the column must be

refreshed and the row has to be incremented. i.e., done by Hsync signal.

4) After completing 1 frame of information, a new frame has to be started

for this row and column are to be refreshed .i.e., done by Vsync signal.

=> For giving information for 1 pixel we use 1 clock (for controlling all
operations).

14
 1 clock = 1 pixel
1 clock cycle period = 40ns.
Clock frequency = 1/time period =1/40ns = 25 mhz
1 clock frequency = 25 mhz.

So, if we use 25mhz clock and display 1 pixel information for each and enery
clock then we use can attain min. 60hz refreshing rate.
do not use the clock frequency less than 25mhz.

Ex:
15MHz 25MHz
30MHz

Time period = more effectively utilized frequency

Less

No. of frames/sec = less

More

Decreases
Increases
(It is unable to display 60frames/sec)

Signals used for image display:-

R (Red)
G (Green)
B (Blue)

15
HSYNC (Horizontal Synchronous signal)
VSYNC (Vertical Synchronous signal)

All the above signals are used to control the image data to be correctly
displayed on the VGA display monitor.

7.2 Timings for front port, sync pulse, back port:-

Horizontal sync: Vertical sync:

Front port: 0.94µs Front port: 0.35ms

Sync pulse: 3.77 µs Sync pulse: 0.063ms
Back port: 1.89 µs Back port: 1.02ms

16
 8. FUNCTIONAL DESCRIPTION
8.1 Symbol:

VGA Controller Symbol

Pin description:
The pin description is shown in the below table.
Table VGA Pin description:

Name Type Polarity/ Bus size Description

Global Control Signals
CLK I Rising
Global system clock. This
clock determines the
maximum rate at which
pixels can be sent to the
monitor. The frequency of
the clock signal determines
the refresh rate as follows:
640x480
CLK = 25MHz, Refresh =

17
 60Hz
CLK = 30MHz, Refresh =
72Hz
800x600
CLK = 40MHz, Refresh =
60Hz
CLK = 50MHz, Refresh =
72Hz.
RST I High Global system reset

VGA Input Settings Signals

RESOLUTION I High / Low This input selects the screen

CMOD I 2
DISPSIZE_H I 10
DISPSIZE_V I 10
Data Memory Control Signals
resolution to be used.
1 = 640x480 (VGA)
0 = 800x600 (SVGA).
This input selects the color
palette to be used:
00 = Black & White
01 = 16 Colors
10 = 64 Colors.
This input determines the
number of viewable pixels
to be displayed in each line
of a frame and is therefore
used to control the
horizontal extents of the
visible display area.
This input determines the
number of lines to be
displayed in a frame and is
therefore used to control the
vertical extents of the visible
display area.

RD O High This is the enable signal

when data is required to be
read from the memory
space. This signal is
controlled by, and follows,
the internal line enable
signal, en, generated by the

18
 Synchronization Unit of the
Controller.

DATA I 8 Data input from picture

ADDR_PIXEL
VGA Monitor Control Signals
memory space. Data is
stored in memory in bytes,
the content of which
depends on the chosen color
palette as follows:
Black & White mode : 8, 1-
bit pixels
16 Colors mode : 2, 4-bit
pixels
64 Colors mode : 1, 6-bit
pixel (DATA[5..0])
Note : In 64 Colors mode,
bits 7 and 6 of each byte are
not used.
O 19 Specifies the address of the
next pixel in picture
memory. Addresses are
consecutive – once the end
of the current line has been
reached, the next address is
that of the pixel at the start
of the next line down in the
frame.

HSYNC O Falling Horizontal synchronization

signal. This signal is used to
control the horizontal
deflection circuit in the

19
 VGA monitor, so that the
start and end of a line of
pixels is correctly displayed
across the visible display
area of the screen. The
horizontal size of the display
area is controlled by the
DISPSIZE_H input to the
R1 O High / Low Provides the 2-bit digital
Controller
signal for the intensity of red
VSYNC O Falling Vertical synchronization
used in composing a pixel's
signal. This signal is used to
displayed color. These two
control the vertical
signals are inputs to a simple
deflection circuit in the VGA
2-bit DAC (external to the
monitor, so that the start and
Controller) that provides the
end of a frame (of lines) is
analog signal required by the
correctly displayed between
VGA monitor.
the top and bottom edges of
the visible display area of the
screen. The vertical size of
the display area is controlled
by the DISPSIZE_V input to
the Controller.

G1 O High / Low Provides the 2-bit digital

signal for the intensity of
S green used in composing a
pixel's displayed color. These
two signals are inputs to a
simple 2-bit DAC (external to
the Controller) that provides
the analog signal required by
the VGA monitor.

B1 O High / Low Provides the 2-bit digital

signal for the intensity of
blue used in composing a
pixel's displayed color.
These two signals are
inputs to a simple 2-bit
DAC (external to the
Controller) that provides
the analog signal required
by the VGA monitor.

9. VGA SIGNAL TIMING

20
 Figure 3 summarizes the signal timing involved in sending a line of
pixels and a frame of lines. The actual time values differ according to the
resolution selected (640x480 or 800x600), the processor-defined values for
DISPSIZE_H and DISPSIZE_V and the frequency of the external clock signal
(CLK).

21
 9.1 VGA PIXEL UNIT:
The Pixel Unit provides access to the pixilated image stored in external
picture memory, reading in data a byte at a time and formatting each pixel to
be displayed. For each pixel, the 6-bit RGB value required for the control of
the monitor’s three, primary color electron guns is generated, so that the pixel
is displayed on the screen with the correct color.

Accessing the stored image

The image to be displayed on the monitor screen is written, by the host
microcontroller, into external memory space (RAM). This memory space can
be located anywhere (e.g. using a block of RAM within the FPGA design, or
using the SRAM on the NanoBoard itself).
Pixel data is stored in the memory space in bytes. The number of pixels in a
byte depends on which color palette is being used for the image (selected by
the CMOD input):
• in Black & White mode – one byte of data in RAM contains 8, 1-bit pixels
• in 16 Colors mode – one byte of data in RAM contains 2, 4-bit pixels
• in 64 Colors mode – one byte of data in RAM contains 1, 6-bit pixel
(DATA[7..6] are not used)

22
 The size of memory required to store a picture is determined by the total
number of viewable pixels in a line (determined by DISPSIZE_H), the total
number of viewable lines in a frame (determined by DISPSIZE_V) and the
number of pixels stored in each byte in memory space:
Memory required for picture = (PixTotal x LinTotal) / number of pixels per byte
The address in RAM where the next pixel is stored is determined using
an internal signal provided by the Synchronization Unit – hvcnt – which
reflects the current contents of the MEMADDR register. The exact addressing
is described below.

9.2 Black & White mode

The picture memory address – the byte of data containing the next 8 pixels
– is determined by using bits 18..3 of hvcnt and right shifting the contents by
three:
ADDR_PIXEL = "00" & hvcnt[18..3]

16 Colors mode
The picture memory address – the byte of data containing the next 2 pixels
– is determined by using bits 18..1 of hvcnt and right shifting the contents by
one:
ADDR_PIXEL = '0' & hvcnt[18..1]

64 Colors mode
The picture memory address – the byte of data containing the next pixel – is
determined by using the full value of hvcnt:
ADDR_PIXEL = hvcnt[18..0]

The Pixel register (PIXREG)

The Pixel register is used to receive the byte of pixel data read from the
current address in memory space. The register, PIXREG, is reset to zero when
the VGA Controller receives an external reset signal (RST).

23
 The register is updated on each rising edge of the CLK signal. Data can be
read from the memory space as long as the RD signal is active (High). The RD
signal is itself controlled by the external line display enable signal, enex. This
internally generated signal is defined as follows:
If ((HCOUNT > (PixTotal+1)) and (HCOUNT < Line Period)) or ((VCOUNT >
(LinTotal+1)) and (VCOUNT < Frame Period)) then enex = 0
Else
enex = 1
When enex is Low, read access from memory is disabled (RD = 0).
The point at which data is loaded from memory into PIXREG depends on the
particular color palette that is chosen – Black & White, 16 Colors, or 64
Colors.

Black & White mode

The next byte of data will be loaded into the register whenever the
lowest three bits of the hvcnt signal – received from the Synchronization Unit -
are “000”.
For the currently loaded byte, the active pixel is always in the lowest bit
position of the Pixel register. Each pixel in the data byte is moved into this
active pixel position by shifting the contents of the register right by one bit, on
each rising edge of CLK.

16 Colors mode
The next byte of data will be loaded into the register whenever the
lowest bit of the hvcnt signal – received from the Synchronization Unit - is a
'0'.
For the currently loaded byte, the active pixel is always in the low order
nibble of the Pixel register. Remember that in this mode, each byte of data
contains two pixels. The second pixel is moved into this active pixel position
by shifting the contents of the register right by four bits, on the rising edge of
CLK.

24
64 Colors mode
The next byte of data will be loaded into the register on the rising edge
of the external system clock signal (CLK). In this mode, the read of pixel data
does not depend on the status of the hvcnt signal received from the
Synchronization Unit.

9.3 The RGB register (RGBREG)

The RGB register is used to store the six bits that are required for
driving the red, green and blue color guns of the target monitor. When the
chosen color palette is either Black & White or 16 Colors, these six bits are
obtained by mapping the value of the active pixel to a predefined RGB code.
When the chosen color palette is 64 Colors, the actual pixel value is used
directly.
The register, RGBREG, is reset to zero (000000) when the VGA
Controller receives an external reset signal (RST). This RGB code represents
black.
The register is updated on each rising edge of the CLK signal and the
value loaded is dependent on the state of the line display enable signal, en.
When en is Low, blanking is required and RGBREG is loaded with the code
for black (000000).
Table 2 illustrates the mapping of a 1-bit pixel (Black & White mode)
and a 4-bit pixel (16 Colors mode) into the required RGB color code.

25
26
27
The RGB color code stored in the RGB register is output from the VGA
Controller as separate 2-bit R, G and B values (outputs R0, R1, G0, G1, B0
and B1).
The monitor itself expects analog signals as inputs to its electron gun control
circuits. This is achieved by using 2-bit digital to analog converter circuitry,
located on the Nano Board itself, as shown in Figure 4.

Figure 9.1. Digital to Analog RGB conversion

28
 For each color, the 2-bit digital signal from the VGA Controller can be
converted into 4 distinct analog levels. These levels specify the intensity of
each of the three primary colors to use when displaying the pixel on the
monitor’s screen. The levels range from 0V (total darkness) to 0.7V (maximum
brightness).
With each analog input being one of four possible levels, the monitor
can display each pixel on the screen with one of 64 different color
permutations.

Using Block RAM in Spartan-3E Generation

FPGAs

For applications requiring large, on-chip memories, Spartan™-3

Generation FPGAs provides plentiful, efficient Select RAM™ memory blocks.
Using various configuration options, Select RAM blocks create RAM, ROM,
FIFOs, large look-up tables, data width converters,circular buffers, and shift
registers, each supporting various data widths and depths. This application note
describes the features and capabilities of block Select RAM and illustrates how
to specify the various options using the Xilinx CORE Generator™ system or
via VHDL or Verilog instantiation.

29
Table 2: Block RAM Available in Spartan-3E Devices

Devi R R T T T
ce A A o o o
M M t t t
Co Bl a a a
lu oc l l l
m ks R R R
ns pe A A A
r M M M
C B B K
ol l it b
u o s i
m c t
n k s
s
XC3 1 4 4 7 7
S100 3 2
E 7
2
8
XC3 2 6 1 2 2
S250 2 2 1
E 1 6
1
8
4
XC3 2 10 2 3 3
S500 0 6 6
E 8 0
6
4
0

30
XC3 2 14 2 5 5
S120 8 1 0
0E 6 4
0
9
6
XC3 2 18 3 6 6
S160 6 6 4
0E 3 8
5
5
2

Each block RAM contains 18,432 bits of fast static RAM, 16K bits of
which is allocated to data storage and, in some memory configurations, an
additional 2K bits allocated to parity or additional "plus" data bits. Physically,
the block RAM memory has two completely independent access ports, labeled
Port A and Port B. The structure is fully symmetrical, and both ports are
interchangeable and both ports support data read and write operations. Each
memory port is synchronous, with its own clock, clock enable, and write
enable. Read operations are also synchronous and require a clock edge and
clock enable. Though physically a dual-port memory, block RAM simulates
single-port memory in an application, as shown in Figure 1. Furthermore, each
block memory supports multiple configurations or aspect ratios. Table 3
summarizes the essential SelectRAM features. Cascade multiple block RAMs
to create deeper and wider memory organizations, with a minimal timing
penalty incurred through specialized routing resources.

31
32
 10.HARDWARE DESCRIPTIVE LANGUAGE (VHDL)

Why (V) HDL?

• Interoperability
• Technology independence
• Design reuse
• Several levels of abstraction
• Readability
• Standard language
• Widely supported

What is VHDL?

VHDL = VHSIC Hardware Description Language(VHSIC = Very High-Speed

IC)

Design specification language

Design entry language
Design simulation language
Design documentation language
An alternative to schematics

10.1 Brief History:

• VHDL Was developed in the early 1980s for managing design

problems that involved large circuits and multiple teams of engineers.
• Funded by U.S. Department of Defence.

33
 • The first publicly available version was released in 1985.
• In 1986 IEEE (Institute of Electrical and Electronics Engineers, Inc.)
was presented with a proposal to standardize the VHDL.
• In 1987 standardization => IEEE 1076-1987
• An improved version of the language was released in 1994 => IEEE
standard1076-1993.

10.2 Related Standards:

• IEEE 1076 doesn’t support simulation conditions such as unknown and high-
impedance.
• Soon after IEEE 1076-1987 was released, simulator companies began using
their own, non-standard types => VHDL was becoming a nonstandard.
• IEEE 1164 standard was developed by an IEEE.�IEEE 1164 contains
definitions for a nine-valued data type, std_logic.
• IEEE 1076.3 (Numeric or Synthesis Standard) defines data types as they relate
to actual hardware.
• Defines, e.g., two numeric types: signed and unsigned.

VHDL Environment:

34
 Design Units:

Segments of VHDL code that can be compiled separately and stored in a

library.

Entities:
• A black box with interface definition.
• Defines the inputs/outputs of a component (define pins)
• A way to represent modularity in VHDL.
• Similar to symbol in schematic.
• Entity declaration describes entity.
Eg:
entity Comparator is
port (A, B : in std_logic_vector(7 downto0);
EQ : out std_logic);
end Comparator;
Ports:
• Provide channels of communication between the component and its
environment.
• Each port must have a name, direction and a type.

35
 • An entity may have NO port declaration
Port directions:
• In: A value of a port can be read inside the component, but cannot be
assigned. Multiple reads of port are allowed.
• Out: Assignments can be made to a port, but data from a port cannot be
read. Multiple assignments are allowed.
• In out: Bi-directional, assignments can be made and data can be read.
Multiple assignments are allowed.
• Buffer: An out port with read capability. May have at most one
assignment. (are not recommended)

Architectures:
• Every entity has at least one architecture.
• One entity can have several architectures.
• Architectures can describe design using:
Behavior–Structure–Dataflow
• Architectures can describe design on many levels–Gate level–RTL (Register
Transfer Level)–Behavioral level
• Configuration declaration links architecture to entity.
Eg:
Architecture Comparator1 of Comparator is
Begin
EQ <= ’1’when (A=B) else ’0’;
End Comparator1;

Configurations:
• Links entity declaration and architecture body together.
• Concept of default configuration is a bit messy in VHDL ‘87.
–Last architecture analyzed links to entity?
• Can be used to change simulation behavior without re-analyzing the VHDL
source.

36
 • Complex configuration declarations are ignored in synthesis.
• Some entities can have, e.g.,gate level architecture and behavioral
architecture.
• Are always optional.

Packages:
Packages contain information common to many design units.
1. Package declaration

--constant declarations
–type and subtype declarations
–function and procedure declarations
–global signal declarations
–file declarations
–component declarations

2. Package body

–is not necessary needed

–function bodies
–procedure bodies

• Packages are meant for encapsuling data which can be shared globally among
Several design units.
Consists of declaration part and optional body part.
Package declaration can contain:
–type and subtype declarations
–subprograms
–constants,
Alias declarations
–global signal declarations
–file declarations

37
 –component declarations
Package body consists of
–subprogram declarations and bodies
–type and subtype declarations
– deferred constants
– file declarations

Libraries:
Collection of VHDL design units (database).
1. Packages:
• package declaration
• package body
2. Entities (entity declaration)
3. Architectures (architecture body)
4. Configurations (configuration declarations)
• Usually directory in UNIX file system.
• Can be also any other kind of database.
Levels of Abstraction:

VHDL supports many possible styles of design description, which differ

primarily in how closely they relate to the HW.
It is possible to describe a circuit in a number of ways.
• Structural-------
• Dataflow ------- Higher level of abstraction
• Behavioral -------
Structural VHDL description:

• Circuit is described in terms of its components.

• From a low-level description (e.g., transistor-level description) to a high level
description (e.g., block diagram).
• For large circuits, a low-level description quickly becomes impractical.

38
 10.3 Dataflow VHDL Description:

• Circuit is described in terms of how data moves through the system.

• In the dataflow style you describe how information flows between registers in
the system.
• The combinational logic is described at a relatively high level, the placement
and operation of registers is specified quite precisely.

• The behavior of the system over the time is defined by registers.

• There are no build-in registers in VHDL-language.

–Either lower level description
–or behavioral description of sequential elements is needed.
• The lower level register descriptions must be created or obtained.
• If there is no 3rd party models for registers => you must write the behavioral
description of registers.
• The behavioral description can be provided in the form of
subprograms(functions or procedures)

39
 10.4 Behavioral VHDL Description:

• Circuit is described in terms of its operation over time.

• Representation might include, e.g., state diagrams, timing diagrams and
algorithmic descriptions.
• The concept of time may be expressed precisely using delays (e.g., A <= B
after 10 ns)
• If no actual delay is used, order of sequential operations is defined.
• In the lower levels of abstraction (e.g., RTL) synthesis tools ignore detailed
timing specifications.
• The actual timing results depend on implementation technology and efficiency
of synthesis tool.
• There are a few tools for behavioral synthesis.
Concurrent Vs Sequential:

Processes:

• Basic simulation concept in VHDL.

• VHDL description can always be broken up to interconnected processes.

40
• Quite similar to Unix process.

• Process keyword in VHDL.

• Process statement is concurrent statement.

• Statements inside process statements are sequential statements.
• Process must contain either sensitivity list or wait statement(s), but NOT both.
• Sensitivity list or wait statement(s) contains signals which wakes process up.
General format:
Process [(sensitivity_list)]
process_declarative_part
Begin
process_statements
[wait_statement]
End process;

41
 11. VGA CONTROLLER CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga_controller is port(clk50m:in std_logic;

rstn:in std_logic;
hsync:out std_logic;
vsync:out std_logic;
red:out std_logic_vector(0 downto 0);
green:out std_logic_vector(0 downto 0);
blue:out std_logic_vector(0 downto 0));
end vga_controller;

architecture Behavioral of vga_controller is

component memory
port (
addr: IN std_logic_VECTOR(17 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(0 downto 0);
en: IN std_logic;

42
 sinit: IN std_logic);
END component;

component sync_unit port(

clk:in std_logic;
rstn:in std_logic;
hsync:out std_logic;
---horizontal synch pulse(row)
vsync:out std_logic;
--vertical sync pulse(frame) ///111110100000000000
v_en_reg:out std_logic;
h_en:out std_logic;
v_en:out std_logic;
line_count:inout integer;
c_hs:inout integer);
end component;

component pixelgen port(

clk:in std_logic;
rstn:in std_logic;
hsync:in std_logic;
vsync:in std_logic;
h_en:in std_logic;
v_en:in std_logic;
v_en_reg: in std_logic;
data_in:in std_logic_vector(0 downto 0);
line_count:in integer;
c_hs:in integer;
red: out std_logic_vector(0 downto 0);
green:out std_logic_vector(0 downto 0);
blue:out std_logic_vector(0 downto 0);
addr:out std_logic_vector(17 downto 0);

43
 rd:out std_logic);
end component;

signal clk,hsync_s,vsync_s,h_en_s,v_en_s,v_en_reg_s,rd_s:std_logic;
signal line_count_s,c_hs_s,addr:integer;
signal data_s:std_logic_vector(0 downto 0);
signal addr_s:std_logic_vector(17 downto 0);

begin
--addr_s <= std_logic_vector(to_unsigned(addr,18));

process(clk50m,rstn)
begin
if(rstn = '0')then
clk <= '0';
elsif(clk50m = '1' and clk50m'event)then
clk <= not clk;
end if;
--end if;
end process;
hsync <= hsync_s;
vsync <= vsync_s;
sync: sync_unit port map(
clk => clk,
rstn => rstn,
hsync => hsync_s,
vsync => vsync_s,
v_en_reg => v_en_reg_s,
line_count => line_count_s,
h_en => h_en_s,
v_en => v_en_s,

44
 c_hs => c_hs_s

);

pixel: pixelgen port map(

clk => clk,
rstn => rstn,
hsync => hsync_s,
vsync => vsync_s,
h_en => h_en_s,
v_en => v_en_s,
v_en_reg => v_en_reg_s,
data_in => data_s,
line_count=> line_count_s,
c_hs => c_hs_s,
red => red,
green => green,
blue => blue,
addr => addr_s,
rd => rd_s
);

mem12: memory port map(

addr => addr_s,
clk => clk,
dout => data_s,
en => rd_s,
sinit=> rstn
);

45
end Behavioral;

SYNCHRONIZATION BLOCK CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync_unit is port(

clk:in std_logic;
rstn:in std_logic;
hsync:out std_logic; ---horizontal synch pulse(row)
vsync:out std_logic; --vertical sync
pulse(frame) ///111110100000000000
v_en_reg:out std_logic;
h_en:out std_logic;
v_en:out std_logic;
line_count:out integer;
c_hs:out integer );
end sync_unit;

architecture arch_sync_unit of sync_unit is

signal h_en_s,v_en_s:std_logic;
signal line_count_s,c_hs_s:integer;
begin
c_hs <= c_hs_s;
line_count <= line_count_s;
h_en <= h_en_s;
v_en <= v_en_s;

-- hsync counter

46
process(clk,rstn)
begin
if(rstn = '0')then
c_hs_s <= 0;
else
if(clk = '1' and clk'event)then
if(c_hs_s=793)then
c_hs_s <= 0;
else
c_hs_s <= c_hs_s +1;
end if;
end if;
end if;
end process;

--vsync counter
--vertical line counter
process(h_en_s,rstn)
begin
if(rstn = '0')then
line_count_s <= 0;
elsif(h_en_s = '1' and h_en_s'event)then
line_count_s <= line_count_s + 1;
if (line_count_s=515)then
line_count_s <= 0;
end if;
end if;
--end if;
end process;

--hysnc pulse

47
process(clk,rstn)
begin
if(rstn = '0')then
hsync <= '1';
elsif(clk = '1' and clk'event)then
if(c_hs_s <=95)then
hsync <= '0';
else
hsync <= '1';
end if;
end if;
--end if;
end process;

process(clk,rstn) ----Horizontal Enable ( Row Information Will be Sent in

this period)
begin
if(rstn = '0')then
h_en_s <= '0';
elsif(clk = '1' and clk'event)then
if((c_hs_s >=143) and (c_hs_s<=778))then
h_en_s <= '1';
else
h_en_s <= '0';
end if;
end if;
--end if;
end process;

---vysnc pulse
process(clk,rstn) -- Vertical Enable (Data is Valid in this Region)

48
begin

if(rstn = '0')then
v_en_s <= '0';
elsif(clk = '1' and clk'event)then
if((line_count_s>=35 and line_count_s<=515))then
v_en_s <= '1';
else
v_en_s <= '0';
end if;
end if;
--end if;
end process;

process(clk,rstn) --Vertical Sync, Front porch, Back Porch

begin
if(rstn = '0')then
vsync <= '1';
elsif(clk = '1' and clk'event)then
if(line_count_s <2)then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
--end if;
end process;

process(clk)
begin
if(clk = '1' and clk'event)then
v_en_reg<=v_en_s;

49
 end if;
end process;
end arch_sync_unit;
PIXEL GENERATOR:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pixelgen is port(

clk:in std_logic;
rstn:in std_logic;
hsync:in std_logic;
vsync:in std_logic;
h_en:in std_logic;
v_en:in std_logic;
v_en_reg: in std_logic;
data_in:in std_logic_vector(0 downto 0);
line_count:in integer;
c_hs:in integer;
red: out std_logic_vector(0 downto 0);
green:out std_logic_vector(0 downto 0);
blue:out std_logic_vector(0 downto 0);
addr:out std_logic_vector(17 downto 0);
rd:out std_logic
);
end pixelgen;

architecture behv of pixelgen is

signal addr_s:std_logic_vector(17 downto 0);
begin

50
addr <= addr_s;
process(clk,rstn)
begin

if(rstn = '0')then
rd <= '0';
red <= "0";
green <= "0";
blue <= "0";
addr_s <= x"0000" & "00";
elsif (clk = '1' and clk'event)then
if((v_en='1') and (v_en_reg='0'))then
addr_s<=(others =>'0');
end if;
if(v_en='1' and h_en='1')then
if(line_count<=514)then
if(c_hs <= 655)then

rd <= '1';
red <= data_in;
green <= data_in;
blue <= data_in;
addr_s <=addr_s +"000000000000000001";

else
rd <= '0';
red <= "0";
green <= "1";
blue <= "0";
end if;
else
rd <= '0';
red <= "1";

51
 green <= "1";
blue <= "1";
end if;
if(addr_s="111011111111111111")then
addr_s<= (others =>'0');
end if;
else
red <= "0";
green <= "0";
blue <= "0";
end if;
end if;
-- end if;
--end if;
end process;
end behv;

52
 12. FPGA ARCHITECTURE

A field-programmable gate array (FPGA) is a semiconductor device that can

be configured by the customer or designer after manufacturing—hence the
name "field-programmable". FPGAs are programmed using a logic circuit
diagram or a source code in a hardware description language (HDL) to specify
how the chip will work. They can be used to implement any logical function
that an application-specific integrated circuit (ASIC) could perform, but the
ability to update the functionality after shipping offers advantages for many
applications.

FPGAs contain programmable logic components called "logic blocks", and a

hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"—somewhat like a one-chip programmable breadboard. Logic blocks
can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, the logic blocks also
include memory elements, which may be simple flip-flops or more complete
blocks of memory.

History: The FPGA industry sprouted from programmable read only

memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs
both had the option of being programmed in batches in a factory or in the field
(field programmable), however programmable logic was hard-wired between
logic gates.

Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the

first commercially viable field programmable gate array in 1985 – the
XC2064. The XC2064 had programmable gates and programmable
interconnects between gates, the beginnings of a new technology and market.
The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-

53
input lookup tables (LUTs). More than 20 years later, Freeman was entered
into the National Inventor's Hall of Fame for his invention.

Some of the industry’s foundational concepts and technologies for

programmable logic arrays, gates, and logic blocks are founded in patents
awarded to David W. Page and LuVerne R. Peterson in 1985.

In the late 1980s the Naval Surface Warfare Department funded an experiment
proposed by Steve Casselman to develop a computer that would implement
600,000 reprogrammable gates. Casselman was successful and the system was
awarded a patent in 1992.

Xilinx continued unchallenged and quickly growing from 1985 to the mid-
1990s, when competitors sprouted up, eroding significant market-share. By
1993, Actel was serving about 18 percent of the market.

The 1990s were an explosive period of time for FPGAs, both in sophistication
and the volume of production. In the early 1990s, FPGAs were primarily used
in telecommunications and networking. By the end of the decade, FPGAs
found their way into consumer, automotive, and industrial applications.

FPGAs got a glimpse of fame in 1997, when Adrian Thompson merged genetic
algorithm technology and FPGAs to create a sound recognition device.
Thomson’s algorithm allowed an array of 64 x 64 cells in a Xilinx FPGA chip
to decide the configuration needed to accomplish a sound recognition task.

12.1 Modern developments

A recent trend has been to take the coarse-grained architectural

approach a step further by combining the logic blocks and interconnects of
traditional FPGAs with embedded microprocessors and related peripherals to
form a complete "system on a programmable chip". This work mirrors the
architecture by Ron Perlof and Hana Potash of Burroughs Advanced Systems
Group which combined a reconfigurable CPU architecture on a single chip

54
 called the SB24. That work was done in 1982. Examples of such hybrid
technologies can be found in the Xilinx Virtex-II PRO and Virtex-4 devices,
which include one or more PowerPC processors embedded within the FPGA's
logic fabric. The Atmel FPSLIC is another such device, which uses an AVR
processor in combination with Atmel's programmable logic architecture.

An alternate approach to using hard-macro processors is to make use of "soft"

processor cores that are implemented within the FPGA logic. (See "Soft
processors" below).

As previously mentioned, many modern FPGAs have the ability to be

reprogrammed at "run time," and this is leading to the idea of reconfigurable
computing or reconfigurable systems — CPUs that reconfigure themselves to
suit the task at hand. The Mitrion Virtual Processor from Mitrionics is an
example of a reconfigurable soft processor, implemented on FPGAs. However,
it does not support dynamic reconfiguration at runtime, but instead adapts itself
to a specific program.

Additionally, new, non-FPGA architectures are beginning to emerge.

Software-configurable microprocessors such as the Stretch S5000 adopt a
hybrid approach by providing an array of processor cores and FPGA-like
programmable cores on the same chip.

Gates

• 1987: 9,000 gates, Xilinx

• 1992: 600,000, Naval Surface Warfare Department
• Early 2000s: Millions

Market size

• 1985: First commercial FPGA technology invented by Xilinx

• 1987: $14 million
• ~1993: >$385 million

55
• 2005: $1.9 billion
• 2010 estimates: $2.75 billion

12.2 FPGA Comparisons

Historically, FPGAs have been slower, less energy efficient and generally
achieved less functionality than their fixed ASIC counterparts. A combination
of volume, fabrication improvements, research and development, and the I/O
capabilities of new supercomputers have largely closed the performance gap
between ASICs and FPGAs.

Advantages include a shorter time to market, ability to re-program in the field

to fix bugs, and lower non-recurring engineering costs. Vendors can also take a
middle road by developing their hardware on ordinary FPGAs, but
manufacture their final version so it can no longer be modified after the design
has been committed.

Xilinx claims that several market and technology dynamics are changing the
ASIC/FPGA paradigm:

• IC costs are rising aggressively

• ASIC complexity has bolstered development time and costs
• R&D resources and headcount is decreasing
• Revenue losses for slow time-to-market are increasing
• Financial constraints in a poor economy are driving low-cost technologies

These trends make FPGAs a better alternative than ASICs for a growing
number of higher-volume applications than they have been historically used
for, which the company blames for the growing number of FPGA design starts
(see History).

56
The primary differences between CPLDs and FPGAs are architectural. A
CPLD has a somewhat restrictive structure consisting of one or more
programmable sum-of-products logic arrays feeding a relatively small number
of clocked registers. The result of this is less flexibility, with the advantage of
more predictable timing delays and a higher logic-to-interconnect ratio. The
FPGA architectures, on the other hand, are dominated by interconnect. This
makes them far more flexible (in terms of the range of designs that are
practical for implementation within them) but also far more complex to design
for.

Another notable difference between CPLDs and FPGAs is the presence in most
FPGAs of higher-level embedded functions (such as adders and multipliers)
and embedded memories, as well as to have logic blocks implement decoders
or mathematical functions.

Some FPGAs have the capability of partial re-configuration that lets one
portion of the device be re-programmed while other portions continue running.

12.3 Applications:

Applications of FPGAs include digital signal processing, software-defined

radio, aerospace and defense systems, ASIC prototyping, medical imaging,
computer vision, speech recognition, cryptography, bioinformatics, computer
hardware emulation, radio astronomy and a growing range of other areas.

FPGAs originally began as competitors to CPLDs and competed in a similar

space, that of glue logic for PCBs. As their size, capabilities, and speed
increased, they began to take over larger and larger functions to the state where
some are now marketed as full systems on chips (SoC). Particularly with the
introduction of dedicated multipliers into FPGA architectures in the late 1990s,
applications, which had traditionally been the sole reserve of DSPs, began to
incorporate FPGAs instead.

57
FPGAs especially find applications in any area or algorithm that can make use
of the massive parallelism offered by their architecture. One such area is code
breaking, in particular brute-force attack, of cryptographic algorithms.

FPGAs are increasingly used in conventional high performance computing

applications where computational kernels such as FFT or Convolution are
performed on the FPGA instead of a microprocessor.

The inherent parallelism of the logic resources on an FPGA allows for

considerable computational throughput even at a low MHz clock rates. The
flexibility of the FPGA allows for even higher performance by trading off
precision and range in the number format for an increased number of parallel
arithmetic units. This has driven a new type of processing called
reconfigurable computing, where time intensive tasks are offloaded from
software to FPGAs.

The adoption of FPGAs in high performance computing is currently limited by

the complexity of FPGA design compared to conventional software and the
extremely long turn-around times of current design tools, where 4-8 hours wait
is necessary after even minor changes to the source code.

Traditionally, FPGAs have been reserved for specific vertical applications

where the volume of production is small. For these low-volume applications,
the premium that companies pay in hardware costs per unit for a
programmable chip is more affordable than the development resources spent
on creating an ASIC for a low-volume application. Today, new cost and
performance dynamics have broadened the range of viable applications.

Architecture :

The most common FPGA architecture consists of an array of configurable

logic blocks (CLBs), I/O pads, and routing channels. Generally, all the routing
channels have the same width (number of wires). Multiple I/O pads may fit
into the height of one row or the width of one column in the array.

58
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs and I/Os required is easily determined from the
design, the number of routing tracks needed may vary considerably even
among designs with the same amount of logic. (For example, a crossbar switch
requires much more routing than a systolic array with the same gate count.)
Since unused routing tracks increase the cost (and decrease the performance)
of the part without providing any benefit, FPGA manufacturers try to provide
just enough tracks so that most designs that will fit in terms of LUTs and IOs
can be routed. This is determined by estimates such as those derived from
Rent's rule or by experiments with existing designs.

The FPGA is an array or island-style FPGA. It consists of an array of logic

blocks and routing channels. Two I/O pads fit into the height of one row or the
width of one column, as shown below. All the routing channels have the same
width (number of wires).
12.1 FPGA structure

A classic FPGA logic block consists of a 4-input lookup table (LUT), and a
flip-flop, as shown below. In recent years, manufacturers have started moving
to 6-input LUTs in their high performance parts, claiming increased
performance.

59
 Typical logic block

There is only one output, which can be either the registered or the unregistered
LUT output. The logic block has four inputs for the LUT and a clock input.
Since clock signals (and often other high-fanout signals) are normally routed
via special-purpose dedicated routing networks in commercial FPGAs, they
and other signals are separately managed.

For this example architecture, the locations of the FPGA logic block pins are
shown below.

Logic Block Pin Locations

Each input is accessible from one side of the logic block, while the output pin
can connect to routing wires in both the channel to the right and the channel
below the logic block.

Each logic block output pin can connect to any of the wiring segments in the
channels adjacent to it.

60
Similarly, an I/O pad can connect to any one of the wiring segments in the
channel adjacent to it. For example, an I/O pad at the top of the chip can
connect to any of the W wires (where W is the channel width) in the horizontal
channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment
spans only one logic block before it terminates in a switch box. By turning on
some of the programmable switches within a switch box, longer paths can be
constructed. For higher speed interconnect, some FPGA architectures use
longer routing lines that span multiple logic blocks.

Whenever a vertical and a horizontal channel intersect, there is a switch box. In

this architecture, when a wire enters a switch box, there are three
programmable switches that allow it to connect to three other wires in adjacent
channel segments. The pattern, or topology, of switches used in this
architecture is the planar or domain-based switch box topology. In this switch
box topology, a wire in track number one connects only to wires in track
number one in adjacent channel segments, wires in track number 2 connect
only to other wires in track number 2 and so on. The figure below illustrates
the connections in a switch box.

Switch box topology

61
Modern FPGA families expand upon the above capabilities to include higher
level functionality fixed into the silicon. Having these common functions
embedded into the silicon reduces the area required and gives those functions
increased speed compared to building them from primitives. Examples of these
include multipliers, generic DSP blocks, embedded processors, high speed IO
logic and embedded memories.

FPGAs are also widely used for systems validation including pre-silicon
validation, post-silicon validation, and firmware development. This allows chip
companies to validate their design before the chip is produced in the factory,
reducing the time to market.

12.4 FPGA Design and Programming :

To define the behavior of the FPGA, the user provides a hardware description
language (HDL) or a schematic design. The HDL form might be easier to work
with when handling large structures because it's possible to just specify them
numerically rather than having to draw every piece by hand. On the other hand,
schematic entry can allow for easier visualisation of a design.

Then, using an electronic design automation tool, a technology-mapped netlist

is generated. The netlist can then be fitted to the actual FPGA architecture
using a process called place-and-route, usually performed by the FPGA
company's proprietary place-and-route software. The user will validate the
map, place and route results via timing analysis, simulation, and other
verification methodologies. Once the design and validation process is
complete, the binary file generated (also using the FPGA company's
proprietary software) is used to (re)configure the FPGA.

Going from schematic/HDL source files to actual configuration: The source

files are fed to a software suite from the FPGA/CPLD vendor that through
different steps will produce a file. This file is then transferred to the

62
 FPGA/CPLD via a serial interface (JTAG) or to an external memory device
like an EEPROM.

The most common HDLs are VHDL and Verilog, although in an attempt to
reduce the complexity of designing in HDLs, which have been compared to the
equivalent of assembly languages, there are moves to raise the abstraction level
through the introduction of alternative languages.

To simplify the design of complex systems in FPGAs, there exist libraries of

predefined complex functions and circuits that have been tested and optimized
to speed up the design process. These predefined circuits are commonly called
IP cores, and are available from FPGA vendors and third-party IP suppliers
(rarely free, and typically released under proprietary licenses). Other
predefined circuits are available from developer communities such as Open
Cores (typically free, and released under the GPL, BSD or similar license), and
other sources.

In a typical design flow, an FPGA application developer will simulate the

design at multiple stages throughout the design process. Initially the RTL
description in VHDL or Verilog is simulated by creating test benches to
simulate the system and observe results. Then, after the synthesis engine has
mapped the design to a netlist, the netlist is translated to a gate level
description where simulation is repeated to confirm the synthesis proceeded
without errors. Finally the design is laid out in the FPGA at which point
propagation delays can be added and the simulation run again with these
values back-annotated onto the netlist.

Basic Process Technology Types :

• SRAM - based on static memory technology. In-system programmable and re-

programmable. Requires external boot devices. CMOS.
• Antifuse - One-time programmable. CMOS.

63
• EPROM - Erasable Programmable Read-Only Memory technology. Usually
one-time programmable in production because of plastic packaging. Windowed
devices can be erased with ultraviolet (UV) light. CMOS.
• EEPROM - Electrically Erasable Programmable Read-Only Memory
technology. Can be erased, even in plastic packages. Some, but not all, EEPROM
devices can be in-system programmed. CMOS.
• Flash - Flash-erase EPROM technology. Can be erased, even in plastic
packages. Some, but not all, flash devices can be in-system programmed. Usually, a
flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive
to manufacture. CMOS.
• Fuse - One-time programmable. Bipolar.

Major Manufacturers :

Xilinx and Altera are the current FPGA market leaders and long-time industry
rivals. Together, they control over 80 percent of the market, with Xilinx alone
representing over 50 percent.

Xilinx also provides free Windows and Linux design software, while Altera
provides free Windows tools; the Solaris and Linux tools are only available via
a rental scheme.

Other competitors include Lattice Semiconductor (flash, SRAM), Actel

(antifuse, flash-based, mixed-signal), SiliconBlue Technologies (low power),
Achronix (RAM based, 1.5GHz fabric speed), and QuickLogic (handheld
focused CSSP, no general purpose FPGAs!).

12.5 FPGA prototype :

FPGA prototyping, sometimes also referred to as ASIC prototyping or SoC

prototyping is the method to prototype SoC and ASIC design on FPGA for
hardware verification and early software development.

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 Main stream verification methods for hardware design and early software and
firmware co-design has become mainstream. Prototyping SoC and ASIC
design on FPGA has become a good method to do this.

Reasons why Prototyping is important:

1. Running a SoC design on FPGA prototype is a reliable way to ensure that it is

functionally correct. This is compared to designers only relying on software
simulations to verify that their hardware design is sound. Simulation speed and
modeling accuracy limitations hinder this development.
2. Due to time constrains, many projects cannot wait until the silicon is back from
the foundry to start on software tests. FPGA prototyping allows for much more time in
area of software development and testing at the software-hardware integration stage.
This allows many unforeseen software bugs that appear due to today's array of
operating systems, applications, and hardware.
3. Prototyping also allows the developer to ensure that all IP technologies on his
system work well together off the simulation stage and in actual form.
4. Prototyping has the added advantage as demo platforms to SoC clients,
bringing in interest early. This speeds up the overall development cycle and allows for
more enhancement or improvement to the chip features as it would otherwise have
been.

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13. SIMULATION RESULTS

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GATE LEVEL

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Fig:VGA CONTROLLER

GATE LEVEL

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Fig: SYNC UNIT

TECHNOLOGY SCHEMATIC

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 14. APPLICATIONS:

 Motion Tracking Systems.

 Image processing systems.

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 Displaying Systems.

14.1 CONCLUTION

Hence by implementing FPGA, taking a processor-generated picture

(pixilated) from memory space, the Controller provides digital RGB values for
each pixel, as well as horizontal and vertical synchronization signals, in order
to correctly display the picture on a connected monitor.

REFERENCES

1. http://en.wikipedia.org/wiki/Video_Graphics_Array

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2. A VGA display controller by Eduardo Sanchez.

3. Hinner:”VGA Interface and video signal documents”

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