2-bit ripple binary counter using JK

flip flops (asynchronous counters)

1 J K Q(t+1)
0 0 Q(t)
J J
Q0 Q1 0 1 0
CP 1 0 1
1 1 Q’(t)
K K
Q0’ Q1’

CP

Q0’

Q0
0 1 0 1 0

Q1 0 0 1 1 0
 3-bit ripple binary counter using JK
1
flip flops (asynchronous counters)

J J Q1 J
Q0 Q2
CP

K K K
Q0’ Q1’ Q2’

CP

Q0’

Q0

Q1

Q2
Simple Registers
 No external gates.
 Example: A 4-bit register. A new 4-bit data is loaded
on every clock cycle.
A4 A3 A2 A1

Q Q Q Q

D D D D

CP

I4 I3 I2 I1
 (Control Signal) 4-bit register with parallel load
Load

S Q A1
I1
R

S Q A2
I2
R

S Q A3
I3
R

I4 S Q A4

CP
Clear
Register with Parallel Load Using D Flip
Load Flops Load A + Load I
1 1

D Q A1
I1

D Q A2
I2

D Q A3
I3

D Q A4
I4

CP
Clear
Using Registers to implement Sequential
Circuits
• A sequential circuit may consist of a register (memory) and a
combinational circuit.
Next-state value

Clock
Register Combinational
Pulse Circuit
Inputs Outputs

• The external inputs and present states of the register determine

the next states of the register and the external outputs, through
the combinational circuit.
• The combinational circuit may be implemented by any of the
methods covered in MSI components and Programmable
Logic Devices.
 Using Registers to implement
Sequential Circuits
• Example 1: Design a Sequential Circuit whose state table is given below using two flip-flops.
A1+ = ∑ m(4,6) = A1. x'
A2+ = ∑ m(1,2,5,6) = A2.x' + A'2 .x = A2 x
y = ∑ m(3,7) = A2.x

State Table Logic Diagram

Present Next
State Input State Output
A1 A2 x A1+ A2+ y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0 A1 . x’ A1
0 1 1 0 0 1
1 0 0 1 0 0 A2 x A2
1 0 1 0 1 0
1 1 0 1 1 0
y
1 1 1 0 0 1 x

Sequential Circuit Implementation

Using Registers to implement Sequential
Circuits
• Example 2: Repeat example 1, but use a ROM &Register.
Address Outputs
1 2 3 1 2 3
A1 A2 x A1 A 2 y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0 A1 1 1
8X3
0 1 1 0 0 1 2 2
A2
1 0 0 1 0 0 ROM
x 3 3 y
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1
ROM truth table
Sequential circuit using a register and a ROM
 Serial IN/Serial Out Shift Registers
• Accepts data serially – one bit at a time and also
produces output serially.

Serial Input Q0 Q1 Q2 Q3 Serial Output

D Q D Q D Q D Q
(SI) (SO)

CLK

Shift Register
 Serial In/Serial Out Shift Registers
• Application: Serial transfer of data from one register to another.

1011 0010
SI SO SI SO
Shift register A Shift register B
Clock CP
Shift Control

Clock

Shift Control Wordtime

CP
T1 T2 T3 T4
 Serial In/Serial Out Shift Registers
Serial-transfer example.

Timing Pulse Shift Register A Shift Register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1
 Bidirectional Shift Registers
 4-bit bidirectional shift register with parallel load
Parallel outputs

A4 A3 A2 A1

Clear Q Q Q Q
D D D D

CLK

S1 4x1 4x1 4x1 4x1

S0 MUX MUX MUX MUX
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial
input for
Serial
shift-right I4 I3 I2 I1
input for
shift-left
Parallel inputs
 Bidirectional Shift Registers
• 4-bit bidirectional shift register with parallel
load.
Mode Control
s1 s0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
 An Application-Serial Addition
• Most operations in digital computers are done in parallel.
Serial operations are slower but require less equipment.
• A serial adder is shown below. A A+B.

1010
SI
Shift-right SO
Shift register A x S
CP
y FA
SI 0111 z C
External input
SO
Shift register B
Q D

Clear
 Excitation table for a serial adder
Example: Design a serial adder using a sequential logic
procedure
with JK flip-flops. Q(t) Q(t+1) J K
Present Next Flip-flop 0 0 0 X
State Inputs State Output inputs 0 1 1 X
Q x y Q S JQ KQ 1 0 X 1
0 0 0 0 0 0 X 1 1 X 0
0 0 1 0 1 0 X
0 1 0 0 1 0 X
0 1 1 1 0 1 X S=x+y + Q
1 0 0 0 1 X 1
JQ = xy
1 0 1 1 0 X 0
1 1 0 1 0 X 0 KQ = x’y’ =(x+y)’
1 1 1 1 1 X 0
 SO=x S
Shift-right Shift register A
CP

External input J Q
Shift register B
SO=y

Clear

S=x+y + Q
JQ = xy
KQ = x’y’ =(x+y)’
Second form of a serial adder
 4-bit binary ripple counter
J K Q(t+1)
0 0 Q(t)
A4 A3 A2 A1
0 1 0
1 0 1
1 1 Q’(t)

1 1 1 1
Q J Q J Q J Q J
To next stage
Count
pulses

K 1 K 1 K 1 K 1
 Count sequence for a binary ripple counter
Count sequence Condition for complementing flip-flops
A4 A3 A2 A1
0 0 0 0 Complement A1
0 0 0 1 Complement A1 A1 will go from 1 to 0 and complement A2
0 0 1 0 Complement A1
0 0 1 1 Complement A1 A1 will go from 1 to 0 and complement A2
A2 will go from 1 to 0 and complement A3
0 1 0 0
Complement A1
0 1 0 1 A1 will go from 1 to 0 and complement A2
Complement A1
0 1 1 0
Complement A1
0 1 1 1
Complement A1 A1 will go from 1 to 0 and complement A2;
A2 will go from 1 to 0 and complement A3;
A3 will go from 1 to 0 and complement A4
1 0 0 0
And so on……
State diagram of a decimal BCD counter

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101

 Logic diagram of a BCD ripple counter
0 0 0 0
Q8 Q4 Q2 Q1

1 0 0 1
1 1
Q J Q J Q J Q J

Count
pulses

1 1 1 1
Q’ K K K K

J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q’(t)
 Timing diagram for the decimal counter
Count
pulses
Q1

Q2 0 1 0 1 0 1 0 1 0 1 0

Q3 0 0 1 1 0 0 1 1 0 0 0

Q4 0 0 0 0 1 1 1 1 0 0 0

Q5 0 0 0 0 0 0 0 0 1 1 0
Block diagram of a 3-decade decimal BCD counter

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

BCD BCD BCD Count

Counter Counter Counter pulses
102 digit 101 digit 100 digit

0-999 0-99 0-9

 4-bit synchronous binary counter
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q’(t)
A4 A3 A2 A1

Q/ Q Q/ Q Q/ Q Q/ Q

K J K J K J K J

CP

To Count
next enable
stage
 T Q(t+1) 4-bit up-down binary counter
0 Q(t)
1 Q’(t) A4 A3 A2 A1

Q/ Q Q/ Q Q/ Q Q/ Q

T T T T

CP

To
Next UP
stage

Down
Design a BCD counter using T flip-flops
Excitation table for a BCD counter
Count Sequence Flip-flop inputs Output Carry
Q8 Q4 Q2 Q1 TQ8 TQ4 TQ2 TQ1 y
0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 1 0
0 0 1 0 0 0 0 1 0
0 0 1 1 0 1 1 1 0
0 1 0 0 0 0 0 1 0
0 1 0 1 0 0 1 1 0
0 1 1 0 0 0 0 1 0
0 1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1 0
1 0 0 1 1 0 0 1 1

Using K-maps, we get Q(t) Q(t+1) T

TQ1 =1
TQ2 = Q/8Q1 0 0 0
TQ4 = Q2Q1
0 1 1
TQ8 = Q8Q1 + Q4Q2Q1
y = Q8Q1 1 0 1
Now logic diagram can be drawn for BCD synchronous
1 1 0
counter
 Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1
T T T T

CP

TQ1 =1
TQ2 = Q/8Q1
TQ4 = Q2Q1
TQ8 = Q8Q1 + Q4Q2Q1
y y = Q8Q1
Counters with Parallel Load
 4-bit counter with Count

parallel load. Load

I1 JQ A1
Clear CP Load Count Function
0 X X X Clear to 0
K
1 X 0 0 No Change
I2 JQ A2
1 1 X Load inputs
1 0 1 Next State K
(counting)

I3 JQ A3
J K Q(t+1) K
0 0 Q(t)
0 1 0 I4 JQ A4
1 0 1 K
1 1 Q’(t)
Clear
CP Carry
out
4-bit binary counter with parallel load
 Counters with Parallel Load
 Different ways of getting a MOD-6 counter
A4 A3 A2 A1 A4 A3 A2 A1

Load Count = 1 Clear Count = 1

Clear = 1 Load = 0
I 4 I 3 I2 I1 CP I 4 I 3 I2 I1 CP
Inputs = 0

(a) Binary states 0,1,2,3,4,5 (b) Binary states 0,1,2,3,4,5

A4 A3 A2 A1 A4 A3 A2 A1
Carry-out
Count = 1 Count = 1
Clear = 1 Load Clear = 1
Load I4 I 3 I2 I 1 I4 I 3 I2 I 1
CP CP

1 0 1 0 0 0 1 1

(c) Binary states 10,11,12,13,14,15 (d) Binary states 3,4,5,6,7,8

 Timing Sequences
Word-time
Start S Q control
CP
R
Stop

Count enable
CP 3-bit counter

(a) Circuit Diagram

CP

Start

Stop

Q
Word-time = 8 pulses

(b) Generation of a word-time control for serial operations

 Shift right
T0 T1 T2 T3

(a) ring-counter (initial value = 1000)

T0 T1 T2 T3
CP

T0
2X4
decoder
T1

Count T2
enable
2-bit counter T3

(b) Counter and Decoder

(c) Sequence of four timing signals
 A B C E
D Q D Q D Q D Q

A/ B/ C/ E/
Q /
Q /
Q / Q /

CP
(a) 4-stage switch tail ring counter

Sequence Flip-flop outputs And gate required

number A B C E for outputs
1 0 0 0 0 A/ E/
2 1 0 0 0 A B/ (b) Count
3 1 1 0 0 B C/
sequence and
4 1 1 1 0 C E/
5 1 1 1 1 AE
required
6 0 1 1 1 A/ B
decoding
7 0 0 1 1 B/ C
8 0 0 0 1 C/ E