Professional Documents
Culture Documents
Nanoprogramming
vs.
M icroprogramming
G. Franco Casaglia
Ing. C. Olivetti & C. S.p.a.
0
as sequential circuits; they are similar to traditional CONTROL z
control structures, taking into account that often
the microinstruction set is as complex as the Figure 2b. Decoder scheme in a vertically microprogrammed
machine language instruction set of a minicom- control
January 1976 55
wherein a machine is said to be microprogrammed if programmed structures. Nevertheless, we want to
and only if the decoding network is combinational. note that residual control has been used together
Chroust also defines it as a formalism by means with vertical microprogramming in order to main-
of which it is possible to evaluate the degree of tain a minimum level of control of the hardware
microprogramming of a system with a continuous resources within each individual microinstruction.
transition from strictly microprogrammed systems This control is not apparent (though its function
to more complex control structures. remains) when we substitute the enabling bits to a
Finally, disregarding some implementation ad- microinstruction bit pattern.
vantages, we can say that in realizing a vertical The flexibility of residual control obviously de-
control structure, as we described above, we have a pends on the number of such setup registers, on the
significant lack of flexibility in CPU resource meaning assigned to their content, and on the way
utilization if the design objective is a machine for chosen to set and select them.
various and different applications supported by the A second attempt to enhance flexibility is repre-
same host hardware machine. sented by the introduction of nanoprogramming; in
the following section we will introduce this technique
by reviewing two significant examples.
Evolution of Vertical Microprogramming
Nanoprogramming
The first attempt, in order to avoid this lack of
flexibility, is realized by introducing the residual Nanodata QM-1 Machine.9' 10, 11 This machine
control technique (see Flynn and Rosin7 for a de- has been designed as an experimental machine to
scription of residual control and the IBM 2025 be implemented and used in order to carry out
CPU8 for an application). Residual control charac- research on microprogramming. Two critical items,
teristics are briefly summarized below. among' a set, by which the machine was evaluated
Much information specified in the microinstruc- before implementation, are (1) flexibility/generality
tion is static-i.e., it represents environmental in- of the instruction set, and (2) flexibility/generality of
formation. The status remains unchanged during addressing.
the execution of a number of microinstructions. If Disregarding the overall architecture, we sum-
this static information and specification are filtered marize the control organization of such a machine
out of the microinstruction and placed in setup as follows (refer to Figure 4): Local store is com-
registers, the combination of a particular field of a posed of 32 registers, one of which (IR) holds a repre-
microinstruction with its corresponding setup regis-
ter would completely define the control for re-
source (Figure 3). This idea is not strictly connected
with vertical microprogramming and can be used
also as a coding technique for horizontally micro-
R CO4TROL
I. CONROL
I~~~~~~~~~~~~~~~~ ATRIWL 0U
SET UP
REGISTER
SELECTION
MECANISM
DECODER Notes
IR -holds a representation of the 16-bit micro-
instruction currently being executed
CIA -COS
busOlD-OS t
address s
DATA PATH CONTROL CID -CS input bus
COD - CS output bus
Figure 3. Residual control scheme Figure 4. Control structure of the QM-1 machine
56 COMPUTER
sentation of the 16-bit microinstruction currently with the operation code, and A, B are the two address
being executed. Control store (CS) consists of 2K parts of the microinstruction pointing to registers.
16-bit words storage; the basic instruction format 'This microinstruction (M,) can be executed in four
of these words is usually a 6-bit op code and two steps (Slp is the first of the four steps defined
5-bit address parts. Nanostore consists of 256 by the pth nanoword):
(expandable to 2K) 342-bit words of memory.
The microinstruction fetching phase is composed
Sip: move
move A toIALU left-side input bus,
B to ALU right-side input bus,
of the following steps: (1) Add one to the 16-bit increment the register containing the micro-
value in the local storage word whose address is instruction buffer;
in CIA. (2) Move that value into the control store S2p: move B to ALU output bus, initiate the
address register and fetch a word which will be microinstruction fetching phase;
used as a microinstruction. (3) Use the 6-bit op code
field of the microinstruction which has been fetched S3p: fill the ALU hold register;
to fetch a 342-bit word from nanostore. S4p: gate the ALU hold register;
Now we consider nanoinstruction sequencing and STOP
control structure. A 342-bit word contains four
nanoinstructions. Each nanoword contains a nano-
program branch address; therefore a nanoprogram CII MITRA 15 Machine.'2 In order to produce a
can span more than one word of nanostore and can small general-purpose computer, whose main charac-
contain loops. The selection of the next nanoword teristics, in addition to a good price/performance
to be processed in QM-1 is also determined, in part, ratio, have to be flexibility and modularity, CII
by the interrupt status of the system. designed a microprogrammed general processing
As an example of the complexity of one of the unit to be used to realize the CPU, various indepen-
four steps defined by a nanoword and of the com- dent I/O external processing units, and special
plexity of a microinstruction, consider the micro- complex operations.
ins'truction (see Figure 5.) "ADD register [A] to This general processing unit has been implemented
register [B]" where the ADD operation is defined using two levels of microprogramming. The first
level is held in a 16-bit word size control store;
the sixteen bits are used as follows:
* memory dialogue control-2 bits
* type of microfunction-5 bits
* general register address-3 bits
[A] [B]
* address of the next microinstruction-6 bits.
The microfunctions are interpreted through a
second level of ROS; the 5 bits are directly used
to address a ROS word whose bits, defining nano-
instructions, are directly used by the operation part
of the computer. The microfunction is translated
from a 5-bit code to a 48-bit word.
ALUx l
Nanoprogramming vs. Microprogramming
hold Reg. l
We want now to compare the microprogrammed
V(5 structures of the Nanodata QM-1 and CII Mitra
15 with a traditional microprogrammed structure:
the 360 control described by Tucker.'3 This control
is schematically shown in Figure 1; an example of
the nature of microoperations, microinstructions,
Notes and microprograms is shown in the following
a, is issued by S1 p or by 0, example (refer to Figure 5).
Let us write a microinstruction to add the comple-
a-2 is issued by S1 p or by 02 ment of register A to register B and put the results
a3 is issued by S2p or by 04 into register B:
a4 is issued by S3p or byO3 M2 Gate register A bit positions 0-31 in comple-
Oa5 is issued by S4p or by 04 ment form to adder left side (01).
Gate register B bit positions 0-31 to adder right
Delay problems are solved in the two examples side (02).
with two different clocking mechanisms. Pass adder output straight through shifter
Figure 5. Schematic ALU structure as used by microinstruc- (03).
tions M1 and M2 Set shifter output into register B (04).
January 1976 57
In microinstruction M, each phase (0, through References
04) defines a microorder; a set of microinstructions 1. R. F. Rosin, "Contemporary Concepts of Microprogram-
like M2 defines a microprogram. A ROS word con- ming and Emulation," Computing Surveys, Vol. 1, No. 4,
tains the bit pattern of a microinstruction including pp. 202, 203, Dec. 1969.
the ROS next address field. 2. R. M. McClure, "Parallelism in Microprogrammed Con-
The model shown in Figure 1, and traditionally trols," in Boulaye and Mermet (eds.) Microprogramming,
called microprogrammed control, is similar to the Hermann, Paris, 1972.
one used to describe the nanostore, the decoders 3. M. J. Flynn, "Interpretation, Microprogramming and the
being similar to those shown in Figure 2a. More Control of a Computer," Palyn Technical Report No.
particularly, the content of avAanoword defines four 104-405, February 1974.
steps, each of which is of the type and complexity
of the microinstruction M, described above. There- 4. A. K. Agrawala and T. G. Rauscher, "Microprogranmuing:
fore we affirm that QM-1 nanoprogramming is Perspective and Status," IEEE Transactions on Com-
puters, Vol. C-23, pp. 817-837, August 1974.
nothing but microprogramming, as originally con-
ceived by Wilkes. 5. G. Chroust, "Microprogramming and Microcontrol, Hard-
ware Definition," Euromicro Newsletter, Vol. 1, No. 1,
pp. 21-27, October 1974.
6. G. F. Casaglia, G. B. Gerace, and M. Vanneschi, "Maximum
Conclusions Computation Speed of Microprogrammed Systems," Proc.,
International Computing Symposium, Venice, Italy, pp.
The introduction of vertical microprogramming 91-99, April 1972.
gave an easy way to implement extensible and modi-
fiable instructions sets, but masked one of the most 7. M. J. Flynn and R. F. Rosin, "Microprogramming:
important characteristics of the original definition: An Introduction and Viewpoint," IEEE Transactions on
Computers, Vol. C-20, pp. 727-731, June 1971.
a flexible and systematic way of hardware resource
management. The first main result of a project such 8 IBM Field Engineering, "Theory of Operation, 2025
as the one started with the design of the QM-1 Processing Unit," IBM Form No. Y24-3527.
machine is, in our opinion, the following: 9. M. W. Cashman, "Microprogramming for the Many,"
Datamation, Vol. 17, No. 21, November 1971.
When it is necessary to maintain flexibility in
organizing the hardware resources of a host 10. R. C. Haavind, "The Many Faces of Microprogramming,"
machine, in order to obtain different systems for ComputerDecisions, September 1971.
different purposes, we have to impl6hient a hori- 11. R. F. Rosin, G. Frieder, and R. Eckhouse, "An Environ-
zontally microprogrammed control using a R/W ment for Research in Microprogramming and Emulation,"
control store. In this situation we also are able CACM, Vol. 15, No. 8, p. 197, August 1972.
to decide, at any time of the overall system
design, at which level particular resource manage- 12. Recoque, "Microprogramming in a Small Computer,"
NATO Advanced Summer School on Microprogramming,
ment algorithms, special instructions, and so on, St. Raphael, France, August 1971.
have to be implemented. In our opinion this is
the level in which it is useful to implement inter- 13. S. G. Tucker, "Microprogram Control for System/360,"
process synchronization primitives and virtual IBM Systems Journal, Vol. 6, No. 4, pp. 224-241, 1967.
address mapping mechanisms. This is the way to 14. V. Lesser, "A Dynamically Reconfigurable Multiple Micro-
be followed in order to eliminate the present rigid processor," Proc., Workshop on Computer Architecture,
boundary among software, firmware, and Grenoble, June 1973.
hardware.
15. M. J. Lutz and M. J. Manthey, "A Microprogrammed
Implementation of a Block Structured Architecture,"
Our results and conclusions do not clarify the Preprints, 5th Workshop on Microprogramming, pp. 28-41,
meaning and the real implication of the intro- September 1972.
duction of a second level of microprogramming
as was done in the QM-1 machine. Why, for example,
is the QM-1 control store not considered as a module
of the main memory? An answer to that question
will probably come from works that deal with the
implementation of block structured architectures."4, 15 gm B kGianfranco
, Casaglia is with ing. C. Olivetti &
Our working approach t& block structured archi- C. S.p.a., Ivrea, Italy. At Olivetti since 1973,
tectures is the following: A computer structure can he is in charge of the definition of the archi-
be seen as level organized; the level boundary and tecture of terminal concentrator systems for
commercial applications. Before joining Oli-
the features contained in each level are defined vetti he did research in the field of micro-
following functional criteria and not following a pre- programming and parallel system organiza-
defined structure. The level "O" is- realized by the tion.
bare machine, the first level is implemented by hori- _ Dr. Casaglia received the Dr. Ing. degree
in electronic engineering from the Universita
zontal microprogramming, and the following level of Pisa, Pisa, Italy, in 1967. He is a member of the IEEE
by software of increasing complexity. The simplest Computer Society, ACM, and the AICA (Associazione Italiana
level of this software can be the one called firmware. per il Calcolo Automatico).
58 COMPUTER