TITLE: Design and implementation of PRBS Generator using VHDL

ABSTRACT: Pseudo random binary sequence is essentially a random sequence of binary

numbers. So PRBS generator is nothing but random binary number generator. It is ‘random’ in a
sense that the value of an element of the sequence is independent of the values of any of
the other elements. It is 'pseudo' because it is deterministic and after N elements it starts
to repeat itself, unlike real random sequences.

The implementation of PRBS generator is based on the linear feedback shift

register(LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0
occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise
one data pattern, and this pattern will repeat itself over time.

In this project, the entire design of the PRBS generator was implemented using
VHDLprogramming language and the simulation were done and tested on the XILINX ISE 9.1i
simulator. A separate program module for D-Flip-Flop was written and this module was
called 16 times in the main program to get the 16-bit shift register. Now the taps 1, 2, 4
and 15 were taken out and XORed together and then was fed back to the first bit as an
input to the shift register. The output to the PRBS generator was taken from all the 16-
bits of the shift register. Thus the output of the PRBS generator cycles between 0 to
65535.

TITLE: Simulation and synthesis of an efficient 32 bit lossless compression

method using VHDL
ABSTRACT: The objective of the project is to design a lossless parallel data compression
system which operates in high-speed to achieve high compression rate. The main parts of
the system are the two Xmatchpro based data compressors in parallel and the control
blocks. Each Data compressor can process four bytes of data into and from a block of data every
clock cycle.
Statistical Methods: Statistical Modeling of lossless data compression system is based on
assigning values to events depending on their probability. The higher the value, the
higher the probability.
Dictionary Methods: Dictionary Methods try to replace a symbol or group of symbols by a
dictionary location code.
In our project we use XMatchPro Algorithm .
TITLE: Design and implementation of different multipliers using VHDL
ABSTRACT: Low power consumption and smaller area are some of the most
important criteria for the fabrication of DSP systems and high performance systems.
Optimizing the speed and area of the multiplier is a major design issue. However,
area and speed are usually conflicting constraints so that improving speed results
mostly in larger areas. In this project we try to determine the best solution to this
problem by comparing a few multipliers.

This project presents an efficient implementation of high speed multiplier using the
shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this
project we compare the working of the three multiplier by implementing each of
them separately in FIR filter.

The parallel multipliers like radix 2 and radix 4 modified booth multiplier does the
Computations using lesser adders and lesser iterative steps. As a result of which
they occupy lesser space as compared to the serial multiplier. This a very important
criteria because in the fabrication of chips and high performance system requires
components which are as small as possible.

In our project when we compare the power consumption of all the multipliers we
find that serial multipliers consume more power. So where power is an important
criterion there we should prefer parallel multipliers like booth multipliers to serial
multipliers. The low power consumption quality of booth multiplier makes it a
preffered choice in designing different circuits.

In this project we first designed three different type of multipliers using shift snd
method, radix 2 and radix 4 modified booth multiplier algorithm. We used different
type of adders like sixteen bit full adder in designing those multiplier. Then we
designed a 4 tap delay FIR filter and in place of the multiplication and additions we
implemented the components of different multipliers and adders. Then we
compared the working of different multipliers by comparing the power consumption
by each of them.

The result of this project helps us to choose a better option between serial and
parallel multiplier in fabricating different systems. Multipliers form one of the most
important component of many systems. So by analyzing the working of different
multipliers helps to frame a better system with less power consumption and lesser
area.
TITLE: Embedded processor design and Implementation of CAM
ABSTRACT: Microprocessors are the heart of all “smart” devices, whether
they be electronic devices or otherwise. Their smartness comes as a direct
result of the decisions and controls that microprocessors make. For example,
we usually do not consider a car to be an electronic device. However, it
certainly has many complex, smart electronic systems, such as the anti-lock
brakes and the fuel-injection system. Each of these systems is controlled by
a microprocessor. Yes, even the black, hardened blob that looks like a dried-
up and pressed-down piece of gum inside a musical greeting card is a
microprocessor.

There are generally two types of microprocessors: general-

purpose microprocessors and dedicated microprocessors. General-purpose
microprocessors, such as the Pentium CPU, can perform different tasks under
the control of software instructions. General-purpose microprocessors are
used in all personal computers. Dedicated microprocessors, also known as
application-specific integrated circuits (ASICs), on the other hand, are
designed to perform just one specific task. For example, inside your cell
phone, there is a dedicated microprocessor that controls its entire operation.
The embedded microprocessor inside the cell phone does nothing else but
controls the operation of the phone. Dedicated microprocessors are,
therefore, usually much smaller than and not as complex as general-purpose
microprocessors. However, they are used in every smart electronic device,
such as the musical greeting cards, electronic toys, TVs, cell phones,
microwave ovens, and anti-lock break systems in your car. From this short
list, I’m sure that you can think of many more devices that have a dedicated
microprocessor inside them. Although the small dedicated microprocessors
are not as powerful as the general-purpose microprocessors, they are being
sold and used in a lot more places than the powerful general-purpose
microprocessors that are used in personal computers.
TITLE: Encryption & decryption of data In GF (13n) field
ABSTRACT: Cryptography is the science of using mathematics to encrypt and decrypt data.
Cryptography enables you to store sensitive information or transmit it across insecure networks
(like the Internet) so that it cannot be read by anyone except the intended recipient.

Cryptographic strength is measured in the time and resources it would require to recover the
plaintext. The result of strong cryptography is cipher text that is very difficult to decipher
without possession of the appropriate decoding tool.

A cryptographic algorithm, or cipher, is a mathematical function used in the encryption and

decryption process. A cryptographic algorithm works in combination with a key — a word,
number, or phrase — to encrypt the plaintext. The same plaintext encrypts to different cipher text
with different keys. The security of encrypted data is entirely dependent on two things: the
strength of the cryptographic algorithm and the secrecy of the key.

With growing dependencies on secure information transfer and data security in this information
age the requirement for a strong method of securing data is always in demand.

In this project , we have tried to device a new means of securing data by encryption and
decryption in GF(13). The reason for using GF(13) is that much research has been done on GF(2)
but the GF(13) field is still mostly untouched. Hence there is much scope for designing versatile
techniques which will be both secure and faster. This will again reduce the probability of
anonymous decryption by undesirable agents. Such technique can be the future of data security
with wide application in every field starting with military application, internet security, wireless
data transfer and many more.
TITLE: Design and implementation of faster and low power multipliers
ABSTRACT: A multiplier is one of the key hardware blocks in most digital and high
performance systems such as FIR filters, digital signal processors and microprocessors etc. With
advances in technology, many researchers have tried and are trying to design multipliers which
offer either of the following- high speed, low power consumption, regularity of layout and hence
less area or even combination of them in multiplier. Thus making them suitable for various high
speed, low power, and compact VLSI implementations. However area and speed are two
conflicting constraints. So improving speed results always in larger areas. So here we try to find
out the best trade off solution among the both of them.

Generally as we know multiplication goes in two basic steps. Partial product and then addition.
Hence in this paper we have first tried to design different adders and compare their speed and
complexity of circuit i.e. the area occupied. And then we have designed Wallace tree multiplier
then followed by Booth’s Wallace multiplier and have compared the speed and Power
consumption in them.

While comparing the adders we found out that Ripple Carry Adder had a smaller area while
having lesser speed, in contrast to which Carry Select Adders are high speed but posses a larger
area. And a Carry Look Ahead Adder is in between the spectrum having a proper trade off
between time and area complexities.

After designing and comparing the adders we turned to multipliers. Initially we went for Parallel
Multiplier and then Wallace Tree Multiplier. In the mean time we learned that delay amount was
considerably reduced when Carry Save Adders were used in Wallace Tree applications. Then we
turned to Booths Multiplier and designed Radix-4 modified booth multiplier and analyzed the
performance of all the multipliers.

After that we turned to different methods of power optimization, of which we could only
complete a few like we went for designing different recoding schemes and their corresponding
partial product generator scheme. After that we designed these recoders and PP generators and
found out the time delays and area covered and power consumed by each scheme. We took into
consideration that since all the PP generators take a huge amount of area we need to go for
simplest of the designs for them and also side by side we need to ensure that we don’t have much
switching actions in the circuit. After this we even modified one of the recoding schemes to
lower the delay and power required by the circuit.

The result of our project helps us to make a proper choice of different multipliers in fabricating
in different arithmetic units as well as making a choice among different adders in different digital
applications according to requirements. All the programs and results have been given in the
following sections.

Further work on Low Power Techniques on different multipliers needs to be done in order to
make us choose a proper multiplier in accordance with the requirements by making the best
possible trade off choice between Speed and Power in different circumstances.
TITLE: Implementation of multi-channel UART controller based on FIFO
technique and FPGA.
ABSTRACT: To meet modern complex control systems communication demands, the
project presents a multi-channel UART controller based on FIFO (First In First Out) technique
and FPGA (Field Programmable Gate Array). The project presents design method of
asynchronous FIFO and structure of the controller. This controller is designed with FIFO circuit
block and UART (Universal Asynchronous Receiver Transmitter) circuit block within FPGA to
implement communication in modern complex control systems quickly and effectively. Form the
communication sequence diagrams; it is easily to know that this controller can be used to
implement communication when master equipment and slaver equipment are set at different
Baud Rate. It also can be used to reduce synchronization error between sub-systems in a system
with several sub-systems. The controller is reconfigurable and scalable.