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Revision 1.2
August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• 54 TSOP(II) Pb-free Package
• RoHS compliant
GENERAL DESCRIPTION
The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. Orgainization Max Freq. Interface Package
K4S280432F-UC(L)75 32M x 4 133MHz LVTTL 54pin TSOP(II)
K4S280832F-UC(L)75 16M x 8 133MHz LVTTL 54pin TSOP(II)
K4S281632F-UC(L)60/75 8M x 16 166MHz LVTTL 54pin TSOP(II)
0~8°C
0.25
TYP
0.010
#54 #28
0.018~0.030
0.45~0.75
0.463±0.008
11.76±0.20
0.400
10.16
#1 #27
( 0.50 )
0.125+0.075
0.020
-0.035
22.62 0.005+0.003
-0.001
MAX
0.891
22.22 ± 0.10 0.21 ± 0.05 1.00 ± 0.10 1.20
0.875 ± 0.004 ± 0.002 ± 0.004
MAX
0.008 0.039 0.047
0.10
MAX
0.004 0.05
+0.10
0.71 0.30 -0.05 0.80 MIN
( ) 0.002
0.028 0.012 +0.004
-0.002
0.0315
I/O Control
LWE
Data Input Register
LDQM
Bank Select
8M x 4 / 4M x 8 / 2M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
8M x 4 / 4M x 8 / 2M x 16
DQi
Address Register
8M x 4 / 4M x 8 / 2M x 16
CLK
8M x 4 / 4M x 8 / 2M x 16
ADD
Column Decoder
LRAS
LCBR
Col. Buffer
LCKE
Programming Register
LRAS LCBR LWE LCAS LWCBR LDQM
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
x16 x8 x4 x4 x8 x16
VDD VDD VDD 1 54 VSS VSS VSS
DQ0 DQ0 N.C 2 53 N.C DQ7 DQ15
VDDQ VDDQ VDDQ 3 52 VSSQ VSSQ VSSQ
DQ1 N.C N.C 4 51 N.C N.C DQ14
DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13
VSSQ VSSQ VSSQ 6 49 VDDQ VDDQ VDDQ
DQ3 N.C N.C 7 48 N.C N.C DQ12
DQ4 DQ2 N.C 8 47 N.C DQ5 DQ11
VDDQ VDDQ VDDQ 9 46 VSSQ VSSQ VSSQ
DQ5 N.C N.C 10 45 N.C N.C DQ10
DQ6 DQ3 DQ1 11 44 DQ2 DQ4 DQ9
VSSQ VSSQ VSSQ 12 43 VDDQ VDDQ VDDQ
DQ7 N.C N.C 13 42 N.C N.C DQ8
VDD VDD VDD 14 41 VSS VSS VSS
LDQM N.C N.C 15 40 N.C/RFU N.C/RFU N.C/RFU
WE WE WE 16 39 DQM DQM UDQM
CAS CAS CAS 17 38 CLK CLK CLK
RAS RAS RAS 18 37 CKE CKE CKE
CS CS CS 19 36 N.C N.C N.C
BA0 BA0 BA0 20 35 A11 A11 A11
BA1 BA1 BA1 21 34 A9 A9 A9
A10/AP A10/AP A10/AP 22 33 A8 A8 A8
A0 A0 A0 23 32 A7 A7 A7
A1 A1 A1 24 31 A6 A6 A6
A2 A2 A2 25 30 A5 A5 A5 54Pin TSOP
A3 A3 A3 26 29 A4 A4 A4 (400mil x 875mil)
VDD VDD VDD 27 28 VSS VSS VSS (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CS Chip select
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE Clock enable CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
A0 ~ A11 Address Row address : RA0 ~ RA11,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
Selects bank to be activated during row address latch time.
BA0 ~ BA1 Bank select address
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
RAS Row address strobe
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
CAS Column address strobe
Enables column access.
Enables write operation and row precharge.
WE Write enable
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
DQM Data input/output mask
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
DQ0 ~ N Data input/output
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
VDDQ/VSSQ Data output power/ground
immunity.
No connection
N.C/RFU This pin is recommended to be left No Connection on the device.
/reserved for future use
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Version
Parameter Symbol Test Condition Unit Note
-75
Burst length = 1
Operating current
ICC1 tRC ≥ tRC(min) 90 mA 1
(One bank active)
IO = 0 mA
Precharge standby current in ICC2P CKE ≤ VIL(max), tCC = 10ns 2
mA
power-down mode ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N 20
Precharge standby current in Input signals are changed one time during 20ns
mA
non power-down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS 10
Input signals are stable
Active standby current in ICC3P CKE ≤ VIL(max), tCC = 10ns 5
mA
power-down mode ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Active standby current in ICC3N 30 mA
Input signals are changed one time during 20ns
non power-down mode
(One bank active) CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS 25 mA
Input signals are stable
Operating current IO = 0 mA
ICC4 110 mA 1
(Burst mode) Page burst
Refresh current ICC5 tRC ≥ tRC(min) 200 mA 2
C 2 mA 3
Self refresh current ICC6 CKE ≤ 0.2V
L 800 uA 4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S2804(08)32F-UC
4. K4S2804(08)32F-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Version
Parameter Symbol Test Condition Unit Note
-60 -75
Burst length = 1
Operating current
ICC1 tRC ≥ tRC(min) 130 100 mA 1
(One bank active)
IO = 0 mA
Precharge standby current in ICC2P CKE ≤ VIL(max), tCC = 10ns 2
mA
power-down mode ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N 20
Precharge standby current in Input signals are changed one time during 20ns
mA
non power-down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS 10
Input signals are stable
Active standby current in ICC3P CKE ≤ VIL(max), tCC = 10ns 5
mA
power-down mode ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Active standby current in ICC3N 30 mA
Input signals are changed one time during 20ns
non power-down mode
(One bank active) CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ 25
ICC3NS mA
Input signals are stable
Operating current IO = 0 mA
ICC4 150 140 mA 1
(Burst mode) Page burst
Refresh current ICC5 tRC ≥ tRC(min) 220 200 mA 2
C 2 mA 3
Self refresh current ICC6 CKE ≤ 0.2V
L 800 uA 4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281632F-UC
4. K4S281632F-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
1200Ω 50Ω
VOH (DC) = 2.4V, IOH = -2mA
Output Output Z0 = 50Ω
VOL (DC) = 0.4V, IOL = 2mA
50pF 50pF
870Ω
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol Unit Note
- 60 (x16 only) - 75
Row active to row active delay tRRD(min) 12 15 ns 1
RAS to CAS delay tRCD(min) 18 20 ns 1
Row precharge time tRP(min) 18 20 ns 1
tRAS(min) 42 45 ns 1
Row active time
tRAS(max) 100 us
Row cycle time tRC(min) 60 65 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2,5
Last data in to Active delay tDAL(min) 2 CLK + tRP - 5
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
CAS latency=3 2
Number of valid output data ea 4
CAS latency=2 - 1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
mA
2.6 -21.1 -129.2 -7.5 -300
2.4 -34.1 -153.3 -13.3
2.0 -58.7 -197.0 -27.5
-400
1.8 -67.3 -226.2 -35.5
1.65 -73.0 -248.0 -41.1
1.5 -77.9 -269.7 -47.9 -500
1.4 -80.8 -284.3 -52.4
1.0 -88.6 -344.5 -72.5
-600
0.0 -93.0 -502.4 -93.0
Voltage
Voltage
mA
1.0 0.23 10
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35 5
2.0 9.83
2.2 12.48
2.4 15.30
0
2.6 18.31
0 1 2 3
Voltage
I (mA)
-30
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58 -40
-0.7 -0.05
-0.6 0.0 -50
-0.4 0.0
-0.2 0.0
-60
0.0 0.0
Voltage
I (mA)