Chapter 1

8088/8086 Microprocessors and supporting chips

First microprocessor of Intel is 4004 with 2,300 PMOS

transistors.
4004 is 4-bit processor, use in calculator.
In 1972 Intel designed 8008 with 8 bits processor.
8008 has 8-bit data bus and 16K bytes of memory .
8008 has 18-pin uses 3,000 PMOS transistors with 66
instructions.
In 1974 Intel introduce 8080 use NMOS technology in 40-
pin package.
8080 could handle 64K bytes of memory and had 111
instruction.
8080 has 2 supporting chip use for system controller and
oscillator.
In 1976 Intel repack all three chips into a single package
call 8085.
8088 was sold on 1970.

Evolution of Intel’s microprocessors (from 8008 to 8088)

Table 1-1

Intel microprocessors from 8086 to Pentium

by late of 1970 Intel was leading IC chip designer using
MOS technology Microprocessor and Memory.
In 1980 IBM has used Intel’s microprocessor for IBM PC.
1978 Intel had introduced 16-bit microprocessor called
8086.
8086 was 16-bit internally and externally.
1979 Intel introduced 8088 microprocessor with 16-bit
internally but 8-bit externally for use peripheral chips of
8085 and reduce board design cost.
 8086/8088 has 20 address pins and can address maximum
of 1M of memory with 29,000 NMOS in 40-pin package.

80286 microprocessor
In early 1980 Intel source for two of most important
components of PC : CPU and Memory (Dynamic RAM).
And in 1982 Intel introduced 80286 used 1300,000 NMOS
with 24 address pin and 16 pin for data and change
package from DIP to LCC (Leaded chip carrier)
80286 has fully compatible with 8088/8086 with new
instruction and capabilities.

IBM PC AT
In 1984 IBM used 80286 for design of PC AT
Many company cloning IBM PC AT and was more
successful than IBM such as Compaq.
In mid 1980 the drop in DRAM memory price caused Intel
withdraw from this market and shifted resources to
microprocessor design.

80386
In 1985 Intel introduced the 80386 microprocessor
80386 has 32-bit register and 32 bit address bus, allowing
it to address 4GB of memory.
80386 used 275,000 CMOS transistors packaged in 132-
pin PFA (Pin grid array)
2 popular versions of 80386: 80386DX and 80386SX.
While both at internally 32-bit microprocessor
80386SX has 16-bit external data bus and 24-bit address
bus
80386SX PC can running 32-bit software for 3086 without
the added cost of a larger motherboard.
In 1990 AMD and Cyrix began producing the 80386
microprocessor.

80486
 8046 was the first 1 million-transistor microprocessor. (1.2
million CMOS transistor) packaged in 168-pin PGA like
386
8046 was 32-bit microprocessor with capability of 4GB of
memory.
Intel integrated 80387 Math coprocessor in addition to 8K
bytes of cache memory into a single chip.
80486SX is exactly like 80486 except it does not contain
the math coprocessor. A math coprocessor for 80486Sx is
80487SX.

Pentium and Pentium Pro

In 1992 Intel release next version of 80X86
microprocessor, Pentium.
It given name instead of number because numbers cannot
copyrighted.
Pentium use sub-micron fabrication technology with more
than 3 million transistors at 60 – 66 MHz
Pentium was fully compatible with 80X86 microprocessor
with separate 8K cache for code and data, 64-bit bus and
improve floating point unit.
Pentium’s package is 273-pin PGA uses BICOMOS
technology with combine speed of bipolar transistor and
power efficiency of CMOS
Pentium has 32-bit address bus capable 4GB of memory
In 1995 Intel introduced Pentium Pro, The sixth generation
of 80x86 family
Pentium Pro is enhanced version of Pentium that used 5.5
million transistors.

Evolution of Intel’s x86 microprocessors (from 8086 to Pentium

Pro)
Table 1-2

Figure 1-1 8086 and 8088 in minimum mode

8088/8086 Microprocessor
 Data bus
8088 and 8086 are both 40-pin microprocessor chips, with
some differences in address and data buses.
Both are 16-bit processors internally, But
8088 has 8-bit data bus (AD0-AD7)
8086 has 16-bit data bus (AD0-AD15)
AD0-AD7/15 mean address and data bus multiplexed for
minimum number of pin.
When ALE (Address latch enable) is activate (Sets high)
use for indicate when AD0-AD7/15 is address. This
process call demultiplexing

Address bus
To demultiplex address signals from address/data pins,
Latch must be use.
Most widely use of latch is 74LS373
In any system all address must be latched to provide a
stable, high-drive capability for system.

Figure 1-3 Role of ALE in Address/Data Demultiplexing

Pin descriptions

Figure 1-2 8086 and 8088 in maximum mode

/BHE (Bus high enable)

8086 has 16 bit-external data bus. BHE use to distinguish
between low byte and high byte of data
Table 2-1

NMI (nonmaskable interrupt)

Edge-triggered (low to high) input signal to interrupt
processor which cannot be marked by software

INTR (interrupt request)

Active-high level-triggered input signal to interrupt
processor which can be masked by software
 In IBM PC this pin connected to 8259 interrupt controller
and INTA (interrupt acknowledgment) is provided by
8288

CLOCK
Microprocessor require a very accurate clock for
synchronization event and driving CPU
8084 is clock generator for Intel microprocessor

RESET
to terminate present activities of microprocessor and
automatically contain data shown in table

Table 1-3

READY
ready is input signal used to inserted wait state for slow
memories and I/O.

TEST
Input from 8087 coprocessor for synchronize 8087 and
8088/8086.
If it is low, executing of program will continue, If not it
will stop executing.

Minimum/Maximum mode
Function of pins 24-31 of 8088/8086 depending on mode
of processor.
Minimum mode is selected by connecting ping MN/MX to
+ 5V and ground for maximum mode.

Minimum mode
Pins 24-31 are used as memory and I/O control signal that
generated internal of 8088/8086.
Similarly to earlier 8085A 8-bit microprocessor

Table 1-4 Minimum mode 8088/8086 control signals

 Maximum mode
Some control signals are generated externally by 8088
(Bus control chip)
Some new feature available only in maximum mode, Can
used math coprocessor

QS0, QS1 (queue status, pins 24 and 25)

Two outputs signal give information about status of queue
inside microprocessor at any given time.
In IBM PC these two pins are connected to 8087 math
coprocessor to synchronize to 8088 and 8087.

Table 1-5 Queue Status Signals

/S0, /S1 and /S2 (Status signals, pins 26, 27 and 28)
Three status signal output pins from 8088/8086 to 8288 to
produces all control signal such as DT/R, DEN,
MC/PDEN, ALE, INTA,IOR IOW, MRD, MRWT.

Table 1-6 Control Signals for the 8288

/LOCK (pin 29)

Active-low output signal use to prevent another processor
or device from gaining control of system bus.
LOCK activated by prefix in instruction of an assembly
language program.
When LOCK executed, Output will stay low
In IBM PC, LOCK use to prevent the DMA from gaining
control of buses unintentionally.

/RQ / /GT0, /RQ / /GT1 (request/grant, pins 30 and 31)

Bi-directional pins all another processor to gain control of
local bus.
/RQ / /GT0 is high priority than /RQ / /GT1
In IBM PC, /RQ / /GT0 is permanently connected to high,
making it disable.
 /RQ / /GT1 is connected to 8087 math coprocessor to
allow it to access the buses.

Pin 24-31 in minimum mode

Table 1-7 Summary of pins 24-31, 34 in minimum mode

8088 minimum mode control bus design

8086/8088 in minimum mode some control signals must
be generated using logic gates. In maximum mode using
8288
8086/8088 provide 3 signals: /RD, /WR and IO / /M

Table 1-8 Control Signal Generation

Figure 1-4 Control Signal Generation

Figure 1-5 Control Signal Generation using Logic Gates

Basic buses for a minimum mode 8088

Three basic buses: Address, Data and Control bus.
In 8088 AD0-AD7 are used for both Address and Data bus
/MEMR, /MEMW, /IOR and /IOW are generated from
/RD, /WR and IO / /M pin.

Figure 1-6 8088 Address, Data and Control Buses

8284 Clock Generator and Driver

Has 18 pins in DIP package, Design for 8088/8086.
It is provide Clock and Synchronization for CPU and
READY signal for insertion wait states into CPU bus
cycle.

Figure 1-7 8284A Chip

Input Pins
/RES (Reset in)
 Active-low signal to generated RESET connected to
power-good signal from power supply.
When switch on power supply and low on this signal 8084
force CPU to reset called cold boot.

X1 and X2 (Crystal in)

Pins to attached crystal
Crystal must be 3 times of desired frequency for CPU.
Maximum frequency for 8284A is 24 MHz and 30 MHz
for 8284A-1.
IBM PC used 14.31818 MHz crystal, and 24MHz for
Turbo compatible.

F / /C (Frequency/Clock select)
Select two sources of clock : Generated internally 8284
(using Crystal) or receive clock from EFI pin.
IBM PC connected this pin to low mean generated
internally.

EFI (External Frequency In)

External frequency is connected to this pin and F / /C pin
must connect to high.

CSYNC (Clock synchronization)

Active-high signal used to several 8284 chips to
synchronize.
IBM PC only uses one 8284, This pin connected to ground

RDY1 and /AEN1

RDY is active high, /AEN1 is active low.
Used together to provide ready signal to CPU to insert
WAIT state when read/write cycle.
IBM PC connected RDY1 to DMAWAIT and /AEN1 to
RDY/WAIT

RDY2 and /AEN2

 Like RDY1 and /AEN1 used for multiprocessor system.
In IBM PC RDY2 connected to ground and /AEN2
connected to Vcc for permanently disables.

/ASYNC
Ready synchronization select, active low pin for device
that are not able to adhere in setup time.
IBM PC connected this pin to low make system design
easier with slower logic gates.

Output signals
RESET
Active-high signal to RESET 8088/8086 CPU.

OSC (Oscillator)
Provides clock equal to crystal use for expansion slot.

CLK (Clock)
One-third clock (4.772776 MHz) frequency from crystal
or EFI pin, with 33% of duty cycle.
Connected to clock input of 8088/8086 and all devices that
must be synchronized with CPU.

PCLK (peripheral clock)

One-half of CLK (one-sixth of crystal or EFI pin), with
50% of duty cycle. (2.386383 MHz)
Connected to 8253 timer chip, to generate speaker tones
and other function.

READY
Connected to READY pin of CPU to insert WAIT state
due to slowness of devices that CPU trying to connect.

8288 Bus Controller

Figure 1-9 8288 Bus Controller

Input signals
/So, /S1, /S2 (Status pin)
Come from 8088/8086, and generated one of control sinal.

Table 1-9 Status Pins of the 8288 and Their Meanings

CLK (Clock)
Input from 8284 clock generator to synchronize all
command and control signal with CPU.

/AEN (Address enable)

Active-low signal, activates 8288 command output >= 115
ns after its activation
IBM PC connected to AEN generation circuitry.

CEN (Command enable)

Active-high signal, activates/enable command signal and
DEN
IBM PC connected to AEN generation circuitry.

IOB (Input/Output bus mode)

Active-high signal makes 8288 operate in input/output bus
mode rather than system bus mode.
IBM PC designed with system bus mode, connected to
ground.

Output signals

/MRDC (Memory read command)

Active-low pin, provide /MEMR control signal.
Activates the selected device or memory to release its data
to data bus.

/MWTC (Memory write command), /AMWC (Advanced

memory write)
Active-low pins, Tell memory to record data present on
data bus.
 Same as /MEMW, /AMWC is activated slightly earlier to
give extra time for slow devices.
IBM PC used /MWTC as /MEMW, /AMWC is unused.

/IORC (I/O read command)

Active-low pins, Tell I/O to released its data into data bus.
In PC called /IOR (I/O read).

/IOWC (I/O write command) and /AIOWC (Advance I/O

write command)
Same as /MWTC and /AMWC, But use for I/O not
memory.

/INTA (interrupt acknowledge)

Active-low signal will inform interrupting for device that
its interrupt has been acknowledge and will provide vector
address to data bus.
IBM PC connected this pin to INTA of 859 interrupt
controller.

DT / /R (Data transmit/receive)
Use to control direction of data in and out for 8088/8086.
In IBM PC it is connected to DIR pin of 74LS245.
When CPU is writing this pin is high and allow data go
from A to B of 74LS245.
When CPU is reading this pin is low and allow data go
from B to A of 74LS245.

DEN (Data enable)

Active-high signal, use with signal from 8259 to activate
G of 74LS245.

MCE/PDEN (Master cascade enable/Peripheral data enable)

Used along 8259 in master configuration.
IBM PC used 8259 as slave, This pin is ignored.

ALE (Address latch enable)

 Active-high signal, used to activate address latch.
IBM PC used in demultiplexing address and data signal
from ADx pin by connected to G of 74LS373.

Overview of timing

Figure 1-10 8088 Timing Diagram fro IOR and MEMR

IBM PC/XT buses

Three bus: Address, Data and Control bus.
Only CPU and 8237 DMA controller can access the bus.
DMA used to transfer large of data from device and
memory without CPU.
DMA and CPU can use bus by control of bus arbitration
circuit.

Figure 1-11 8088 Connections and Busses in PC/XT

AEN signal generation

Table 1-10 AEN Bus arbitration

Figure 1-12 AEN generation circuitry in PC/XT

Local bus and System bus

Bus buffering