UART Specification 1 of 5

UART Specification

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1 Hardware overview

The UART in SI16P for the IC35 project is of a type similar to the TI16550. The base clock for this
UART is 1.8432 MHz. The system provides 6 UART lines to access DTE or DCE. These are CTS,
DSR, RXD, TXD, RTS, and DTR with RS232 voltage level. The cable and IrDA share one
UARTchannel , COM1 is for cable, COM2 is for IrDA.

2 UART register

2.1 Receive Buffer Register (read-only)

Bit 7 to bit 0: keep the data from the RX line.

Offset in UART module: 0x00.

2.2 Transmitter Holding Register (write-only)

Bit 7 to bit 0: keep the data to be sent to the TX line.

Offset in UART Module: 0x01.

2.3 Interrupt Enable Register (IER)

Offset in UART Module: 0x01.

Bit Description
0 1: Enable Received Data Available Interrupt
1 1: Enable Transmitter Holding Register Empty
2 1: Enable Receiver Line Status Interrupt
3 1: Enable Modem Status Interrupt
4 Always 0
5 Always 0
6 Always 0
7 Always 0

Example of accessing the UART register:

VisitUartReg( 1, // COM1: Cable
1, // IER Offset is 0x01
1, // Write
0x0f ) // Enable all interrupt sources

2.4 Interrupt Ident. Register (read-only)

Offset in UART Module: 0x02.

Bit Description

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0 Bit 3:0=0000, No Interrupt

1 Bit 3:0=0110, Interrupt on overrun error, parity error, framing error or break.
2 Bit 3:0=0100, Receiver data available in FIFO.
3

Bit 3:0=Timeout
Bit 3:0=Transmitter holding register is empty.
Bit 3:0=Interrupt by Modem Status.
4 Always 0
5 Always 0
6 Not significant
7 Not significant

2.5 FIFO Control Register (write-only)

Offset in UART Module: 0x02.

Bit Description
0 1: FIFO Enable
1 1: RX FIFO Reset
2 1: TX FIFO Reset
3 Always 0
4 Always 0
5 Always 0
6 Bit 7:6=0, receiver FIFO Trigger Level is 1 byte.
7 Bit 7:6=1, receiver FIFO Trigger Level is 4 bytes.
Bit 7:6=2, receiver FIFO Trigger Level is 8 bytes.
Bit 7:6=3, receiver FIFO Trigger Level is 14 bytes.

2.6 Line Control Register

Offset in UART Module: 0x03.

Bit Description
0 Bit 1:0=0, Word Length is 5 bits.
1 Bit 1:0=1, Word Length is 6 bits.
Bit 1:0=2, Word Length is 7 bits.
Bit 1:0=3, Word Length is 8 bits.
2 Number of stop bits.
3 1: Parity Enable
0: Parity Disable
4 1: Even Parity
0: Odd Parity
5 1: Stick Parity
6 1: Break Control Enable
7 1: Baud Rate Divisor Register can be accessed.

Notice: It is strongly recommended that you use a BIOS call to set the bit width instead of accessing
the UART register directly.

2.7 Modem Control Register

Offset in UART Module: 0x04.

Bit Description
0 Set DTR
1 Set RTS

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2 Always 0.
3 Always 0.
4 Always 0.
5 1: Auto flow control.
6 Always 0.
7 Always 0.

Notice: This register is of no significance for IrDA.

2.8 Line Status Register

Offset in UART Module: 0x05.

Bit Description
0 1: Data Ready
1 1: Overrun error
2 1: Parity Error
3 1: Framing Error
4 1: Break Interrupt
5 1: Transmitter Holding Register
6 1: Transmitter is Empty
7 Not significant

2.9 Modem Status Register

Offset in UART Module: 0x06.

Bit Description
0 1: Changes on CTS
1 1: Changes on DSR
2 1: Don’t care
3 1: Don’t care
4 Level of CTS
5 Level of DST
6 Not significant
7 Not significant

Notice: This register is of no significance for IrDA.

2.10 Baud Rate Divisor Register (LSB)

Offset in UART Module: 0x06.

Item Baud rate Divisor (LSB) Divisor (MSB)
1 115200bps 1 0
2 57600bps 2 0
3 38400bps 3 0
4 19200bps 6 0
5 14400bps 8 0
6 9600bps 0x0c 0
7 7200bps 0x10 0
8 4800bps 0x18 0
9 2400bps 0x30 0
10 1200bps 0xf6 0

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2.11 Baud Rate Divisor Register (MSB)

Offset in UART Module: 0x07.

Notice: It is strongly recommended that you use a BIOS call to set the bit width instead of accessing
the UART register directly.

2000/8/4 Revision 1.1