Adc Testing Resource Follow

EE247
Lecture 12
• Data Converters
– Data converter testing (continued)
• Measuring DNL & INL
– Servo-loop
– Code density testing (histogram testing)
• Dynamic tests
– Spectral testing Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
• Direct Discrete Fourier Transform (DFT) based
measurements utilizing sinusoidal signals
• DFT measurements including windowing
• Relationship between: DNL & SNR, INL & SFDR
• Effective number of bits (ENOB)
EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 1
Summary
ADC Differential Nonlinearity & Integral Nonlinearity
End-Point
1. Endpoints connected +0.5 LSB DNL error
7
2. Ideal characteristics 6
Digital Output Code
derived eliminating
offset & full-scale error 5
(same as for DNL) -1 LSB INL
4
3. DNL  deviation of 3
code width from D 2

(1LSB)
1
4. INL deviation of code 0

transition from ideal -0.5 LSB DNL error
-1 0 1 2 3 4 5 6 7 8
ADC Input Voltage [D]
EECS 247 Lecture 11: Intro. to Data Converters & Performance Metrics © 2010 H. K. Page 2
How to measure DNL/INL?
• DAC:
– Simply apply digital codes and use a good voltmeter to
measure corresponding analog output
• ADC
– Not as simple as DAC need to find "decision levels", i.e.
input voltages at all code boundaries
• One way: Adjust voltage source to find exact code trip
points "code boundary servo"
• More versatile: Histogram testing
Apply a signal with known amplitude distribution and
analyze digital code distribution at ADC output
Code Boundary Servo

Input
Digital i1
Code C1
A VREF fS
A<B
ADC
Digital R2 Input ADC
Comp. Under
AB Test
B
C2
i2
ADC
Output
Code Boundary Servo
• i1 and i2 are small,
111
ADC Digital Output

and C1 is large
(DV=it/C1), so the 110
ADC analog input
101
moves a small
fraction of an LSB
100
(e.g. 0.1LSB) each
sampling period 011
010
• For a code input of
101, the ADC analog 001
input settles to the 000
code boundary shown
D 2D 3D 4D 5D 6D 7D
ADC Analog Input
Code Boundary Servo

Input Good DVM
Digital i1
Code C1
A VREF fS
A<B
Digital R2
Comp. ADC
AB
B
C2
i2
ADC
Output
Code Boundary Servo
• A very good digital voltmeter (DVM)
measures the analog input voltage
corresponding to the desired code boundary
• DVMs have some interesting properties
– They can have very high resolutions (8½ decimal
digit meters are inexpensive)
– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line
cycles to filter out pickup in the measurement loop
Code Boundary Servo

• ADCs of all kinds are Good DVM
notorious for kicking
back high-frequency, VREF fS
signal-dependent
glitches to their analog R2
inputs ADC
C2
• A magnified view of an
analog input glitch
follows …
Code Boundary Servo
• Just before the input is
sampled and
analog input
conversion starts, the
analog input is pretty
quiet
• As the converter begins

to quantize the signal, it start of conversion
kicks back charge
0 1/fS
time
Code Boundary Servo

DVM measures the average
• The difference between input including the glitch
what the ADC
analog input
measures and what the

DVM measures is not
ADC INL, it’s error in
the INL measurement
• How do we control this ADC converts this voltage

error?
0 1/fS
time
Code Boundary Servo
• A large C2 reduces the Good DVM
effect of kick-back
VREF fS
• At the expense of longer
measurement time R2
ADC
C2
Histogram Testing
• Code boundary measurements are slow
– Long testing time
• Histogram testing
– Apply input with known pdf (e.g. ramp or sinusoid)
& quantize
– Measure output pdf
– Derive INL and DNL from deviation of measured
pdf from expected result

Histogram Test Setup
VREF fS
Ramp VREF
ADC PC
Time
0
• Slow (wrt conversion time) linear ramp applied to ADC

• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
A/D Histogram Test Using Ramp Signal

Digital Output
Example:
ADC
ADC sampling rate: Input/Output
fs =100kHz  Ts=10msec
1LSB =10mV
For 0.01LSB measurement
resolution: Analog
n =100 samples/code input
 Ramp duration per code:

=100x10msec=1msec n.Ts
Ramp
 Ramp slope: 10mV/msec
Time

A/D Histogram Test Using Ramp Signal
Digital Output
Example: Ideal ADC
Input/Output
Ramp slope: 10mV/msec
1LSB =10mV
Each ADC code1msec
Analog
input
fs =100kHz  Ts=10msec
n =100 samples/code n/fs Ramp
Time
Per code
Samples
n
# of
Digital
Output
Ramp Histogram
Example: Ideal 3-Bit ADC
200
ADC characteristics
ideal converter
7 180
6 160
Code Count
Digital Output Code
140
5
120
4
100
3
80
2 60
1 40
0 20
0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7
ADC Input Voltage [D]
ADC output code

Ramp Histogram
Example: Real 3-Bit ADC Including Non-Idealities
ADC characteristics
200
ideal converter
7 180
6 160
-0.4 LSB DNL
Digital Output Code
140
Code Count
5
120
4
100
3
+0.4 LSB INL 80
2
60
1 40
+0.4 LSB DNL
0 20
0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7
ADC Input Voltage [D] ADC output code
Example: 3 Bit ADC

DNL Extracted from Histogram
140
Code Count, End bins removed
1- Remove “Over-range bins” 120
(0 and full-scale) 100
80
2- Compute average count/bin
(600/6=100 in this case) 60
40
20
0
0 1 2 3 4 5 6 7
ADC output code

Example: 3 Bit ADC
Process of Extracting from Histogram
3- Normalize: 1.4
Normalized Code Count

1.2
- Divide histogram by 1
average count/bin
0.8
 ideal bins have exactly the

0.6
average count, which, after
normalization, would be 1 0.4
 Non-ideal bins would have 0.2

a normalized value greater or
smaller than 1 0
0 1 2 3 4 5 6 7
ADC output code
Example: 3 Bit ADC

DNL Extracted from Histogram
4- Subtract 1 from the

DNL = Counts / Mean(Counts) -1
0.4
normalized code count 0.3
0.2
5- Result  DNL (+-0.4LSB 0.1

in this case) 0
-0.1
-0.2
-0.3
-0.4 0 1 2 3 4 5 6 7
ADC output code

Example: 3-Bit ADC
Static Characteristics Extracted from Histogram
• DNL histogram  used to

reconstruct the exact converter 7 Reconstructed ADC
characteristic (having measured Transfer Characteristic
only the histogram) 6
Digital Output
5
• Width of all codes derived from 4
measured DNL (Code=DNL +
1LSB) 3
2
• INL(deviation from a straight 1
line through the end points)- is
found 0
0 1 2 3 4 5 6 7
ADC Input Voltage
Example: 3 Bit ADC

DNL & INL Extracted from Histogram
ADC characteristics
Ideal converter
1
DNL [LSB]
7 0.5
6 0
Digital Output Code
-0.4 LSB DNL

5 -0.5
-1
4 1 2 3 4 5 6
3 1
+0.4 LSB INL
INL [LSB]
2 0.5
1 0
+0.4 LSB DNL
-0.5
0
-1
0 1 2 3 4 5 6 7 1 2 3 4 5 6
ADC Input Voltage [D] Digital Output Code

Measuring DNL
• Ramp speed is adjusted to provide large number of
output/code - e.g. an average of 100 outputs of each
ADC code (for 1/100 LSB resolution)
• Ramp test can be quite slow for high resolution ADCs

• Example:
16bit ADC & 100conversions/code @100kHz
sampling rate
(216or 65,536 codes)(100 conversions/code)
= 65.6 sec
100,000 conversions/sec
ADC Histogram Testing

Sinusoidal Inputs
• Ramp signal generators linear ADC Output- Raw Histogram

to only 8 to10bits & thus only
good for testing ADCs <10bit
res. 1000
Code Count
 Need to find input signal

with better purity for testing
higher res. ADCs
• Solution: 500
Use sinusoidal test signal
(may need to filter out
harmonics)
• Problem: Ideal ADC histogram 0 1000 2000 3000 4000

not flat but has “bath-tub shape” ADC output code

ADC Histogram Test Using Sinusoidal Signals
Digital Output
At sinusoid midpoint crossings:
dv/dt  max. ADC
Input/Output
 least # of samples
Analog
At sinusoid amplitude peaks: input
dv/dt  min.
 highest # of samples
Per code Time

Sinusoid
Samples
# of
Digital
Output
Histogram Testing
Correction for Sinusoidal PDF
• Is it necessary to know the exact amplitude and offset
of sinusoidal input? No!
• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,
“Dynamic Testing and Diagnostics of A/D Converters,” IEEE
Transactions on Circuits and Systems, vol. CAS-33, no. 8,
Aug. 1986.
– [2] IEEE Standard 1057

DNL/INL Extraction Matlab Program
Sinusoidal Histogram
% transition levels found by:

function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN T = -cos(pi*ch/sum(h));
% dnl and inl ADC output
% input y contains the ADC output % linearized histogram
% vector obtained from quantizing a hlin = T(2:end) - T(1:end-1);
% sinusoid
% truncate at least first and last
% Boris Murmann, Aug 2002
% bin, more if input did not clip ADC
% Bernhard Boser, Sept 2002
trunc=2;
% histogram boundaries hlin_trunc = hlin(1+trunc:end-trunc);
minbin=min(y);
maxbin=max(y); % calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
% histogram dnl= [0 hlin_trunc/lsb-1];
h = hist(y, minbin:maxbin); misscodes = length(find(dnl<-0.99));
% cumulative histogram
% calculate inl
ch = cumsum(h);
inl= cumsum(dnl);
Example: Test Results for DNL & INL

Using Sinusoidal Histogram
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.99)
DNL [LSB]
-1
0 500 1000 1500 2000 2500 3000 3500 4000
code
2 INL = +1.7 / -0.69 LSB
INL [LSB]
-1
0 500 1000 1500 2000 2500 3000 3500 4000
code

Example: Matlab ADC Model
DNL/INL Code Test
% converter model
DNL = +0.7 / -0.7 LSB
1
DNL [LSB]
B = 6; % bits
0.5
range = 2^(B-1) - 1;
% thresholds (ideal converter) 0
th = -range:range; % ideal thresholds
-0.5
th(20) = th(20)+0.7; % error
-1
-30 -20 -10 0 10 20 30
fs = 1e6;
fx = 494e3 + pi; % try fs/10!
C = round(100 * 2^B / (fs / fx));
INL = +0.7 LSB
0.8
INL [LSB]
t = 0:1/fs:C/fx;
0.4
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
0
hist(y, min(y):max(y)); -30 -20 -10 0 10 20 30
dnl_inl_sin(y); Digital Output
Histogram Testing Limitations

• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.
• Dynamic sparkle codes produce only minor DNL/INL errors

E.g. 123, 123, …, 123, 0, 124, 124, …  look at ADC output to
detect
• Noise not detected & averaged out
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution
ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.

Why Additional Tests/Metrics?
• Static testing does not tell the full story
– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?
– In principle we can vary fs and fin when performing
histogram tests
– Result of such sweeps is usually not very useful
– Hard to separate error sources, ambiguity
– Typically we use fs=fsNOM and fin << fs/2 for
histogram tests
• For additional info regarding higher frequency
operation  Spectral testing
DAC Spectural Test or Simulation

Device Under Test
(DUT)
Digital
Sinusoid
Signal Vout Spectrum
Generator DAC
Analyzer
Clock
Generator
• Input sinusoid  Need to have significantly better purity compared to DAC

linearity
• Spectrum analyzer need to have better linearity than DUT
• Typcally, test performed at several different input signal frequencies

Filtering Input to Spectrum Analyzer
Prevent Signal Distortion Incurred by Spec. Analyzer
1.Measure
fundamental
signal level Notch (Band Reject) Filter
DAC
2.Notch out
Output Signal
fundamental
Amplitude ...
signal so that
Spec. Analyzer
input signal 0 fin 2fin 3fin 4fin ... f
becomes small
enough not to Spectrum
drive S.A. input Analyzer
into non-linear Input
region Signal ...
3.Measure the Amplitude
harmonic content
of the DAC output 0 fin 2fin 3fin 4fin ... f
Direct ADC Spectral Test via DAC

Device Under Test (DUT)
Signal Vin Vout Spectrum

Generator ADC DAC Analyzer
Clock
Generator
• Need DAC with much better performance compared to ADC

under test
• Beware of DAC output sinx/x frequency shaping
• Good way to "get started"...

Direct ADC-DAC Test
Device Under Test (DUT)
Bandpass
Signal or V in Notch
ADC DAC
Generator Lowpass Filter
Filter
Clock Spectrum
Generator Analyzer
• Issues to beware of:

– Linearity of the signal generator output has to be much better than ADC linearity
– Spectrum analyzer nonlinearities
 May need to build/purchase filters to address one or both above
problems
– Clock generator signal jitter
Filtering ADC Input Signal

Bandpass Filter
Signal Generator
Output Signal
Amplitude ...
0 fin 2fin 3fin 4fin ... f

ADC
Input
Signal
Amplitude ...
0 fin 2fin 3fin 4fin ... f

ADC Spectral Test via
Data Acquisition Sytem
Device Under Test

(DUT)
Signal Vin Data

ADC Acquisition PC
Generator System
Clock
Generator
Analyzing ADC Outputs via

Discrete Fourier Transform (DFT)
x(t) x(k)

• Sinusoidal waveform has all its power at one single frequency
• An ideal, infinite resolution ADC would preserve ideal, single tone

spectrum
• DFT used as a vehicle to reveal ADC deviations from ideality

Discrete Fourier Transform (DFT)
Properties
• DFT of N samples spaced Ts=1/fs seconds:
– N frequency bins from DC to fs
– Num of bins  N & each bin has width= fs /N
– Bin # m represents frequencies at m * fs /N [Hz]
• DFT frequency resolution:

– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a

computationally more efficient algorithm named:
– FFT  Fast Fourier Transform
DFT Magnitude Plots

• Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is
redundant to plot Am’s for m >N/2
0 fs/2 fs
• Usually magnitudes are plotted on a log scale normalized so that a

full scale sinusoidal waveform with rms value aFS yields a peak bin of
0dBFS:
Am
Am [dBFS] = 20 log10
aFS .N/2

Matlab Example
Normalized DFT
fs = 1e6; 1
fx = 50e3;
Afs = 1; 0.5
Amplitude
N = 100;
0
% time vector -0.5

t = linspace(0, (N-1)/fs, N);
-1
% input signal 0 0.2 0.4 0.6 0.8 1
-4
Time x 10
y = Afs * cos(2*pi*fx*t);
Magnitude [ dBFS ]
% spectrum 0
s = 20 * log10(abs(dft(y)/N/Afs*2));
-100
% drop redundant half
s = s(1:N/2); -200
% frequency vector (normalized to fs)
f = (0:length(s)-1) / N; -300
Note: Where does the -300dBFS noise 0 0.1 0.2 0.3 0.4 0.5
fx/fs Frequency [ f / fs]
floor come from?
“Another” Example …
1
Signal Amplitude
Even though the

input signal is a
0 pure sinusoidal
waveform note that
-1
0 1 2 3 4 5
the DFT results
Time x 10-5 does not look like
Amplitude [ dBFS ]
-10 the spectrum of a

-20 sinusoid …
-30
Seems that the
-40
signal is distributed
-50
0 0.1 0.2 0.3 0.4 0.5 among several bins
Frequency [ f / fs ]

DFT Periodicity
Actual Signal
1
• The DFT implicitly assumes that time
Signal Amplitude
sample blocks repeat every N 0.5
samples
0
• With a non-integer number of signal
periods within the observation -0.5
window, the input yields significant
amplitude/phase discontinuity at the -1
0 0.4 0.8 1.2 -4
block boundary Time x 10
DFT Perceived Signal
• This energy spreads into other 1
Signal Amplitude
frequency bins as “spectral leakage”
0.5
• Spectral leakage can be eliminated
0
by either
1. Choice of integer number of -0.5
sinusoids in each block
2. Windowing -1
0 0.4 0.8 1.2 -4
Time x 10
Frequency Spectrum
Integer # of Cycles versus Non-Integer # of Cycles
Integer number of cycles Non-integer number of cycles
1
1
Signal Amplitude
Signal Amplitude
0.5
0.5
0
0
-0.5
-0.5
-1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 -1
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Time -4 -4
x 10 Time x 10
0 -10
Amplitude [ dBFS ]
Amplitude [ dBFS ]
-20
-100
-30
-200
-40
-300
-50
-400 -60
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / f s] Frequency [ f / f s]

Choice of Number of Cycles & Number of
Samples
To overcome frequency N/cycles = fs / fx=6  integer
Signal Amplitude
spectrum leakage problem: 1
0.5
– Number of Cycles 0
 integer
-0.5
-1
– N/cycles = fs / fx Time
 non-integer (choose
prime # of cycles)
otherwise quant. noise  N/cycles = fs / fx=5.55  non-integer
1
Signal Amplitude
periodic and non-random
0.5
– Preferable to have N:  0
power of 2 (FFT instead of
-0.5
DFT)
-1
Time
Example: Integer Number of Cycles

fs = 1e6;
% Number of cycles in test 0
cycles = 67;
-50
Magnitude [ dBFS ]
%Make N/cycles non- -100

integer!
accomplished by choosing -150
cycles prime #
-200
%N=power of 2 speeds up
analysis -250
-300
N = 2^10;
-350
%signal frequency 0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / fs ]
fx = fs*cycles/N
y = Afs * cos(2*pi*fx*t); Notice: Range of test signals limited to
s = 20 * log10(abs(fft(y)/N/Afs*2)); [( cycles)x fs/N]

Example: Integer Number of Cycles
• Fundamental falls into a single

0
DFT bin
-50
Amplitude [ dB ]
• Noise (this example numerical -100
quantization noise) occupies all
-150
other bins
-200
• “integer number of cycles” -250
constrains signal frequency fx -300
-350
0 0.1 0.2 0.3 0.4 0.5
• Alternative: windowing  s]
Frequency [ f / fs]
Windowing
• Spectral leakage can be attenuated by “windowing”
time samples prior to the DFT
– Windows taper smoothly down to zero at the beginning and
the end of the observation window
– Time samples are multiplied by window coefficients on a
sample-by-sample basis
 Convolution in frequency domain
• Large number choices of various windows

– Tradeoff: attenuation versus fundamental signal spreading to
number of adjacent bins
• Window examples: Nuttall versus Hann

Example: Nuttall Window
Time domain Frequency domain
1 20
0
0.8
Magnitude (dB)
Amplitude
-20
0.6
-40
0.4
-60
0.2 -80
0 -100
20 40 60 0 0.2 0.4 0.6 0.8
Samples Normalized Frequency ( rad/sample)
• Time samples are multiplied by window coefficients on a sample-by-sample basis

• Multiplication in the time domain  convolution in the frequency domain
Windowed Data
Signal Amplitude
1
• Signal before windowing
0
• Time samples are -1

multiplied by window 0 0.2 0.4 0.6 0.8 1
coefficients on a sample- Time [msec]
by-sample basis
2
Signal Amplitude
Windowed
• Signal after windowing

0
– Windowing removes
the discontinuity at
block boundaries -2
0 0.2 0.4 0.6 0.8 1
Time [msec]

Nuttall Window DFT
• Only first 20 bins shown 0
Normalized Amplitude [dB]

• Response attenuated by -120dB -20
for bins > 5
-40
• Lots of windows to choose from -60

(go by name of inventor-
Blackman, Harris, Nutall…) -80
• Various window trade-off -100
attenuation versus width

-120
(smearing of sinusoids)
2 4 6 8 10 12 14 16 18 20
DFT Bin
DFT of Windowed Signal

Spectrum Before/After Windowing
Spectrum not Windowed
0
• Windowing results Before windowing
[ dBFS ]
-20
in ~ 100dB
attenuation of -40
sidelobes -60
0 0.1 0.2 0.3 0.4 0.5

Frequency [ fx / fs]
0
• Signal energy
Windowed Spectrum
After windowing
“smeared” over -40
[ dBFS ]
several -80
(approximately 10) -120
bins 0 0.1 0.2 0.3 0.4 0.5
Frequency [ fx / fs]

Window
Nuttall versus Hann
Time domain Frequency domain
1 Nuttall
Magnitude (dB)
0 Hann
0.8
Amplitude
0.6
0.4 -50
0.2
0 -100
20 40 60 0 0.2 0.4
Samples Normalized Frequency ( rad/sample)
Matlab code:
N=64;
wvtool(nuttallwin(N),hann(N));
Integer Cycles versus Windowing
• Integer number of cycles

– Signal energy for a single sinusoid falls into single DFT bin
– Requires careful choice of fx
– Ideal for simulations
– Measurements  need to lock fx to fs (PLL)- not always possible
• Windowing
– No restrictions on fx  no need to have the signal locked to fs
 Good for measurements w/o having the capability to lock f x to fs or
cases where input is not periodic
– Signal energy and its harmonics distributed over several DFT bins –
handle smeared-out harmonics with care!
– Requires more samples for a given accuracy
– Note that no windowing is equal to windowing with a rectangular
window!

Example: ADC Spectral Testing
• ADC with B bits
• Full scale input level=2
B = 10;
delta = 2/2^B;
%sampled sinusoid
y = cos(2*pi*fx/fs*[0:N-1]);
%quantize samples to delta=1LSB
y=round(y/delta)*delta;
s = abs(fft(y)/N*2);
f = (0:length(s)-1) / N;
ADC Output Spectrum

0
N=2048
• Input signal bin:
-20
– Bx @ bin # (N * fx /fs + 1)
(Matlab arrays start at 1)
-40
Amplitude [dbFS]
– Asignal = 0dBFS
-60
• What is the SNR? -80
-100
-120
0 0.1 0.2 0.3 0.4 0.5
f /fs

Simulated ADC Output Spectrum
0
N=2048
• Noise bins: all except signal bin -20
Amplitude [dbFS]
bx = N*fx/fs + 1;
-40
As = 20*log10(s(bx))
%set signal bin to 0
-60
s(bx) = 0;
An = 10*log10(sum(s.^2))
SNR = As - An -80
• MatlabSNR = 62dB (10 bits) -100

• Computed SQNR =
6.02xN+1.76dB=61.96dB f /fs
-120
0 0.1 0.2 0.3 0.4 0.5
Note: In a real circuit including thermal/flicker noise  the measured
total noise is the sum of quantization & noise associated with the circuit
Why is Noise Floor Not @ -62dB ?

• DFT bins act like an analog 0
spectrum analyzer with N=2048
bandwidth per bin of fs /N -20
• Assuming noise is uniformly

Amplitude [dbFS]
distributed, noise per bin: -40
(Total noise)/N/2
-60
The DFT noise floor wrt total 30dB
noise: -80
-10log10(N/2) [dB]
-100
below the actual noise floor
• For N=2048: -120

0 0.1 0.2 0.3 0.4 0.5
-10log10(N/2) =-30 [dB] f /fs

DFT Plot Annotation
• Need to annotate DFT plot such that actual
noise floor can be readily computed by one of
these 3 ways:
1. Specify how many DFT points (N) are used
2. Shift DFT noise floor by 10log10(N/2) [dB]
3. Normalize to "noise power in 1Hz bandwidth“
then noise is in the form of power spectral
density
Example:10Bit ADC FFT

0
• For a real 10bit ADC
spectral test results: N = 4096
-20
SNR = 55.9dB
Amplitude [ dBFS ]
-40
SDR = 76.4dB
• SNR=55.9dB SNDR = 55.1dB
-60 SFDR = 77.3dB
• A 3rdharmonic is barely -80

visible
-100
• Is better view of distortion -120

component possible?
-140
0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / fs]

Example:10Bit ADC FFT
0
• Increasing N, the number of
samples (and hence the N = 65536
measurement or simulation SNR = 55.9dB SDR = 77.9dB
Amplitude [ dBFS ]
time) distributes the noise SNDR = 55.2dB SFDR = 78.5dB
over larger # of bins -50
• Larger # of bins  less

noise power per bin (total
noise stays constant) -100
• Note the 3rd harmonic is

clearly visible when N is
-150
increased 0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / fs]
Spectral Performance Metrics

ADC Including Non-Idealities
• Signal S
• DC
• Distortion D
• Noise N
• Ideal ADC adds:

– Quantization noise
• Real ADC typically adds:

– Thermal and flicker noise
– Harmonic distortion
associated with circuit
nonlinearities

ADC Spectral Performance Metrics
SNR
• Signal S
• DC
• Distortion D
• Noise N
• Signal-to-noise ratio
SNR = 10log[(Signal Power) /
(Noise Power)]
• In Matlab: Noise power includes

power associated with all bins
except:
– DC
– Signal
– Signal harmonics
ADC Spectral Performance Metrics

SDR & SNDR & SFDR
• SDR Signal-to-distortion ratio
= 10log[(Signal Power) /
(Total Distortion Power)]
• SNDR Signal-to-(noise+distortion)
= 10log[S / (N+D)]
• SFDR Spurious-free dynamic

range
= 10log[(Signal )/
(Largest Harmonic)]
 Typically SFDR > SDR

Harmonic Components
• At multiples of fx
• Aliasing:
– fsignal = fx = 0.18 fs
– f2 = 2 f0 = 0.36 fs
– f3 = 3 f0 = 0.54 fs
 0.46 fs
– f4 = 4 f0 = 0.72 fs
 0.28 fs
– f5 = 5 f0 = 0.90 fs
 0.10 fs
– f6 = 6 f0 = 1.08 fs
 0.08 fs
Relationship INL & SFDR/SNDR

ADC Transfer Curve
Output
Output
Real
INL Input INL Input
Quadratic shaped transfer function: Cubic shaped transfer function:

 Gives rise to even order harmonics  Gives rise to odd order harmonics

Frequency Spectrum versus INL & DNL
DNL [LSB]
0
-0.03 Good DNL and poor INL

suggests distortion
INL [LSB]
1
-1
INLNot fully symmetric
-2 100 200 300 400 500 600 700 800 9001000
bin #
Relationship INL & SFDR/SNDR

• Nature of harmonics depend on "shape" of
INL curve
• Rule of Thumb: SFDR  20log(2B/INL)

– E.g. 1LSB INL, 10b SFDR60dB
• Beware, this is of course only true under the

same conditions at which the INL was taken,
i.e. typically low input signal frequency

SNR Degradation due to DNL
[Source: Ion Opris]
• Uniform quantization error pdf was assumed for ideal quantizer

over the range of: +/- D/2
• Let's now add uniform DNL over +/- D/2 and repeat math...
– Joint pdf for two uniform pdfs  Triangular shape

• To find total noise  Integrate triangular pdf:
D e2 D2
e2  2  (1  e) de   SNR  6.02  N  1.25 [dB]
0 D 6
3dB
• Compare to ideal quantizer:
 D / 2 e2 D2  SNR  6.02  N  1.76 [dB]

e2   de 
D / 2 D 12
Error associated with DNL reduces overall SNR

• More general case:
– Uniform quantization error (ideal) ±0.5D
– Uniform DNL error ± DNL [LSB]
– Convolution yields trapezoid shaped joint pdf
– SQNR becomes:
2
1  2 N D 
2  2 
SQNR 
D2 DNL2

12 3

• Degradation in dB:  
1
 
Valid only for cases where
SQNR _ deg  1.76  10 log  8 
 1 DNL 
2 no missing codes
12  3 
8
6
SNR
Degradation
4
[dB]
0
0 0.2 0.4 0.6 0.8 1
|DNL| [LSB]

Summary
INL & SFDR - DNL & SNR
INL & SFDR DNL & SNR

• Type of distortion depends on Assumptions:
"shape" of INL • DNL pdf uniform
• No missing codes
• Rule of Thumb:
2
SFDR  20 log(2B/INL) 1  2 N D 
2  2 
SQNR 
– E.g. 1LSB INL, 10b D2 DNL2

 SFDR60dB 12 3
Uniform DNL?
250
# of occurrences
200
150
100
50
0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
DNL
• DNL distribution of 12-bit ADC test chip

• Not quite uniform...
Effective Number of Bits (ENOB)
• Is a 12-Bit converter with 68dB SNDR really a 12-Bit
converter?
• Effective Number of Bits (ENOB) # of bit of an ideal
ADC with the same SQNR as the SNDR of the non-
ideal ADC
SNDR  1.76dB
ENOB 
6.02dB
68  1.76
  11.0Bits
6.02
 Above ADC is a 12bit ADC with ENOB=11bits
ENOB
• At best, we get "ideal" ENOB only for
negligible thermal noise, DNL, INL
• Low noise design is costly  4x penalty in

power per (ENOB-) bit or 6dB extra SNDR
• Rule of thumb for good performance /power

tradeoff: ENOB < N-1

ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on

Selected Areas in Communications, pp. 539-50, April 1999

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EE247

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 1

code width from D 2

4. INL deviation of code 0

Code Boundary Servo

ADC Digital Output

Code Boundary Servo

Code Boundary Servo

• As the converter begins

Code Boundary Servo

measures and what the

• How do we control this ADC converts this voltage

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 12

• Slow (wrt conversion time) linear ramp applied to ADC

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 13

A/D Histogram Test Using Ramp Signal

 Ramp duration per code:

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 14

n =100 samples/code n/fs Ramp

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 15

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 16

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 17

Example: 3 Bit ADC

1- Remove “Over-range bins” 120

(0 and full-scale) 100

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 18

Normalized Code Count

 ideal bins have exactly the

 Non-ideal bins would have 0.2

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 19

Example: 3 Bit ADC

4- Subtract 1 from the

5- Result  DNL (+-0.4LSB 0.1

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 20

• DNL histogram  used to

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 21

Example: 3 Bit ADC

-0.4 LSB DNL

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 22

• Ramp test can be quite slow for high resolution ADCs

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 23

ADC Histogram Testing

• Ramp signal generators linear ADC Output- Raw Histogram

 Need to find input signal

• Problem: Ideal ADC histogram 0 1000 2000 3000 4000

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 24

Per code Time

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 25

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 26

% transition levels found by:

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 27

Example: Test Results for DNL & INL

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 28

dnl_inl_sin(y); Digital Output

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 29

Histogram Testing Limitations

• Dynamic sparkle codes produce only minor DNL/INL errors

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 30

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 31

DAC Spectural Test or Simulation

• Input sinusoid  Need to have significantly better purity compared to DAC

EECS 247 Lecture 12: Data Converters- Testing © 2010 H. K. Page 32

Direct ADC Spectral Test via DAC