Sizing Logic Paths for Speed

‰ Frequently, input capacitance of a logic path is constrained

‰ Logic also has to drive some capacitance
Logical Effort ‰ Example: ALU load in an Intel’s microprocessor is 0.5pF
- sizing for speed ‰ How do we size the ALU datapath to achieve maximum
speed?
‰ We have already solved this for the inverter chain – can we
generalize it for any type of logic?

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Buffer Example Logical Effort

 C 
Delay = k ⋅ Runit Cunit 1 + L 
 γCin 
In Out
= τ (p + g ⋅ f )

CL p – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)

1 2 N
g – logical effort (kRunitCunit) – gate parameter ≠ f(W)
N f – effective fanout (electrical effort)
Delay = ∑ ( pi + g i ⋅ f i )
i =1 (in units of τinv) • Normalize everything to an inverter:
ginv =1, pinv = 1
• For given N: Ci+1/Ci = Ci/Ci-1 • Divide everything by τinv
find N: Ci+1/Ci ~ 4 (everything is measured in unit delays τinv)
• How to generalize this to any logic path?
• Assume γ = 1.
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 Delay in a Logic Gate Logical Effort (g)
• Gate delay: ‰ Inverter has the smallest logical effort and intrinsic
d=p+h delay of all static CMOS gates
intrinsic delay effort delay
‰ Logical effort of a gate presents the ratio of its
• Effort delay: input capacitance to the inverter capacitance
h=gf when sized to deliver the same current
electrical effort =
‰
logical effort effective fanout = Cout/Cin
Logical effort increases with the gate complexity
Logical effort is a function of topology, independent of sizing.
Electrical effort (effective fanout) is a function of load/gate size
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Logical Effort (g) Logical Effort of Gates

Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current Delay: d = p + g f
VDD VDD VDD

Normalized delay (d)

A 2 A 2 B 2 B 4 g = 4/3 t
pNAND
p=2 tpInv
F g = 5/3 d = 2+ (4/3)f
F g=1
A 4
p=1
A 2
A 1
g = 4/3 F d = 1+ f
A 1 B 1 effort delay, g f
B 2
intrinsic delay, p
g=1
Inverter 2-input NAND 2-input NOR 1 2 3 4 5 6 7
Fanout (f)
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 Add Branching Effort Multistage Networks
N
Branching effort: Delay = ∑ ( pi + g i ⋅ f i )
i =1
Con − path + Coff − path
b= Stage effort: hi = gi fi
Con − path
• Path electrical effort: F = Cout/Cin
• Path logical effort: G = g1g2…gN
• Branching effort: B = b1b2…bN
Total path effort: H = GFB

Path delay D = Σdi = Σpi + Σhi

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Optimum Effort per Stage Optimal Number of Stages

Optimum delay is achieved when each stage bears the For a given load, and given input capacitance of the first
same effort: gate, find optimum number of stages and optimal sizing
hN = H
h=N H D = NH 1/ N + Npinv
• Stage efforts: g1f1 = g2f2 = … = gNfN
∂D
• Effective fanout of each stage: f i = h g i = − H 1/ N ln (H 1/ N )+ H 1/ N + pinv = 0
∂N
• Minimum path delay
h = H 1/ N
ˆ
Substitute ‘best stage effort’
Dˆ = ∑ (g i f i + pi ) = NH 1/ N + P

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 Logical Effort Method of Logical Effort
‰ Compute the path effort: H = GFB
‰ Find the optimum number of stages: N ~ log4H
‰ Compute the stage effort h = H1/N
‰ Sketch the path with this number of stages
‰ Work either from either end, find sizes (gate capacitance):
Cin = Cout • gi / h or Cout = Cin • h / gi

Cout
Cin
h / gi = fi
From Sutherland, Sproul
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
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Example: Optimize Path Example – 8-input AND

Assume no branching: B=1

1 b c
a
5
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
f1 = a/1 f2 = b/a f3 = c/b f4 = 5/c

Compute path effort:

F = f1 f2 f3 f4 = 5 a,b,c mean capacitances
G = g1g2g3g4 = 25/9
H = GFB= 125/9 = 13.9 Recall: h = const = fi gi
h = H 1/4 = 1.93
Compute gate sizes: f1 = h/g1 = 1.93
a = 1.93 f2 = h/g2 = 1.16
b = a h /g2 = 2.23 f3 = h/g3 = 1.16
c = b h /g3 = 5g4/h = 2.59 f4 = h/g4 = 1.93
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