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• Programmable OE control
I3 5 17 F5
programmable through a set of Ex-OR gates
for implementing AND-OR or AND-NOR logic B0 6 16 F4
functions. Similarly, any of the 32 AND gates • Positive edge-triggered clock B1 7 15 F3
can drive the J-K inputs of all flip-flops. There
are 4 AND gates for the Asynchronous
• Input loading: –100µA (max.) B2 8 14 F2
• TTL compatible
B3 GND OE F0 F1
All flip-flops are positive edge-triggered and
• 3-State outputs
can be used as input, output or I/O (for A = Plastic Leaded Chip Carrier
interfacing with a bidirectional data bus) in
conjunction with load control gates (L),
steering inputs (I), (B), (Q) and
programmable output select lines (E). APPLICATIONS
The PLS159A is field-programmable, • Random sequential logic
enabling the user to quickly generate custom
patterns using standard programming
• Synchronous up/down counters
equipment. • Shift registers
• Bidirectional data buffers
• Timing function generators
• System controllers/synchronizers
• Priority encoder/registers
ORDERING INFORMATION
DESCRIPTION ORDER CODE DRAWING NUMBER
20-Pin Plastic Dual In-Line Package (300mil-wide) PLS159AN 0408D
20-Pin Plastic Leaded Chip Carrier PLS159AA 0400E
LOGIC DIAGRAM
11 OE
I0 2
I1 3
I2 4
I3 5
F0
F1
F2
F3
F4
F5
F6
F7
B0
B1
B2
B3
C PB RB PA RA LB LA D3 D2 D1 D0 EA EB
S3 9 B3
X3
S2 8 B2
X2
S1 7 B1
X1
S0 6 B0
X0
P R
J Q 19 F7
M7
CK’
K
J Q 18 F6
M6
CK’
K
J Q 17 F5
M5
CK’
K
J Q 16 F4
M4
CK’
K
P R
J Q 15 F3
M3
CK’
K
J Q 14 F2
M2
CK’
K
J Q 13 F1
M1
CK’
K
J Q 12 F0
M0
CK’
K
CK 1 CLK
31 24 23 16 15 8 7 0 FC
NOTES:
1. All OR gate inputs with a blown link float to logic “0”.
2. All other gates and control inputs with a blown link float to logic “1”.
3. ⊕ denotes WIRE-OR.
4. Programmable connection.
FUNCTIONAL DIAGRAM
(LOGIC TERMS) (CONTROL TERMS)
PB RB PA RA LB LA D EA EB
a OE
a
a
b
b
b
Q
Q
C
S
B
X
P R
J Q F
M (4)
K CK
P R
J Q F
M (4)
K CK
T31 T0 FC
CK CLK
DC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V
LIMITS
SYMBOL PARAMETER TEST CONDITION MIN TYP1 MAX UNIT
Input voltage2
VIH High VCC = MAX 2.0 V
VIL Low VCC = MIN 0.8 V
VIC Clamp VCC = MIN, IIN = –12mA –0.8 –1.2 V
Output voltage2
VOH High VCC = MIN, IOH = –2mA 2.4 V
VOL Low IOL = 10mA 0.35 0.5 V
Input current
AC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 =470Ω, R2 = 1kΩ
LIMITS
SYMBOL PARAMETER FROM TO TEST CONDITION MIN TYP1 MAX UNIT
Pulse width
tCKH Clock2 High CK + CK – CL = 30pF 20 15 ns
tCKL Clock Low CK – CK + CL = 30pF 20 15 ns
tCKP Period CK + CK + CL = 30pF 55 45 ns
tPRH Preset/Reset pulse (I,B) – (I,B) + CL = 30pF 35 30 ns
Setup time5
tIS1 Input (I,B) ± CK + CL = 30pF 35 30 ns
tIS2 Input (through Fn) F± CK + CL = 30pF 15 10 ns
Input (through
tIS3 (I,B) ± CK + CL = 30pF 55 45 ns
Complement Array)4
Hold time
tIH1 Input (I,B) ± CK + CL = 30pF 0 –5 ns
tIH2 Input (through Fn) F± CK + CL = 30pF 15 10 ns
Propagation delay
tCKO Clock CK + F± CL = 30pF 15 20 ns
tOE1 Output enable3 OE – F– CL = 30pF 20 30 ns
tOD1 Output disable3 OE + F+ CL = 5pF 20 30 ns
tPD Output (I,B) ± B± CL = 30pF 25 35 ns
tOE2 Output enable3 (I,B) + B± CL = 30pF 20 30 ns
tOD2 Output disable3 (I,B) – B+ CL = 5pF 20 30 ns
tPRO Preset/Reset (I,B) + F± CL = 30pF 35 45 ns
tPPR Power-on/preset VCC + F– CL = 30pF 0 10 ns
NOTES:
1. All typical values are at VCC = 5V, Tamb = +25°C.
2. To prevent spurious clocking, clock rise time (10% – 90%) ≤ 10ns.
3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
4. When using the Complement Array tCKP = 75ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
10%
0V C1 C2 R1
OE
5ns tR tF 5ns
I0 BY
+3.0V
90% R2 CL
INPUTS In DUT
BW
10%
0V
BX BZ
5ns 5ns
CLK OUTPUTS
GND
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
NOTE:
C1 and C2 are to bypass VCC to GND.
Input Pulses
ÇÇÇÇÇ
Required delay between
I, B 1.5V positive transition of clock and
(INPUTS) tIH2
ÇÇÇÇÇ
0V
end of valid input data forced
at flip-flop output pins.
ÇÇÇÇÇ
tPD
VOH Delay between positive
ÇÇÇÇÇ
B
1.5V transition of clock and when
(OUTPUTS) VT tCKO
outputs become valid (with
VOL OE Low).
tOE2 tOD2
+3V
Delay between beginning of
I, B tOE1 Output Enable Low and when
(OUTPUT +1.5V +1.5V outputs become valid.
ENABLE)
0V
Delay between beginning of
Gate Outputs Output Enable High and
tOD1
when outputs are in the
OFF-State.
+5V
Delay between VCC (after
ÇÇÇÇÇ
4.5V
power-on) and when flip-flop
tPPR
outputs become preset at “1”
ÇÇÇÇÇ
VCC 0V (internal Q outputs at “0”).
ÇÇÇÇÇ
tPPR
Propagation delay between
ÇÇÇÇÇ
VOH tPD combinational inputs and
F outputs.
1.5V 1.5V
ÇÇÇÇÇ
(OUTPUTS)
VOL
Delay between predefined
tCKO Output Enable High, and
tOE2
+3V when combinational outputs
I, B become valid.
1.5V 1.5V
(INPUTS)
0V Delay between predefined
Output Enable Low and when
tIH1 tIS1 tOD2
combinational outputs are in
+3V
the OFF-State.
1.5V 1.5V 1.5V
CLK 0V
Delay between positive
tIS1 tCKH tCKL
transition of predefined
tCKP
tPRO Preset/Reset input, and
when flip-flop outputs become
Power-On Reset valid.
ÇÇÇÇÇÇ
+3V
I,B
1.5V
ÇÇÇÇÇÇ
(INPUTS)
0V
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
+3V
ÇÇÇÇÇÇ
CLK 1.5V
0V
(PRESET)
Q
(RESET)
tPRO
VOH
(RESET)
F
1.5V 1.5V
(OUTPUTS) (PRESET)
VOL
* Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge if tIS1
cannot be guaranteed by the user.
Asynchronous Preset/Reset
+3V
I, B
(LOAD SELECT) 1.5V 1.5V
0V
+3V
OE 1.5V 1.5V
0V
tOE1
+3V VOH
F
(INPUTS) VT (FORCED DIN) 1.5V
0V VOL
ÇÇÇÇÇÇÇÇÇÇÇÇÇ
tOD1 tIS2 tIH2
+3V
ÇÇÇÇÇÇÇÇÇÇÇÇÇ
CLK
ÇÇÇÇÇÇÇÇÇÇÇÇÇ
0V
tCKH
ÇÇÇÇÇÇÇÇÇÇÇÇÇ
tIH1
ÇÇÇÇÇÇÇÇÇÇÇÇÇ
Q (DIN)
LOGIC PROGRAMMING PLS159A logic designs can also be COMPLEMENT, INACTIVE, PRESET, etc.,
The PLS159A is fully supported by industry generated using the program table entry are defined below.
standard (JEDEC compatible) PLD CAD format detailed on the following pages. This
tools, including Philips Semiconductors’ program table entry format is supported by
SNAP, Data I/O Corporation’s ABEL and the Philips Semiconductors SNAP PLD PROGRAMMING AND
Logical Devices Inc.’s CUPL design design software package. SOFTWARE SUPPORT
software packages. To implement the desired logic functions, the Refer to Section 9 (Development Software)
All packages allow Boolean and state state of each logic variable from logic and Section 10 (Third-party Programmer/
equation entry formats. SNAP, ABEL and equations (I, B, O, P, etc.) is assigned a Software Support) of this data handbook for
CUPL also accept, as input, schematic symbol. The symbols for TRUE, additional information.
capture format.
(T, FC, L, P, R, D)n (T, FC, L, P, R, D)n (T, FC, L, P, R, D)n (T, FC, L, P, R, D)n
C C C C
C C C C
J Q J Q J Q J Q
ENABLED DISABLED M = ENABLED M = ENABLED
M M
K K K K
J–K OR D
A J–K ONLY • ACTIVE (Set)1 A INACTIVE (Reset) •
(CONTROLLED)1
J Q J Q J Q J Q
M = DISABLED M = DISABLED M = DISABLED M = DISABLED
K K K K
Tn Tn S S
B B
S, B S, B
OE OE OE OE
En En En En
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, FC, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, FC.
4. En = O and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of “OR” array links.
PROGRAM TABLE
AND OR CONTROL NOTES
1. The device is shipped with all links intact. Thus a back-
INACTIVE O ACTIVE A P, R, B(O) J/K F/F ground of entries corresponding to states of virgin links
I, B, Q H I, B(I), INACTIVE (Q = D) J/K or D A MODE IDLE O exists in the table, shown BLANK for clarity.
I, B, Q L Q(P) (controlled) 2. Program unused C, I, B, and Q bits in the AND array as (–).
CONTROL A
EA, B Program unused Q, B, P, and R bits in the OR array as (–) or
DON’T CARE – ENABLE (A), as applicable.
DISABLE – 3. Unused Terms can be left blank.
INACTIVE O TOGGLE O HIGH H 4. Q (P) and Q (N) are respectively the present and next states
(POL) of flip-flops Q.
GENERATE A SET H LOW L
C (Q = J/K)
PROPAGATE RESET L F/F MODE EB EA POLARITY
TRANSPARENT – HOLD –
T AND (OR)
E
THIS PORTION TO BE COMPLETED BY SIGNETICS
0
1
2
3
4
CUSTOMER SYMBOLIZED PART #
5
6
7
8
9
10
11
12
DATE RECEIVED
13
14
COMMENTS
15
CF (XXXX)
16
17
18
19
20
21
22
23
24
DATE
25
26
27
28
29
REV
30
31
TOTAL NUMBER OF PARTS
FC
PB
PURCHASE ORDER #
RB
PROGRAM TABLE #
LB
CUSTOMER NAME
PHILIPS DEVICE #
PA
RA
LA
D3
D2
D1
D0
PIN 5 4 3 2 9 8 7 6 19 18 17 16 15 14 13 12
Q
Q
OEB159
AND CAND C
ANDFC
OR
C
EXOR159
NOR S
B
X
P R
J Q F
M JKFF159
(4)
K CK
TNOUT159
P R
J Q F
M (4)
K CK
LNIN159
T31 T0 FC LDIN159
CK CLK
CK159