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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO.

4, JULY/AUGUST 1983 6655

Snubber Circuit for High-Power Gate Turn-Off Thyristors


HIROMICHI OHASHI, MEMBER, IEEE

Abstract-A snubber circuit calculation model for high-power gate sirable to include more device characteristics and circuit pa-
turn-off thyristors (GTO's) was proposed to consider problems which rameters for the GTO snubber circuit design consideration.
must be investigated for snubber circuit design. The calculated GTO This paper proposes a GTO snubber circuit calculation model
waveforms showed good agreement with experimental values obtained
by a GTO chopper circuit for both a resistive and inductive load case. and considers problems which must be investigated in the
Problems to be considered for the snubber design, such as voltage snubber circuit design.
spike reduction, maximum GTO anode current, and switching power,
were discussed using the calculation model. Design criteria for the II. CALCULATION MODEL
snubber circuit were successfully established, introducing allowable A. Fundamental Equations
maximum voltage spikes to avoid failures due to current crowding
during the GTO interval and excessive voltage applied over maximum A simple GTO chopper circuit, shown in Fig. 1, was used for
blocking voltage rating. Minimum switching power loss dissipated the GTO snubber circuit study. Anode voltage and current
inside the GTO and the snubber resistor was also calculated, taking waveforms that result in such a circuit are similar to those that
the design criteria into consideration. As results of the calculations,
the snubber circuit stray inductance was found to play an important result in most GTO power conversion circuits as well.
role in optimizing the minimum switching power loss, especially for Applying Kirchihhoffs law to the circuit in Fig. 1, the fol-
large anode current and large stray inductance in a main circuit. lowing fundamental equations are obtained:
di
I. INTRODUCTION EB =ez+Lsl * dt-+ea (1)
IT IS generally necessary to connect a snubber circuit across
di1
a power rectifier or thyristor to absorb the energy associated
with the recovery current in the devices and limit the resulting
el = -
dil+
dt
R -
i, (2)
voltage spike and rate of rise dv/dt. A snubber circuit also
plays an important role in determining the full capability of a ea =S2 dt± Reff is-L
di+ '
(3)
high-power gate turn-off thyristor (GTO). Although many
studies have been made on the snubber circuit for a conven-
tional rectifier or thyristor [1], [21, it is difficult to apply the ii = la ± Is ± Id (4)
results of these studies directly to GTO snubber circuit analy- I =ia~+is (5)
sis because of the following.
1) Voltage polarities across the devices during the turn-
off interval are opposite because of the differences in turn-off R5*.Rd
eR --Rs + Rd (6)
mechanisms, that is, forced commutation and the GTO method.
2) In addition to the purposes already mentioned, the GTO Here, the diode D, in the snubber circuit is divided into two
snubber circuit has another important purpose: to protect parts, i.e., an ideal diode and an effective resistance Rd. The
GTO's from failure due to current crowding during the GTO Reff value is an equivalent resistance in the snubber circuit
interval. which consists of Rs and Rd connected in parallel. The Qs
While a high-power GTO has been regarded as a new switch- value is a charge in the snubber capacitance Cs and is written as
ing device for many power conversion apparatuses, almost no
attempt has been made to analyze the GTO snubber circuit, dQs (7)
except the study made by Steigerwald, who discussed analyti- dt s
cally the voltage spike and rate of rise during the GTO interval
and related the energy dissipation in the snubber circuit to Substituting (3) and (5) into (1) yields
di/dt and dv/dt ratings for GTO's [3]. However, it seems de-
~di Q
(L,±LS2) -s+Reff
dt i~s +Cs
Paper IPCSD 83-8, approved by the Static Power Converter Com-
mittee of the IEEE Industry Applications Society for publication in
this TRANSACTIONS. Manuscript released for publication February 1, dia
1983. =EB-Ls, *-dt--el. (8)
The author is with Electron Devices Laboratory, Toshiba Research
and Development Center, Toshiba Corporation, 1, Komukai Toshiba
cho, Saiwai-Ku, Kawasaki 210, Japan. Anode voltage ea is given by solving differential equations

0093-9994/83/0700-0655$0l .00 © 1983 IEEE


656 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

the initiation of negative gate current to the time, t = t3 in


Fig. 2, at which the voltage across inductance L becomes larger
than the voltage across resistance R. Since el > 0 during this
period, the Df is reverse biased, and the current (id = Ird)
through the Df is negligibly small. Thus (4) and (5) are simpli-
fied, as follows:
11 =1 =1a ±s (11)
Using (2) and (1 1), (8) is changed into

(L +Ls1 +LS2) ds +(R±Reff)*


-

Cff is+
Fig. 1. GTO chopper circuit used for snubber circuit investigations.
dt Cs
dia
I t=o t
-EB R ia (L±+Ls,)
dt
(12)

2) Period B (el < 0): Period B is defined as the time from


t =t3. As diode Df is forward biased during this period, (8) is
also changed into the following under the assumption that el =
V2 Vf=O:
IATO e.
a~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
tE s (Ls, +LS2) dt+Reff °is+CCs
dt

-s t,- dia
It.
i
to0 'I I,3 t4 5 dt
(13)
; To
I , x m , V
A
F ~~~~~~~~~of4
B C. CalculationProcedure
Fig. 2. Typical voltage and current waveforms during gate turn-off In addition to the free-wheel diode bias conditions, the po-
interval.
larity for el, anode current ia, and equivalent resistance Reff
must be given for the calculations. As previously mentioned,
(7) and (8) for iS and Q5 and by substituting the solutions the whole GTO interval is divided into five periods, as is shown
into (3). Switching power P0ff and switching power loss in Fig. 2 for the descriptions of ia and Reff. The given ia and
Q0ff dissipated inside the GTO are written as Reff values for each period are substituted into (12) or (13),
according to the polarity of el, which is given by (2). These
Poff = ea ' ia (9) fundamental equations were numerically solved with the
Runge-Kutta method. The calculation procedures for each
period are described in the following.
Qoff Poff dt. (10) 1) Period I (to t < tl): The time from t = to to t = t1 in
Fig. 2 is defined as Period I and is usually termed the storage
Snubber circuit operations can be described with these funda- time. As anode current ia remains unchanged during this
mental equations. period, no changes occur in is and Q5, as well as ea. There-
Values el, ia, and R,ff, in addition to the other circuit pa- fore, the numerical calculation was carried out from the next
rameters, must be given to solve (7) and (8) for Qs and is. For period.
this purpose, as is shown in Fig. 2, the GTO interval is divided 2) Period II (t1 S t < t2): GTO saturation fails at t = tl,
into two periods, corresponding to the free-wheel diode Df with rapid anode current fall. This rapid decrease in the anode
bias conditions and is also divided into five periods, corre- current continues until t = t2, at which time the gate-cathode
sponding to GTO and Ds characteristics. junction recovers. This period, from t = t1 to t = t2, is defined
as Period II and is usually referred to as the fall time. Since the
B. Free- Wheel Diode Bias Conditions
anode current is shunted into capacitance Cs through diode
Equation (8) is changed into the following two forms, as D., anode voltage ea rises rapidly from this period.
the el polarities for each perio-d (Period A and Period B in Fig. The value Rd in this period is negligibly small, in compari-
2). It is postulated, for simplicity, that reverse current Ird and son with R., because diode D5 is forward biased. Hence (6) is
forward voltage drop Vf for the free-wheel diode, Df, are neg- simplified, as follows:
ligible (Ird = 0, Vf = 0).
1) Period A (el > 0): Period A is defined as the time from Reff = 0°- (14)
OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS 657
Anode current ia for this period was formulated with a where rd = n-(t5 - t4) and constant n depends on diode char-
curve fitting method. As a result of many curve fitting trials, acteristics [5].
the quadratic regression curve showed a good agreement with
experimental data on ia, for various GTO driving conditions. D. Comparison with Experiments
The experimental data were gathered using a high-power GTO, In order to examine the calculation model validity, anode
capable of turning off 600-A anode current [4] . An empirical voltage and current and switching power waveforms were cal-
equation, given with this method, is as follows: culated and compared with experimental data obtained with
the simple GTO chopper circuit shown in Fig. 1, using pre-
t2) viously mentioned high-power GTO's. One of the calculated
ia IATO
To 2 and measured waveforms for a resistive load case is shown in
Fig. 3. An input data list for the calculation is as follows:
where IATO is an anode current to be interrupted with nega-
tive gate current and To is defined as * circuit parameters: EB = 600 V, R = 1 Q2 (IATO = 600
A, L = 0 ,uH), Ls1 = 1.5 pH (measured), Ls 2 = 0.6 pH
To tf/ (IrO/'ATO) (16) (measured), R, = I0 Q;
* GTO and Ds characteristics: tf = 2.5 ps, I0 = 80 A,
Here tf = t2 t, as is shown in Fig. 2, and JrO is an anode cur-
-
Tr = 5 Ps, Qr = 100 C (n = 0.5).
rent at t t2. As is obvious from (16), the time t2 is written As is obvious in the figure, both results show good agreement
=

by t2 = To* l (IrO/IATO).
- with each other. The calculations for an inductive load case
3) Period III (t2 < t < t4): When the energy trapped in in- were carried out and also showed good agreements with the
ductance L is completely transfered to capacitance C. at t = experimental results.
t4, the current flow into C. stops, and then C. begins to dis-
charge back to the dc supply. The time from t = t2 to t= t4 III. MODEL APPLICATIONS
is defined as Period III. As diode D. is kept forward biased In the following, let us consider the problems which must
during this period, Reff is still given by (14). be investigated for determining the GTO snubber circuit de-
Because the gate-cathode junction recovers voltage block- sign such as the anode voltage waveform, the maximum anode
ing capability at t = t2, the cathode current stops after this current to be interrupted, and the switching power loss dis-
period, but the anode-to-gate current continues to flow, de- sipated at the turn-off interval.
caying exponentially as carrier concentration in the N-base
region is reduced by recombination. Thus the anode current A. Anode Voltage Calculations
after this period is written as follows (see Appendix I) Voltage spikes V1, V2, and V3 shown in Fig. 2 are impor-
tant ones for the snubber circuit design considerations. As
ia = IrO exp (-t2), (17) will be described later, V1 is closely related to the maximum
anode current to be interrupted.
V2 has to be limited to within maximum blocking voltage
where 'Tr is the anode current decay time and is closely related ratings. The smaller V2 results in a lower voltage stress on
to carrier lifetime in the N-base region. GTO. The negative voltage spike peak V3, during Period V,
4) Period IV(t4 < t < t5): As Period IV corresponds to the should be suppressed to as low a point as possible, to limit
diode D. storage time, Reff and ia are still governed by (15) the voltage rise rate for retriggering prevention. In the fol-
and (17). The numerical calculation for this period ends when lowing, anode voltages for an inductive load case are numeri-
is satisfies cally investigated. Unless otherwise specified, calculations
rt5 will be carried out under the conditions of EB = 600 V and
Qr fisdt, (18) IATO = 600 A.
t4 Anode voltage waveforms for various Cs values are illus-
trated in Fig. 4. As will be shown later, when Qr and Rs are
where Qr is storage charge removed from diode D. during this sufficiently small, such as Qr = 1 MiC and Rs = 10 Q2 for this
period. case, no negative voltage spike is observed. Hence most cal-
5) Period V (t > t5): Because diode D, begins to recover at culations are carried out under the foregoing conditions for
t = t5, the current through Rs increases rapidly with a de- convenience, because differences between individual calcu-
crease in the current through D. and Rd. From a practical lated curves become easy to compare. As is obvious in the
point of view, it was postulated that Reff changes exponentially .figure, V1 and V2 dependence on Cs becomes noticeable
from zero at t = t5 to the final value Rs. The Reff formulated with a decrease in Cs, especially when C5 is less than around
for this period is 2 pF. On the contrary, a further increase in Cs, to more than
around 2 jiF for this case, produces no appreciable effects on
Reff =RS I - exp -t5 both V1 and V2 suppression.
'rd/ Fig. 5 shows changes in anode voltage waveforms for var-
658 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

r,
0
x

x
r,

(U
a)

t [ts I
Fig. 3. Calculated anode voltage, current, and switching power waveforms for resistive load GTO chopper
circuit used for experiments.

Es 60OV 1800 E8=600V


Ls220.512H 1600 Cs 2osF
CSZO5SMF L -2mH L =2mH
1400
I,aF 1200 L82:.IH
0.3MLH
3juF r
000 Q8MuH
4MpF >I /H
>)0
A Rnn -~~~~~~~~~~

0 2 4 6 8 10 12 14

t [/AS) t tELSI
Fig. 4. Calculated anode voltage waveforms for various snubber Fig. 5. Calculated anode voltage waveforms for various snubber
capacitance conditions Ct. circuit stray inductance conditions LS2.

ious stray inductance Ls2 values in the snubber circuit, in- I MC. Hence a high-speed diode is advisable for the negative

dicating that V1 increases with increase in Ls2 and V2, on voltage spike reduction.
the contrary, increases with LS2 reduction. IATO influences on ea were calculated and are illustrated
Rs influences on anode voltage waveforms are shown in in Fig. 8. Fall time tf used for calculations is given by tf = A +
Fig. 6. Negative voltage spike V3 is seen to increase with R., B In (IATO), where A and B are constant. This empirical equa-
showing more than 1000 V/,us rate of voltage rise for the tion is formulated with the curve fitting method. It is seen that
case of R3 = 30 Q2 in the figure. This figure also indicates that V1 and V2 are almost in proportion to the increase in IATO-
V3 becomes negative whenRs exceeds 30 Q2. This phenomenon In addition to IATO, tf varies with gate driving conditions.
is undesirable not only for retriggering prevention but also Fig. 9 shows anode voltage waveform variations with tf for
for a GTO whose reverse blocking voltage rating is not IATO = 600 A. As is shown in the figure, V1 is greatly in-
guaranteed. fluenced by tf, whereas V2 is almost not affected by tf.
Calculated anode voltage waveforms for various Qr condi- As far as an inductive load is concerned, analytical solutions
tions are illustrated in Fig. 7, indicating that the negative volt- for ea give fairly good agreement with the detailed numerical
age spike reduces with a decrease in Qr. In this case, the nega- solutions, as is shown in Fig. 10. Curve A in the figure shows
tive voltage spike completely disappears when Qr is less than the anode voltage waveform for an inductive load case, which
OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS 659

EB=600V
Cs =2pF
Ls, 1.5pH
LS2=Q5,uH
L =2mH
Q, =1Q,Lc
12001
> 1000 2
1000[ 800 ~
~~~ ~ ~ 00
a) 600~ ~ ~ ~ ~ ~ 30

6001

400

2001

t E[.s) t £MsJ
Fig. 6. Calculated anode voltage waveforms for various snubber Fig. 8. Calculated anode voltage waveforms for various 'ATO condi-
resistor conditions Rs. tions.

1800 EB =600V
Cs =2/LF
1600 Ls,= 1.5MH
1400 LS2-0.4jtH
-L =2mH
1200 Rs =10Q

looc-

0
0) 80C I .Lc

105pc
.Lc a)
60C 50p,c
Or Ooptc
=

40C

20C
I
C
w0 2 4 6 8 10 12 14
*i SI t cps]
Fig. 7. Calculated anode voltage waveforms for various storage charge Fig. 9. Calculated anode voltage waveforms variations with fall time.
conditions Qr removed from diode Dt.
660 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

800 F
C50QljsF
3 Numerical (trr =
5ps) 600 0.5FF 2F

4UuI%r.
A 4O -A - g. -vi imax)
1.mn.1
*... .........t...
0
V)
200- -rSafe Operating Area

IL
OOC) 200 400 600 800
-- IATO [A]
Fig. 11. Experimental relations between IATO and V1 for various C.
2 4 6 8 10 12 14 conditions. Symbols *, A, and * denote gate turn-off failure points.
t [psl
O Experimental Data
Fig. 10. Comparison of analytical solution for ea with numerical
solution. 1000
Calculated Result

is calculated with the analytical method described in Appendix 800 - ~~~~~0


IL. Numerically calculated ea' which corresponds to curve A, is
shown as curve B. Obviously, from comparison of the two 0

E
600 -o~~~~~-8

curves, both curves agree well with each other until t t2.
_0I-
=

After t = t2, the difference gradually becomes large, because 400


0

the I40 and rT effects are not taken into account for the curve Safe
o Operating Area
A calculations. 200-
This comparison shows that the analytical method de-
scribed in Appendix II is widely suitable for an inductive load
application if a precise solution is not necessary. &, 3 2 4 5
Cs CEF]
B. Maximum Gate Turn-OffAnode Current Fig. 12. Calculated safe operating area for resistive load testing circuit.
Symbol o, denotes failure point.
The snubber circuit plays an important role, protecting
GTO's from gate turn-off failure. The relations between maxi-
GTO's to turn off in safety without a failure. V1 (max) for
mum GTO anode current without failure, IATO (max), and
the GTO's under the test may be 400 V.
snubber circuit conditions will be discussed in the following.
First of all, it is necessary to explain briefly the experi- Taking condition V1 < V1 (max) into consideration, the
relation between IATO (max) and Cs for the resistive load
mental results on the GTO failure which are used for snubber
testing circuit is numerically calculated and illustrated in Fig.
circuit design. The GTO failure was observed using a resistive
load GTO chopper circuit in such a way that IATO was in- 12, where the measured failure points are shown by the symbol
o. Most of the failure points, except one, are located outside
creased until the turn-off failure occurs by adjusting dc power
the shaded numerically calculated safe operating area. Hence
supply voltage under constant resistive load conditions. The we conclude, from the practical point of view, that the method
experimental relations between IATO and V1 for various C.
which prescribes V1 (max) is useful for safe operating area
conditions are shown in Fig. 11. Solid lines in the figure show
measured V1 dependence on IATO for the C. conditions. In calculations.
the figure, symbols 0, A, and * indicate GTO failure points;
Let us consider safe operating area for an inductive load
case. Since V1 for an inductive load is given by substituting
IATO (max) for the sample under test. As is obvious in the fig- t = tf into (31), the design criterion for safe operation is given
ure, measured failure points are distributed in the V1 range
from 400 V to 600 V, indicating that V1 shows a close rela- by
tion to the failure.
According to other investigations made using an infrared
microscopic technology and an exact one-dimensional model, V, (max) > (2 LS2 tf 3 *)To (20)
failure occurs when the temperature rise for the current
crowding region, just after the fall time, exceeds allowable Relations between IATO (max) and Cs for various Ls2 values
maximum temperature AT (max), which is approximately were calculated using (20) and the results are illustrated in
proportional to V1 under almost the same tf condition [6]. Fig. 13. As is obvious from the figure, when Ls2 is sufficiently
Since tf is almost constant for a rather wide range of small, IATO (max) increases alnost proportionally with an in-
IATO (tf = 2 3 ,ls for IATO from 200 A to 800 A for crease in C, Meanwhile, large LS2 and small Cs values greatly
the GTO's under test), it seems reasonable to limit V1 to reduce IATO (max). Note that a large C, is useless for
within a certain maximum voltage V1 (max), which allows IATO (max) enlargement without lowering LS2 .
OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS 661

EB=600V
1000 LSI= 23aH
tf =3/AsL
800k
<~~0.6,pLH
0
o
600 _-F I-
600k

400 _ 400k Safe Operating Area


(V2 (max)= 1200V)
200 Safe Operating Area 200 F

O 2 3 4 5 %.O0 1 3 4 5 2
Cs EpF] Cs [EfFJ
Fig. 13. Calculated safe operating area for various snubber circuit Fig. 14. Calculated allowable maximum IATO limited by rated block-
stray inductance, LS2 values for inductive load GTO chopper cir- ing voltage as function of Cs for various LS2 conditions.
cuit.

In addition to the turn-off failure protection purpose, V2


has to be limited to at least within maximum blocking voltage EB = 600V
rating VD RM . Since V2 for an inductive load case is given by IATO = 600A
(41), the requirement for voltage stress removal from the GTO LSI =22LH
is formulated into LS2 =0.6$H
r - =[.. F
VDRM >EB +IATO ( -SC *LS2). (21)
2 8 / 2MF-,9

These two equations are snubber circuit design criteria for an


inductive load GTO chopper.
Under the condition of V2 < 1200 V and with the same in- 2/(: AAL
put parameters as shown in Fig. 13, the relations between
IATO and Cs for various LS 2 values are calculated using (21)
and the results are shown in Fig. 14. As is apparent from com-
paring Figs. 13 and 14, C, is determined by (21), when Ls2 is
sufficiently small; that is, Ls2 is less than 0.2 ,F for this ex- 0 2 4 6 8 10 12 14
ample.
C. Power Loss Estimations Fig. 15. Calculated switching power waveforms inside GTO's for var-
ious C5 conditions.
Power loss problems related to the snubber circuit design
are power loss estimations inside the GTO and in the snubber
circuit itself. The calculated switching power waveforms in-
side the GTO are shown in Fig. 15. As is shown in the figure,
EB =600V
switching power loss Q0ff is divided into two parts, QA during IATO =600A
Period II and power loss QB after Period LI. The relations be- 05F L =2mH
tween Q,ff and C, for various LS2 values were calculated and
are illustrated in Fig. 16. The symbol + shows Q0ff for the 0.4k
minimum snubber capacitance Cs (min), which simultaneously
satisfied (20) and (21), indicating almost the same Q,ff. Since 0.3k
a large C. value accompanies much power loss in the snubber caO \
1%

N.
"s
".. ~ ~ ~ 4~
N,+ ,+
-LS2=02o
62H
circuit, as will be described later, for further decrease in Qoff 0.2k
it is necessary to make device characteristics such as tf, 1r, and 0.4pH
0.2,LH
I,O as small as possible. 0. V
Hereafter, let us consider the power loss Qsb dissipated in
the snubber circuit. The energy trapped in Ls 1 just before the 0 1 l.-
0 1 2 3 4 5
GTO interval and the energy stored in C5 during GTO off-state
are mainly dissipated by Rs in the snubber circuit. Thus Q5b Cs tELF)
is written as follows [3]: Fig. 16. Calculated switching power loss inside GTO for various LS2
conditions. Symbol + denotes Qoff for the allowable minimum Cs,
Qsb=I LS IATO 2+ * CS *EB2. (22) C. (min).
662 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

IATO=600A

0.n
C-,
L- *'S 0.6-
E
en
a,cn O 0.4

L- >K-,-e200A
0.2
" IOOA 0-
0 -00.2 0.4 0 0 I.2 0 02 0.4 0.6 0.8 1.0 1.2
0 0.2 0.4 0.6 0.8 1.0 1.2
LS2 [pHJ
LS2 EuH] Fig. 18. Calculated relations between Qsb (min) and LS2 for vari-
Fig. 17. Calculated relations between LS2 and minimum allowable ous LSI conditions.
switching power loss Qsb (min) inside snubber circuit for various
IATO values. ing during the GTO interval and excessive voltage application
over a maximum blocking voltage rating.
As is obvious from the equation, making Ls, and Cs as small Minimum switching power loss, dissipated inside the GTO
as possible for Qsb reduction is desirable. From this standpoint, and the snubber resistor, was also calculated, taking the de-
minimum snubber circuit power loss Qsb (min) determined by sign criteria into consideration. As the result of the calcula-
(20) and (21) was investigated. tions, it was found that the snubber circuit stray inductance
The relations between Qsb (min) and LS2 for various IATO plays an important role in optimizing the minimum switching
and Ls, conditions were calculated and results are illustrated power loss, especially for the case of large anode current and
in Figs. 17 and 18. In both figures, Regions A and B corre- large stray inductance in a main circuit.
spond to the area where Qsb (min) is determined by (20) and
(21), respectively. For large IATO and Ls, values, as shown APPENDIX I
in the figures, Qsb (min) values rapidly decrease with LS2 in ANODE CURRENT DESCRIPTION AFTER t = t3
Region A and, in turn, slightly increase with reduction in Ls2 The GTO reaches the nonsaturation condition at t = t1, thus
in Region B. However, on the contrary, when IATO and Ls1 excess minority charges Q1 and Q2 in the P and N base layers,
are small, Qsb (min) is mostly determined by (20). Note also respectively, are written after t = t, by the following charge
that Qsb (min) greatly decreases with reduction in Ls2 by control equations [7] as
making Ls, as small as possible. These results show that LS2
plays an important role in optimizing Qsb (min), especially dQ, Q1 _~ Q2 =
i--2-~-ig (23)
for the cases of large IATO and large Ls,. dt T1 Tc2

IV. CONCLUSION
dQ2 Q2 Q= (24)
dt r2 Tcl
A snubber circuit calculation model for high-power GTO
thyristors was proposed to consider problems which must be Ql Q2
investigated for the snubber circuit design. Fundamental equa- la
= J Ig+ik, (25)
Tci Tc2
tions which describe the snubber circuit operation were solved
numerically, dividing the GTO interval into two periods, cor- where
responding to free-wheel diode bias conditions, and also T1, 72 minority carrier lifetime in both base layers,
dividing them into five periods, corresponding to GTO and
snubber diode characteristics. Results of experiments using a c 17,,c2 minority carrier transient time in both base layers.
simple GTO chopper circuit showed good agreement with cal- Subscriptions 1 and 2 denote P and N base layers, respectively.
culated results for both inductive and resistive load cases. As the gate-cathode junction recovers at t= t2 and rI <
Problems to be considered for the snubber design, such as r2, it is assumed that ik = 0 and Q1 0 (Q2 > Ql) after t =
voltage spike reduction, maximum GTO anode current, and t2. Equations (23) and (24) are simplified, under these assump-
switching power, were discussed using the calculation model. tions, as follows:
Design criteria for the snubber circuit were successfully
established, introducing allowable maximum voltage spikes ia = =-' (26)
V1 (max) and V2 (max) to avoid failures due to current crowd- 72
OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS 663

dQ2 Q2 0 (27)
EB into (32) and using (33) lead to
dt r2
t3 =t2 (EB- A )-- (34)
Equation (27) is solved for Q2 . Substituting Q2 into (26) yields - ~~3CS IATO

As Df is forward biased after t= t3, el can be assumed


ia = exp (- ) (28) negligibly small. Combining (1) with (3), under the assump-
Ti T~~2 tions that Re = Oand el Vf =0 for t3 t t5, we obtain
Since ia = Q20/r2 at t-t2, di5 QS
EB (Ls, +LS2)+-
dt Cs
(35)
Q20
Iro Q=
72 where
APPENDIX II dOs
ANALYTICAL SOLUTIONS FOR AN INDUCTIVE is (36)
LOAD CASE dt

As QS = fi,.dt and Reff = 0 until t = t5, (3) is rearranged These equations can be solved for i5 as
as
is =IA TO cos (co(t t3)), (37)
dis 1 r
ea =Ls2-- + C isdt. (29) where
1
Initial load current il (=IATO) remains unchanged during the c = ( (38)
turn-off interval, due to load inductance filtering action, and NALS 1 +LS 2)Cs
Df is reverse biased until t = t3, thus is is written as
Substituting (37) into (29), we get
Is=IATO la, (30)

where ia is governed by (15) during Period II. Substituting ea =EB +IATO ( -coLs2) sin (co(t-t3)). (39)
(30) into (29) yields ea for Period II:
The t4 is given in the following, noting that is = 0 at t = (4
(31) in (3 7):
ea= (zLs2 * t +±;)j T 2
IT
t4 = t3 + (40)
Although ia for t > t2 is written by (17), it is postulated, for 2w
simplicity, that ia = IO = ° at t =t2 in (30), then isIATO.
Equation (29) is rearranged into the foUlowing under this as- By substituting (40) into (39), we
obtain
sumption:
V2 =EBs +IATO (y -LS2u t ) (41)
e C+IATO * (t t2)
(32)
ea =EC+ 0Cs The ts is also given by substituting (37) into (1 8) as
Here Ec is voltage across C5 at t = t2. As voltage across Cs is
given by the second term in (31), EC is written as follows:
4 ± 1 -i1 (i + - Qr
t (42)
I2 co 'IATO,
IATO . 't2 (33)
EC =
3Cs After t t5, C5 discharges back through RS, LS 1, LSI2, and Df
=

to the dc power supply. Since the voltage values across LS1,


Equation (32) describes ea from t = t2 to t t3,
= at which Df LS2, and Df are negligible, anode voltage across GTO approxi-
becomes forward biased because ea = EB. Substituting ea = mately equals EB.
664 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

ACKNOWLEDGMENT [7] M. Kurata, "A new CAD-model of a gate turn-off thyristor," in


IEEE Conf. Rec. Annu. IEEE Power Electronics Specialists Conf.,
The author wishes to thank Dr. K. Kishi and Dr. M. Kurata 1974, pp. 125-133.
for their support of this work, and Mr. K. Takigami and Mr. Y.
Yamaguchi for their cooperation in carrying out the experi-
ments. The author also wishes to thank Dr. K. Imai for his
very informative discussions during the work.
REFERENCES .lll_ Hiromichi Ohashi (M'8 1) was born in Hama-
matsu, Japan., on August 14, 1941. He received
[11 W. McMurray, "Optimum snubbers for,power semiconductors," the B.S. degree in electrical engineering from
IEEE Trans. Ind. Appi.. pp. 593-600, Sept./Oct. 1972. Hosei University, Tokyo, Japan, and the M.S.
[21 T. H. Barton, "Snubber circuits'for thyristor converters," in IEEE degree in electrical and electronics engineering
Conf. Rec. 1978 IAS Annu. Meeting. pp. 1086-1089. from Sophia University, Tokyo, in 1965 and
[3] R. L. Steigerwald, "Application techniques for high power gate 1969, respectively.
turn-off thyristors, " in IEEE Conf. Rec. 1975 IAS Annu. Meeting, In 1969, he joined the Toshiba Research and
pp. 165-174. Development Center, Kawasaki, Japan, where he
[4] H. Ohashi, M. Azuma, and T. Utagawa, "High voltage, high was initially concerned with optical sensing de-
current gate turn-off thyristor," Toshiba Rev., pp. 23-27, Nov.- vices development for an artificial satellite. Since
Dec. 1977. 1972, he has been engaged in developing new high-power semiconductor
[5] G. N. Revankar and P. K. Srivastava, "Turn-off model of an devices, such as gate turn-off thyristors and light triggered thyristors. He
SCR," IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECT-22, is presently the Senior Researcher in the Power Semiconductor Devices
no.. 4, pp. 507-510, 1975. Group of the Electron Devices Laboratory.
[6] H. Ohashi and A. Nakagawa, "A study of GTO turn-off failure Mr. Ohashi is a member of the Institute of Electrical Engineers of
mechanism," in 1981 IEDM Tech. Dig., pp. 414-417. Japan.

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