DESIGN OF RELIABLE HIGH VOLTAGE AVALANCHE TRANSISTOR PULSERS’

E. Stephen Fulkerson and Rex Booth

Lawrence Livermore National Laboratory, P.O. Box 808, M / S L-54, Livermore, CA 94551
and
Kaiser Engineering, P.O. Box 808, M / S L-375, Livermore, CA 94551

Abstract
The authors have developed avalanche transistor based pulsers for use as pockel cell drivers and for impulse radar work. The output voltages
range from 1 to 8kV, with rise times of 100 to 200 picoseconds and repetition rates in excess of 1kHz. Several of these units have been in
service for over a year with no failures. The design of these units is discussed in detail, including circuit design, component selection,
diagnostics, and the all important physical layout.
Iotroduction There is no voltage applied to the output until the final stage
(Q5) switches, this means rise time is basically determined by how
The purpose of this paper is to provide a set of guidelines that fast the last stage transistor(s) turns on. IRise times under loops

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should provide a starting point for the design of high performance have been obtained.
avalanche transistor based pulsers. No attempt has been made to
provide a complete design as each application will require a
somewhat different configuration. The basic operation is discussed
followed by the detailed information required to determine

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component values for each stage. As with any very high speed
circuit layout is vital. Techniques for minimizing stray inductance
and capacitance are presented. Finally, several methods are
presented dealing with the difficult problem of diagnosing the
operation of these units.
l a
Theorv of ODeratiQn
The basic circuit is a string of avalanche transistors and
capacitors from the high voltage supply to ground (See Figure 1). In Q5
order to keep stray inductance to a minimum the capacitors are
$9-
OUTPUT
formed by pads directly on the printed circuit board (C2, C3). The
-it+
inductance of the transistors and the PC capacitors form a
transmission line that tapers from a high impedance (50-2OOQ) at
the high voltage output end to about 1-2Q at the low or triggered
end. The bottom (lowest voltage) stage is triggered via a small
femte bead pulse transformer(T1). This places the collectors of the
first stage (Ql, Q2) near ground potential, resulting in about 600V IIIII
I I I I I I
I ‘C2
-
‘C3
c4

.
collector to emitter across the second stage (Q3, Q4). The second
stage transistors suffer a non-destructive avalanche breakdown due
\\
‘.
CVFVTERMINATION

L
A
1 1 1
DOUBLE SIDED PC BOARD
/
,/’
-/

to this over voltage. As each stage turns on the next “sees” an even
greater over voltage resulting in a “crack -the-whip” effect that
results in faster rise times and shorter stage to stage delay.
Marx bank type designs have the advantage of lower supply
voltages, but at the cost of a much more stored charge. The rational
for using a single long string is to reduce the total stored charge of
the system, this prevents damage to the pulser due to self triggers or
breakdowns. A secondary benefit is that for low repetition rates
very little power is required to operate the pulser. Problems with
corona have limited our current designs to about 12kV dc supplies,
replacement of the PC board based capacitors with surface mount
chip capacitors should allow operation to 15kV.
A zener diode across each transistor limits the DC voltage per stage
to about 320V. This keeps the individual transistors out of their
break down regions which produces more consistent operation
from stage to stage and produces a circuit which is less prone to pre-
fire on noise.
Note that the emitters of the first (triggered) stage are connected
to ground through some paralleled resistors (labeled
CVIUTERMINATION). These resistors serve to terminate the
tapered transmission line in its characteristic impedance. As each
stage in the string triggers, a pair of waves are launched along the
line. One wave travels towards the output and serves to help trigger
the next stage, the second proceeds towards the low or triggered end
of the line. If this wave is not absorbed a large reflection is sent
back up the string which can sum with waves from other switch
closures to cause locally high currents and voltages resulting in
device failures. These reflections which show up clearly in both
SPICE simulations and in current viewing resistors, may be two to
three times the maximum current the transistors will tolerate. The
addition of the termination resistors has resulted in greatly improved
reliability and pulse fidelity. This technique is believed to be unique
to these LLNL designs.
101
Figure 1. Simplified Schematic Diagram
ComDonent Sel e c ~ m
The avalanche transistors used are Zetex FMMT-417’s. These
are surface mount (SOT-23) versions of the Zetex ZTX415 (TO-92)
silicon NPN avalanche transistor. The 417 designation indicates that
these units have been pre-selected by Zetem (at extra cost) t9 have a
guaranteed minimum VCBOof >325V vs. the standard 266V of the
415 part number. The small surface mount package has lower lead
inductance than the TO-92 package and allows for a much more
compact overall physical layout further reducigg unwanted circuit
inductance. A 320V (1N5111) zener diode is Nralleled across each
stage to ensure that none of the transistors are operating in their
unstable zener region.
These devices are rated for a peak collector current of 60A at a
maximum pulse width of 20ns. For shorter pulse widths (Ions) the
manufactures specification sheets indicate maximum peak currents
of 170A can be obtained. However in these extremely fast rise time
circuits (tr<200ps) we have found that device current must limited to
peak currents of less than 50A for even short (Ins) pulse widths. If
one is willing to sacrifice some rise time ]performance and longer
delay times, capacitance can be added in parallel with each stage to
limit the peak dv/dt and improve device reliability.
. .
ircuit Desrgn
As noted above, the string of transistors and capacitors form a
tapered transmission line. The impedance of the final stage is
matched to the load impedance, if the pulser is to drive a 50 ohm

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 load then the capacitance of the final stage is adjusted to react with
the internal inductance of the avalanche transistors (=2nH) to give a
nominal 50 ohm output impedance. It is important to have a smooth
change in impedance along the line, abrupt changes result in
reflections that can cause device failure, and degrade the output
wave form.
The impedance at the low or triggered end of the line is kept low
to provide enough capacitance to keep the “bottom” of the stack on
until the full string has erected. Generally the peak current through
any given transistor is kept below 4 0 A . At currents above 50A per
device we begin to see increased transistor failures. If currents
greater than 50A per stage are required the avalanche transistors may
be paralleled. Tests using inductive probes indicate that there is little
or no current “hogging” in these units. The exception to this rule is
the triggered stage, the series base resistors ( R l , R2) may be
“tuned’ using an inductive loop probe to observe the relative peak
current and timing of each of the triggered units.
Determination of a schedule of capacitance for the string is fairly
simple. First, the overall current through the string is determined.
For example, let us assume lOOA into a 50R resistive load. This
implies a 5kV output pulse. Assuming that 1/2 of the dc voltage for
each stage (320V) will be applied to the load we will need 32 stages.
The triggered stage has a rise time of about Ins, and swings 250V.
This gives a first stage capacitance (Cl) of 400pf. (see equation
below) Note that due to the amount of board space required for this
large a capacitor, a conventional surface mount ceramic unit would
be used for this stage.
Ins
i = C-dv + C = i- dt j C = 10~-= 40oPf
dt dv 250v
The last stage should have an impedance of 50R to match the
load. Assuming the inductance of each avalanche transistor is 2nH,
and two paralleled transistors to keep the current at or below 50A
per device, the capacitance for the last stage is 0.4pF.
The impedance of the first stage (assuming 5 transistors for the
triggered stage) is about IQ. (The large number of transistors in the
first stage serve to further decrease the inductance, and thus improve
the rise time and delay, of the slowest stage in the unit.) A smooth
line is projected from 1 to 50f2and the capacitance for each of the
remaining 30 stages is calculated using the formula above.
Operating at high repetition rates present some additional
problems. The ultimate limiting factor is the pulse current heating of
the transistors. For short pulses this limit appears to be in the
lOOkHz range. The parallel zener diodes may set a lower limit. As
the charging current through the diodes increases the voltage drop
across them increases until the point that the transistors begin to
enter their self breakdown region. If the pulser is to be started and
stopped then the zeners must also be able to dissipate a fair amount
of dc power, the solution to go to active pulse charging systems
with their additional complexity. Overall power efficiency from
supply to pulse output is in the range of 25 to 50 percent.
Phvsical Lavout
When trying to produce transitions in the hundred picosecond
range the control of all unwanted inductance and capacitance is
vitally important. One of the major sources of inductance in
conventional components are the leads. The use of surface mounted
devices for avalanche transistors, the triggered stage capacitors, and
the CVR eliminates most of this stray inductance, plus allows for
the construction of very compact circuits with further serves to
reduce stray capacitance and inductance. The zener diodes are part
of the DC bias circuit and thus conventional leaded components are
used.
After the first stage or two, the capacitance to ground for each
stage is provided by parallel plate capacitors (labeled *C2 and *C3)
formed by varying the area of the pads on a double sided printed
circuit board. These capacitors are very low in series inductance and
have very good high voltage characteristics. The high voltage hold
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off is determined by the bulk dielectric strength of the PC board it
self.
There are several drawbacks associated with using the PC board
for capacitors. 1) For values greater than about lOOpf they occupy
large amounts of board area. 2) To try to compensate for this the PC
board may be made of thinner material, but this results in a
mechanically fragile board which may require reinforcement, and
for very thin boards, may compromise the high voltage hold off
characteristics. 3) For very small values of capacitance (around a
picofarad or less) the required land size may be so small that there
may not be enough area to mount the avalanche transistors and their
bias networks. As an alternative to very small pads at the high
voltage end of the string, the mounting pads may be kept at constant
size and the ground plane on the back of the board may be mounted
on a dielectric wedge (see Figure 2). The taper of the wedge is set to
produce the required capacitance schedule without compromising
pad size or dielectric integrity. The downside of this technique is, of
course, added construction complexity.
Diagnostics
Diagnostics for these units are very difficult. We are trying to
measure multiple kilovolt transitions in picoseconds in high
impedance circuits which may have a designed in capacitance of one
picofarad or less. For load impedances of 50Q we use high speed
high voltage attenuators (usually from Barth Electronics) to observe
the output pulse. E we wish to observe the operation of intermediate
stages, or if the load is a high impedance, conventional high
impedance probes are completely inadequate due to their very
limited bandpass and relatively large capacitance.
Mounting Pad I Avalanche
Capacitor Plates Transistors
Ground Plane / -
Dielectric
Wedge
Figure 2. Printed Circuit Board Cross Section Showing
Dielectric Wedge
One of our most effective measurement techniques has been the
use of a small current viewing resistor (CVR) located at the
triggered end of the string. We are able to view the series current in
the string providing a time history of the pulser before and after the
output pulse is delivered to the load. Initially ten 1R 1/8W surface
mount resistors were paralleled to form a 0.lQ CVR. As each stage
in the string “erects” a pulse of current is observed in the CVR,
from this measurement we can measure the peak current in the string
and the stage to stage delay. This is the measurement that reveled the
need to terminate the triggered end of the line. Current reflections
could clearly be seen that went away completely when the value of
the CVR was increased to the characteristic impedance of the low
end of the line.
The major limitation of the CVR is that it only observes the total
series current of the string. There are also local circulating currents
in each stage that do not appear at the CVR. To observe the
operation of individual stages we use an inductive probe. In it
simplest form this is just a piece of small rigid co-ax with the center
conductor formed in to a small loop to the shield and insulated with
a drop of epoxy resin. The probe measures the dB/dt of a very local
area near its tip, the data is acquired into a computer and is digitally
integrated to produce the current wave form at the point of the
measurement.
These probes can easily be calibrated against a know source and
are very useful in searching for locally high peak currents, and for-
following the progress of reflections up and down the line. An
improved version of the inductive probe is in development that will
have better common mode rejection characteristics to reduce the
effects of capacitive coupling into the probe.
The CVR/termination resistor is useful in determining how well
the string is matched to the output load. The wave form across the
CVR can be interpreted like a TDR trace. If the load impedance is
higher than that of the string there is a sharp drop in current at
switch out time. Conversely, a low impedance load results in a
marked increase in observed current. The true effective impedance
of the string can be determined by loading the output with various
resistive loads until a value is found that results in no (or minimum)
change in CVR current at switch out time.
103
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Conclusior\
Very high performance reliable pulsers can be designed using
avalanche transistors. Care must be taken to limit reflections and
keep the current per avalanche device lbelow 50A. The use of
surface mount devices and printed circuit capacitors minimize
unwanted inductances and capacitances. The use of current viewing
resistors and inductive current probes allow the diagnosis of circuit
operation.
Work performed under the auspices of the U.S. Department of
Energy by the Lawrence Livermore National Laboratory under
Contract W-7405-ENG-48.