What's New in Allegro PCB Editor v16.3

I N V E N T I VE
What’s new in Allegro PCB Editor v16.3

Areas of improvements
• Design Miniaturization
• Productivityy and Ease of Use Improvements

p
• Improvements
p for design
g of high-speed
g p signals
g
• Design For Manufacturing improvements
(c) 2009 - Cadence Design Systems, Inc. All rights reserved worldwide
1. HDI Improvements
2. Improvements for Rigid-Flex designs
3. 3D Viewer
• Productivity and Ease of Use Improvements
• Improvements for design of high-speed signals
Design Miniaturization: HDI Improvements
Exclusive micro-via
micro via stacking rules
• 16.3 adds a control to
limit stacking with similar
via types
– Micro-micro
– But disallow micro-core
16.2 16.3
• Removal of Unused B/B vias in
stack
– Gloss utility removes unused
vias in a stack
– Frees up routing real estate
– Removes stub effects on via
– Can be tied to a function key
Design Miniaturization: HDI Improvements
Via list DRCs and Viewer
• Via List DRC
– Special micro vias
vias,
skip vias can be
confined to a region
(e.g., BGA boundary)
• Via List Viewer

– Graphical
p cross
section view of the
selected vias
1. HDI Improvements
2. Improvements for Rigid-Flex designs
3. 3D Viewer
• Productivity and Ease of Use Improvements
• Improvements for design of high-speed signals
Design Miniaturization
Flex Design – Multi
Multi-line
line generator
• New floorplanning utility designed to
quickly create a bus path across the
flex section of a rigid-flex design
– Option to hug contour of flex outline or
route keep in
• Follow-up by completing routes to

logical pins
• Can be used for Rigid boards as well
Flex Design – Contour hug
• Interactive Route enhancement
designed to guide your route(s)
along either of the following contour
objects:
– Route Keepp In
– Adjacent cline
• Use with single

g or multi-line routing
g
– Flex routing
– Off angle against fabric weave
Flex Design – Editing of clines with arcs
• New Slide option “Enhanced
Arc Editing”
Editing on RMB
• Designed to work with minimal
options
• Predictable behavior based on
selection of
– Arc
– 90 degree corner
– Tangent segment
• Arcs with Segments option
Allegro 3D viewer
• Reduce unnecessary iterations
with MCAD
• View board design in 3D
• Use multiple place bounds with
different heights
• Multiple windows, Spin, Pan,
Zoom functions
• Di /Filtered
Dim /Filt d view
i option
ti
• Plan micro via breakouts

• View micro vias, through hole
vias and traces on different
layers
– View one net with HDI micro via
breakout
Value Prop - Miniaturization
• Shorter time to create dense designs that result from

miniaturization needs
• Multi-line generator with contour hug

• Interactive
I t ti etch
t h editing
diti improvements
i t for
f connectt lines
li
with arcs
• 3D design viewer offers easy way to view
– 3D component profile to possibly avoid an iteration with
mechanical designer
– Plan HDI micro-via
micro via breakout patterns
• Unique Constraint Driven HDI design flow
Value Proposition
Constraint-Driven HDI design flow
1. Shortens time to create HDI

designs
Constraint-Driven
HDI Design Flow
HDI Productivity Features
2. Ensures designs
g created
me
gn Cycle tim
Non CD Flows
adhere to HDI and electrical
constraints
– N
No manuall error prone checking
h ki
Desig
Allegro
– No Physical Prototype iterations
% of nets constrained Æ
due to high-speed or HDI
constraints
Value Proposition – Constraint-Driven HDI design flow
Beta customer quote from PCB 16.2 launch
n “NVIDIA designs require a PCB design solution that offers a robust
constraint-driven PCB design flow,” said Greg Bodi, senior manager,
System
y Design,
g , NVIDIA. “Having g HDI capabilities
p that are driven by
ya
constraint-driven flow is necessary for us to meet our time-to-market
objectives. With the significant improvements for HDI designs in the Allegro
PCB16.2 release, we expect to shave off up to 25 percent from the PCB
layout design cycle time for our designs
designs.”
o Charlie Davies, Principal ECAE Application Engineer at Harris Government

Communications Systems Division:
"We are part of a small, diversified group of customers providing feedback
to Cadence on improvements in Allegro 16.2. The biggest improvement in
the Allegro 16.2 release has been in the area of designing PCBs using a
build-up process with High-Density Interconnects. With the addition of
capabilities for HDI, Allegro provides an excellent constraint-driven HDI
design Flow. These advances along with other ease-of-use improvements
will significantly improve our ability to execute our most difficult HDI design
challenges, while reducing our design cycle time."

p
• Improvements
p for design
g of high-speed
g p signals
g
Productivity and Ease of Use improvements
1. Shapes quality of results improvements
2 DRC multi-threading
2. multi threading
3. Placement replication now handles etch elements

(Cli
(Clines, vias,
i shapes)
h )
4. Pad Entry / Exit improvements
5. Improvements in placement applications
6. Flip board
7 Customizable
7. C t i bl D Data
t ti
tips
Circuit replication improvements in 16.3
• 16.2 limited to p
placement only
y
• New in 16.3
– Support of metal (clines,
vias shapes)
vias,
– Alignment of group circuits
– Circuit Refresh/Update
– Use model improvements
• Mirror & Rotate
Productivity & Ease of Use Enhancements
Enhanced Pad Entry/Exit
• Interactive routing enhancement
designed to improve pad-line
pad line
entry/exit direction
• Works on circle
circle, rectangle
rectangle,
oblong pads
• E
Exits
it perpendicular
di l tto pad
d edge
d
or a radius
– Does not produce an acute angle
• Prevents bend points within

same net p
pad to line distance
Component placement improvements
• Use of arrow keys to move 1
grid unit
• Context sensitive editing

g
support for group objects
(create/disband) Move comp 1 mil to meet min DFA rule
• Change pick point of symbol

during move operation
• RMB mirror support for move
Ease of use improvements
Flip Board
• Valuable for debugging real boards
• Editing text on the flipped side
• View and Full Edit capability
• Flip/Mirror board about Y axis

• Simple toggle on-off command
• Flip Mode indicator
• Open GL dependent
• Available in Allegro Viewers
• Customizable Data Tips
– User configurable data tip display
– Display property name, value or
both

p
• Improvements
p for design
g of high-speed
g p signals
g
High-Speed improvements
Diff Pair Dynamic Phase Control
• Standards based interfaces
require “Running
Running skew rules
require compensation within
specified distance”
– Typical 600 mils
• Current dynamic phase measures

at the coupling events
• Phase matching of Diff Pairs for

high-speed interfaces required at
trace bend ppoints across the
driver-receiver path
High-speed improvements
New constraints for high
high-speed
speed interfaces
• Matched Vias
– Ensure an equal quantity
of vias across members of
buses, classes, matched SATA 3.0 – 6 Gbps (2008)
groups & diff pairs HyperTransport 3.1 – 6.4 Gbps (2008)
PCI Express
E 3.0
3 0 – 8 Gb
Gbps (2009)
– Required for standards
based interfaces such as
DDR2, DDR3, XAUI
• Max Via
– Prevent bubble up of most
conservative
i value
l to XXnet
level

p
• Improvements
p for design
g of high-speed
g p signals
g
Design for Manufacturability
Solderpaste Clearance Check
• Solderpaste openings are not always
scaled to soldermask openings
– They can be larger to accumulate more
paste on a part for a better solder joint
connection
– If there is not a sufficient solder paste gap

between objects, paste could short to other
objects
• Design Level Check
• Clearance option
• Inter/Intra symbol checking
Negative Plane Slivers
• Minimum web check between

elements on negative planes
• Undetected slivers may peel off
during etching or may not be
adequate to provide proper
current
• Design Level Check
• Restricted to wysiwyg negative
planes only
Pin to Route Keepout
• Design
g level DRC detects
presence of “pins” located in
a Route Keep Out Area
• Located in Design Modes

constraint form

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I N V E N T I VE

What’s new in Allegro PCB Editor v16.3

• Productivityy and Ease of Use Improvements

• Design For Manufacturing improvements

• Productivity and Ease of Use Improvements

• Improvements for design of high-speed signals

• Design For Manufacturing improvements

• Via List Viewer

• Productivity and Ease of Use Improvements

• Improvements for design of high-speed signals

• Design For Manufacturing improvements

• Follow-up by completing routes to

• Can be used for Rigid boards as well

• Use with single

• Plan micro via breakouts

• Shorter time to create dense designs that result from

• Multi-line generator with contour hug

• Unique Constraint Driven HDI design flow

1. Shortens time to create HDI

HDI Productivity Features

o Charlie Davies, Principal ECAE Application Engineer at Harris Government

• Productivityy and Ease of Use Improvements

• Design For Manufacturing improvements

3. Placement replication now handles etch elements

4. Pad Entry / Exit improvements

5. Improvements in placement applications

• Prevents bend points within

• Context sensitive editing

• Change pick point of symbol

• RMB mirror support for move

• View and Full Edit capability

• Flip/Mirror board about Y axis

• Available in Allegro Viewers

• Productivityy and Ease of Use Improvements

• Design For Manufacturing improvements

• Current dynamic phase measures

• Phase matching of Diff Pairs for

• Productivityy and Ease of Use Improvements

• Design For Manufacturing improvements

– If there is not a sufficient solder paste gap

• Design Level Check

• Inter/Intra symbol checking

• Minimum web check between

• Located in Design Modes

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