Professional Documents
Culture Documents
Document Disclaimer
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products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered
by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of
Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the
express written approval of ZiLOG, use of information, devices, or technology as critical components
of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this
document under any intellectual property rights.
PS019906-1003 Preliminary
Z8F642x/Z8F482x/Z8F322x/Z8F242x/Z8F162x
Z8 Encore!®
iii
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset and STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timer 0-3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer 0-3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Watch-Dog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . 97
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 103
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . 104
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Multiprocessor (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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List of Figures
Figure 1. Z8 Encore!® Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8Fxx01 in 40-Pin Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Z8Fxx21 in 44-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . . 8
Figure 4. Z8Fxx21 in 44-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . 9
Figure 5. Z8Fxx22 in 64-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . 10
Figure 6. Z8Fxx22 in 68-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . 11
Figure 7. Z8Fxx23 in 80-Pin Quad Flat Package (QFP) . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Power-On Reset Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 9. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 14. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . 102
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . 102
Figure 16. UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . . . . 106
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 108
Figure 18. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 110
Figure 19. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 121
Figure 20. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 21. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System . . . 126
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System . . 127
Figure 24. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 25. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 26. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 27. 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . 142
Figure 28. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 143
Figure 29. Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 144
Figure 30. Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 145
Figure 31. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 163
Figure 32. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 33. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
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List of Tables
Table 1. Z8 Encore!® Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Z8 Encore!® Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Pin Characteristics of the Z8 Encore!® . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Z8F642x Family Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Z8F642x Family Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Reset and STOP Mode Recovery Characteristics and Latency . . . . . . . . . . 44
Table 9. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 10. STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . 48
Table 11. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 13. Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 15. Port A-H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 16. Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 17. Port A-H Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 18. Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 19. Port A-H High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 20. Port A-H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 21. Port A-H STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . 61
Table 22. Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 26. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 27. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 71
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 30. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 31. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 32. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 33. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 73
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Manual Objectives
This Product Specification provides detailed operating information for the Z8F642x,
Z8F482x, Z8F322x, Z8F242x, and Z8F162x devices within the Z8 Encore!® Microcon-
troller (MCU) family of products. Within this document, the Z8F642x, Z8F482x,
Z8F322x, Z8F242x, and Z8F162x are referred to collectively as the Z8 Encore!® or the
Z8F642x family unless specifically stated otherwise.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with
microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Courier typeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is pre-
sented in upper case.
• Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
• Example: R1 is set to F8H.
Brackets
The square brackets, [ ], indicate a register or bus.
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• Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant
bit, and R1[0] is the least significant bit.
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some com-
bination of smaller registers, buses, or individual bits.
• Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
• Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
• Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the
contents of the memory location at address 1234h.
xviii
• Example 2: The Master can generate a Stop condition to abort the transfer.
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that all users understand the following safety terms, which are defined here.
Caution: Indicates a procedure or file may become corrupted if the user does not fol-
low directions.
Trademarks
ZiLOG, eZ8, Z8 Encore!®, and Z8® are trademarks of ZiLOG, Inc. in the U.S.A. and other
countries. All other trademarks are the property of their respective corporations.
Introduction
The Z8 Encore!® MCU family of products are a line of ZiLOG microcontroller products
based upon the 8-bit eZ8 CPU. The Z8F642x/Z8F482x/Z8F322x/Z8F242x/Z8F162x
products, hereafter referred to collectively as Z8 Encore!® or the Z8F642x family. The
Z8F642x family adds Flash memory to ZiLOG’s extensive line of 8-bit microcontrollers.
The Flash in-circuit programming capability allows for faster development time and pro-
gram changes in the field. The new eZ8 CPU is upward compatible with existing Z8®
instructions. The rich peripheral set of the Z8 Encore!® makes it suitable for a variety of
applications including motor control, security systems, home appliances, personal elec-
tronic devices, and sensors.
Features
• 20MHz eZ8 CPU
• Up to 64KB Flash memory with in-circuit programming capability
• Up to 4KB register RAM
• 12-channel, 10-bit analog-to-digital converter (ADC)
• Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
• I2C
• Serial Peripheral Interface
• Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
• Up to four 16-bit timers with capture, compare, and PWM capability
• Watch-Dog Timer (WDT) with internal RC oscillator
• 3-channel DMA
• Up to 60 I/O pins
• 24 interrupts with configurable priority
• On-Chip Debugger
• Voltage Brown-out Protection (VBO)
• Power-On Reset (POR)
Part Flash RAM 16-bit Timers ADC UARTs 40/44-pin 64/68-pin 80-pin
Number (KB) (KB) I/O with PWM Inputs with IrDA I2C SPI packages packages package
Z8F1621 16 2 31 3 8 2 1 1 X
Z8F1622 16 2 46 4 12 2 1 1 X
Z8F2421 24 2 31 3 8 2 1 1 X
Z8F2422 24 2 46 4 12 2 1 1 X
Z8F3221 32 2 31 3 8 2 1 1 X
Z8F3222 32 2 46 4 12 2 1 1 X
Z8F4821 48 4 31 3 8 2 1 1 X
Z8F4822 48 4 46 4 12 2 1 1 X
Z8F4823 48 4 60 4 12 2 1 1 X
Z8F6421 64 4 31 3 8 2 1 1 X
Z8F6422 64 4 46 4 12 2 1 1 X
Z8F6423 64 4 60 4 12 2 1 1 X
Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8 Encore!®.
XTAL / RC On-Chip
Oscillator Debugger
POR/VBO
eZ8
Interrupt & Reset WDT with
CPU
Controller Controller RC Oscillator
System
Clock
Memory Busses
Register Bus
IrDA
Flash
Memory RAM
GPIO
• Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
• Compatible with existing Z8 code
• Expanded internal Register File allows access of up to 4KB
• New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
• Pipelined instruction fetch and execution
• New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
• New instructions support 12-bit linear addressing of the Register File
• Up to 10 MIPS operation
• C-Compiler friendly
• 2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail-
able for download at www.zilog.com.
Flash Controller
The Flash Controller programs and erases the Flash memory.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.
I2C
The inter-integrated circuit (I2C®) controller makes the Z8 Encore!® compatible with the
I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA)
line and a serial clock (SCL) line.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and oper-
ate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM
modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.
Interrupt Controller
The Z8F642x family products support up to 24 interrupts. These interrupts consist of 12
internal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable
interrupt priority.
Reset Controller
The Z8 Encore!® can be reset using the RESET pin, power-on reset, Watch-Dog Timer
(WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore!® features an integrated On-Chip Debugger (OCD). The OCD provides a
rich set of debugging capabilities, such as reading and writing registers, programming the
Flash, setting breakpoints and executing code. A single-pin interface provides communi-
cation to the OCD.
DMA Controller
The Z8F642x family features three channels of DMA. Two of the channels are for register
RAM to and from I/O operations. The third channel automatically controls the transfer of
data from the ADC to the memory.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8F642x
family product line.
Table 2. Z8 Encore!® Package Options
Pin Configurations
Figures 2 through 7 illustrate the pin configurations for all of the packages available in the
Z8F642x family. Refer to Table 3 for a description of the signals. Please note that Timer 3
is not available in the 40-pin and 44-pin packages.
PA1 / T0OUT
PA4 / RXD0
PD4 / RXD1
PA5 / TXD0
PD5 / TXD1
PC5 / MISO
PC4 / MOSI
PA3 / CTS0
PA6 / SCL
PA2 / DE0
PD3 / DE1
6 1 40
PA0 / T0IN 7 39 PA7 / SDA
PD2 PD6 / CTS1
PC2 / SS PC3 / SCK
RESET VSS
VDD VDD
VSS 12 34 PC7 / T2OUT
PD1 PC6 / T2IN
PD0 DBG
XOUT PC1 / T1OUT
XIN PC0 / T1IN
VDD 17 29 VSS
18 23 28
PB3 / ANA3
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PB6 / ANA6
PB7 / ANA7
PB2 / ANA2
VREF
AVDD
AVSS
PA1 / T0OUT
PA4 / RXD0
PD4 / RXD1
PA5 / TXD0
PD5 / TXD1
PC5 / MISO
PC4 / MOSI
PA3 / CTS0
PA6 / SCL
PA2 / DE0
PD3 / DE1
33 28 23
PA0 / T0IN 34 22 PA7 / SDA
PD2 PD6 / CTS1
PC2 / SS PC3 / SCK
RESET VSS
VDD VDD
VSS 39 17 PC7 / T2OUT
PD1 PC6 / T2IN
PD0 DBG
XOUT PC1 / T1OUT
XIN PC0 / T1IN
VDD 44 12 VSS
1 6 11
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
PB2 / ANA2
VREF
AVDD
AVSS
10
PA1 / T0OUT
PD4 / RXD1
PA4 / RXD0
PD5 / TXD1
PC4 / MOSI
PA3 / CTS0
PA5 / TXD0
PC5 / MISO
PD3 / DE1
PA2 / DE0
PA6 / SCL
VDD
VDD
VSS
VSS
PF7
48 40 33
PA0 / T0IN 49 32 PA7 / SDA
PD2 PD6 / CTS1
PC2 / SS PC3 / SCK
RESET PD7 / RCOUT
VDD VSS
PE4 PE5
PE3 PE6
VSS 56 25 PE7
PE2 VDD
PE1 PG3
PE0 VDD
VSS PC7 / T2OUT
PD1 / T3OUT PC6 / T2IN
PD0 / T3IN DBG
XOUT PC1 / T1OUT
XIN 64 17 PC0 / T1IN
1 8 16
PH0 / ANA8
PH1 / ANA9
PH2 / ANA10
PH3 / ANA11
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
PB2 / ANA2
VREF
AVDD
VSS
AVSS
11
PA1 / T0OUT
PD4 / RXD1
PA4 / RXD0
PC4 / MOSI
PD5 / TXD1
PA3 / CTS0
PA5 / TXD0
PC5 / MISO
PD3 / DE1
PA2 / DE0
PA6 / SCL
VDD
VDD
VDD
VSS
VSS
PF7
9 1 61
PA0 / T0IN 10 60 PA7 / SDA
PD2 PD6 / CTS1
PC2 / SS PC3 / SCK
RESET PD7 / RCOUT
VDD VSS
PE4 PE5
PE3 PE6
VSS PE7
PE2 18 52 VDD
PE1 PG3
PE0 VDD
VSS PC7 / T2OUT
VDD PC6 / T2IN
PD1 / T3OUT DBG
PD0 / T3IN PC1 / T1OUT
XOUT PC0 / T1IN
XIN 26 44 VSS
27 35 43
PB2 / ANA2
PH0 / ANA8
PH1 / ANA9
PH2 / ANA10
PH3 / ANA11
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
VREF
AVDD
VSS
AVSS
AVSS
12
PA1 / T0OUT
PD4 / RXD1
PA4 / RXD0
PD5 / TXD1
PC4 / MOSI
PA5 / TXD0
PA3 / CTS0
PC5 / MISO
PD3 / DE1
PA2 / DE0
PA6 / SCL
VDD
VDD
VSS
VSS
PF7
80 75 70 65
PA0 / T0IN 1 64 PA7 / SDA
PD2 PD6 / CTS1
PC2 / SS PC3 / SCK
PF6 PD7 / RCOUT
RESET 5 60 PG0
VDD VSS
PF5 PG1
PF4 PG2
PF3 PE5
PE4 10 55 PE6
PE3 PE7
VSS VDD
PE2 PG3
PE1 PG4
PE0 15 50 PG5
VSS PG6
PF2 VDD
PF1 PG7
PF0 PC7 / T2OUT
VDD 20 45 PC6 / T2IN
PD1 / T3OUT DBG
PD0 / T3IN PC1 / T1OUT
XOUT PC0 / T1IN
XIN 24 41 VSS
25 30 35 40
PB2 / ANA2
AVDD
VSS
AVSS
PH0 / ANA8
PH1 / ANA9
PH2 / ANA10
PH3 / ANA11
VREF
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
PB6 / ANA6
PB7 / ANA7
PB3 / ANA3
13
Signal Descriptions
Table 3 describes the Z8 Encore!TM signals. Refer to the section Pin Configurations on
page 7 to determine the signals available for the specific package styles.
Table 3. Signal Descriptions
I2C Controller
SCL O Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA I/O Serial Data. This open-drain pin transfers data between the I2C and a slave. This
pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O
pin is configured for alternate function to enable the SDA function, this pin is
open-drain.
SPI Controller
SS I/O Slave Select. This signal can be an output or an input. If the Z8 Encore!TM is the
SPI master, this pin may be configured as the Slave Select output. If the Z8
Encore!TM is the SPI slave, this pin is the input slave select. It is multiplexed with
a general-purpose I/O pin.
SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore!TM is the SPI
master, this pin is an output. If the Z8 Encore! is the SPI slave, this pin is an
input. It is multiplexed with a general-purpose I/O pin.
MOSI I/O Master Out Slave In. This signal is the data output from the SPI master device and
the data input to the SPI slave device. It is multiplexed with a general-purpose I/O
pin.
MISO I/O Master In Slave Out. This pin is the data input to the SPI master device and the
data output from the SPI slave device. It is multiplexed with a general-purpose I/O
pin.
14
UART Controllers
TXD0 / TXD1 O Transmit Data. These signals are the transmit outputs from the UARTs. The TXD
signals are multiplexed with general-purpose I/O pins.
RXD0 / RXD1 I Receive Data. These signals are the receiver inputs for the UARTs and IrDAs. The
RXD signals are multiplexed with general-purpose I/O pins.
CTS0 / CTS1 I Clear To Send. These signals are control inputs for the UARTs. The CTS signals
are multiplexed with general-purpose I/O pins.
DE0 / DE1 O Driver Enable. This signal allows automatic control of external RS-485 drivers.
This signal is approximately the inverse of the TXE (Transmit Empty) bit in the
UART Status 0 register. The DE signal may be used to ensure an external RS-485
driver is enabled when data is transmitted by the UART.
Timers
T0OUT / T1OUT/ O Timer Output 0-3. These signals are output pins from the timers. The Timer
T2OUT / T3OUT Output signals are multiplexed with general-purpose I/O pins. T3OUT is not
available in 44-pin package devices.
T0IN / T1IN/ I Timer Input 0-3. These signals are used as the capture, gating and counter inputs.
T2IN / T3IN The Timer Input signals are multiplexed with general-purpose I/O pins. T3IN is
not available in 44-pin package devices.
Analog
ANA[11:0] I Analog Input. These signals are inputs to the analog-to-digital converter (ADC).
The ADC analog inputs are multiplexed with general-purpose I/O pins.
VREF I Analog-to-digital converter reference voltage input. The VREF pin should be left
unconnected (or capacitively coupled to analog ground) if the internal voltage
reference is selected as the ADC reference voltage.
Oscillators
XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can
be connected between it and the XOUT pin to form the oscillator.
XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal
can be connected between it and the XIN pin to form the oscillator.
RCOUT O RC Oscillator Output. This signal is the output of the RC oscillator. It is
multiplexed with a general-purpose I/O pin.
15
On-Chip Debugger
DBG I/O Debug. This pin is the control and data input and output to and from the On-Chip
Debugger. For operation of the On-chip debugger, all power pins (VDD and
AVDD) must be supplied with power, and all ground pins (VSS and AVSS) must be
grounded. This pin is open-drain and must have an external pull-up resistor to
ensure proper operation
Reset
RESET I RESET. Generates a Reset when asserted (driven Low).
Power Supply
VDD I Power Supply.
AVDD I Analog Power Supply.
VSS I Ground.
AVSS I Analog Ground.
Pin Characteristics
Table 4 provides detailed information on the characteristics for each pin available on the
Z8 Encore!® products. Data in Table 4 is sorted alphabetically by the pin symbol mne-
monic.
Table 4. Pin Characteristics of the Z8 Encore!®
16
17
Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
• The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O port control registers.
• The Program Memory contains addresses for all memory locations having executable
code and/or data.
• The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore!® is 4KB (4096 bytes). The Register File
is composed of two sections—control registers and general-purpose registers. When
instructions are executed, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not recom-
mended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
Z8F642x, Z8F482x, Z8F322x, Z8F242x, and Z8F162x provide 2KB to 4KB of on-chip
RAM depending upon the device. Reading from Register File addresses outside the avail-
able RAM addresses (and not within the control register address space) returns an unde-
fined value. Writing to these Register File addresses produces no effect. Refer to the Part
Selection Guide on page 2 to determine the amount of RAM available for the specific Z8
Encore!® device.
18
Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8F642x,
Z8F482x, Z8F322x, Z8F242x, and Z8F162x contain 16KB to 64KB of on-chip Flash
memory in the Program Memory address space, depending upon the device. Reading from
Program Memory addresses outside the available Flash memory addresses returns FFH.
Writing to these unimplemented Program Memory addresses produces no effect. Table 5
describes the Program Memory Maps for the Z8F642x family products.
Table 5. Z8F642x Family Program Memory Maps
19
Data Memory
The Z8F642x family does not use the eZ8 CPU’s 64KB Data Memory address space.
Information Area
Table 6 describes the Z8F642x family Information Area. This 512 byte Information Area
is accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled,
the Information Area is mapped into the Program Memory and overlays the 512 bytes at
addresses FE00H to FFFFH. When the Information Area access is enabled, execution of
LDC and LDCI instruction from these Program Memory addresses return the Information
Area data rather than the Program Memory data. Reads of these addresses through the On-
Chip Debugger also returns the Information Area data. Execution of code from these
addresses continues to correctly use the Program Memory. Access to the Information Area
is read-only.
20
21
22
XX=Undefined
23
24
25
26
Reserved
Cascade Timer Timer 1 Reload High Byte
0 = Timer 0 Input signal is GPIO pin T1RH (%F0A - Read/Write)
1 = Timer 0 Input signal is Timer 3 out D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Timer 1 reload value [15:8]
27
28
Timer Enable
Timer 3 Reload Low Byte 0 = Timer is disabled
T3RL (%F1B - Read/Write) 1 = Timer is enabled
D7 D6 D5 D4 D3 D2 D1 D0
29
Parity Enable
CTS signal
0 = Parity is disabled
Returns the level of the CTS signal 1 = Parity is enabled
Transmitter Empty CTS Enable
0 = Data is currently transmitting 0 = CTS signal has no effect on the
1 = Transmission is complete transmitter
1 = UART recognizes CTS signal as a
Transmitter Data Register Empty transmit enable control signal
0 = Transmit Data Register is full
1 = Transmit Data register is empty Receive Enable
0 = Receiver disabled
Break Detect 1 = Receiver enabled
0 = No break occurred
1 = A break occurred Transmit Enable
0 = Transmitter disabled
Framing Error 1 = Transmitter enabled
0 = No framing error occurred
1 = A framing occurred
Overrun Error
0 = No overrrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
30
Received Data Interrupt Enable UART0 Baud Rate Generator Low Byte
0 = Received data and errors generate U0BRL (%F47 - Read/Write)
interrupt requests
1 = Only errors generate interrupt D7 D6 D5 D4 D3 D2 D1 D0
requests. Received data does not.
UART0 Baud Rate divisor [7:0]
Baud Rate Registers Control
Refer to UART chapter for operation
UART0 Status 1
U0STAT1 (%F44- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new frame
Reserved
31
32
Received Data Interrupt Enable UART1 Baud Rate Generator Low Byte
0 = Received data and errors generate U1BRL (%F4F - Read/Write)
interrupt requests
1 = Only errors generate interrupt D7 D6 D5 D4 D3 D2 D1 D0
requests. Received data does not.
UART1 Baud Rate divisor [7:0]
Baud Rate Registers Control
Refer to UART chapter for operation
Read
UART1 Status 1 0 = Write operation
U0STAT1 (%F4C- Read Only) 1 = Read operation
D7 D6 D5 D4 D3 D2 D1 D0
10-Bit Address
Mulitprocessor Receive 0 = 7-bit address being transmitted
Returns value of last multiprocessor bit 1 = 10-bit address being transmitted
33
34
Interrupt Request
0 = No SPI interrupt request pending SPI Baud Rate Generator Low Byte
1 = SPI interrupt request is pending SPIBRL (%F67 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
35
36
Reserved
Reserved
37
UART 0 Receiver Interrupt Request UART 0 Receiver IRQ Enable Low Bit
38
Port A Address
IRQ2 Enable High Bit PAADDR (%FD0 - Read/Write)
IRQ2ENH (%FC7 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port A Address[7:0]
Port C Pin IRQ Enable High Bit Selects Port Sub-Registers:
00H = No function
DMA IRQ Enable High Bit 01H = Data direction
02H = Alternate function
UART 1 Transmitter IRQ Enable High 03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
UART 1 Receiver IRQ Enable High Bit 06H-FFH = No function
Timer 3 IRQ Enable High Bit
Port A Control
IRQ2 Enable Low Bit PACTL (%FD1 - Read/Write)
IRQ2ENH (%FC8 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port A Control[7:0]
Provides Access to Port Sub-Registers
Port C Pin IRQ Enable Low Bit
39
Port B Control
PBCTL (%FD5 - Read/Write) Port D Address
D7 D6 D5 D4 D3 D2 D1 D0 PDADDR (%FDC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Control[7:0]
Provides Access to Port Sub-Registers Port D Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
Port B Input Data 02H = Alternate function
PBIN (%FD6 - Read Only) 03H = Output control (open-drain)
04H = High drive enable
D7 D6 D5 D4 D3 D2 D1 D0 05H = STOP mode recovery enable
06H-FFH = No function
Port B Input Data [7:0]
Port D Control
Port B Output Data PDCTL (%FDD - Read/Write)
PBOUT (%FD7 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port D Control[7:0]
Port B Output Data [7:0] Provides Access to Port Sub-Registers
Port C Control
PCCTL (%FD9 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Control[7:0]
Provides Access to Port Sub-Registers
40
Port E Control
PECTL (%FE1 - Read/Write) Port G Address
D7 D6 D5 D4 D3 D2 D1 D0 PGADDR (%FE8 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Control[7:0]
Provides Access to Port Sub-Registers Port G Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
Port E Input Data 02H = Alternate function
PEIN (%FE2 - Read Only) 03H = Output control (open-drain)
04H = High drive enable
D7 D6 D5 D4 D3 D2 D1 D0 05H = STOP mode recovery enable
06H-FFH = No function
Port E Input Data [7:0]
Port G Control
Port E Output Data PGCTL (%FE9 - Read/Write)
PEOUT (%FE3 - Read/Write) D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Port G Control[7:0]
Port E Output Data [7:0] Provides Access to Port Sub-Registers
Port F Control
PFCTL (%FE5 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Control[7:0]
Provides Access to Port Sub-Registers
41
STOP
0 = SMR has not occurred
Port H Control 1 = SMR has occurred
PHCTL (%FED - Read/Write) POR
D7 D6 D5 D4 D3 D2 D1 D0 0 = POR has not occurred
1 = POR has occurred
Port H Control [3:0]
Provides Access to Port Sub-Registers
Flash Control
FCTL (%FF8 - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Command
73H = First unlock command
8CH = Second unlock command
95H = Page erase command
63H = Mass erase command
5EH = Flash Sector Protect reg select
42
Z - Zero Flag
43
44
Reset Types
The Z8F642x family provides two different types of reset operation (System Reset and
STOP Mode Recovery). The type of Reset is a function of both the current operating mode
of the Z8F642x family device and the source of the Reset. Table 8 lists the types of Reset
and their operating characteristics.
45
System Reset
During a System Reset, the Z8F642x family device is held in Reset for 66 cycles of the
Watch-Dog Timer oscillator followed by 16 cycles of the system clock. At the beginning
of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are dis-
abled.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins oper-
ating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following pro-
vides more detailed information on the individual Reset sources. Please note that a Power-
On Reset / Voltage Brown-Out event always has priority over all other possible reset
sources to insure a full system reset occurs.
Table 9. Reset Sources and Resulting Reset Type
Power-On Reset
Each device in the Z8F642x family contains an internal Power-On Reset (POR) circuit.
The POR circuit monitors the supply voltage and holds the device in the Reset state until
46
the supply voltage reaches a safe operating level. After the supply voltage exceeds the
POR voltage threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the
Watch-Dog Timer oscillator. After the POR counter times out, the XTAL Counter is
enabled to count a total of 16 system clock pulses. The device is held in the Reset state
until both the POR Counter and XTAL counter have timed out. After the Z8F642x family
device exits the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following
Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register
is set to 1.
Figure 8 illustrates Power-On Reset operation. Refer to the Electrical Characteristics
chapter for the POR threshold voltage (VPOR).
VCC=3.3V
VPOR
VVBO
VCC=0.0V Program
Execution
WDT Clock
Primary
Oscillator
Oscillator
Start-up
Internal RESET
signal
47
After the supply voltage again exceeds the Power-On Reset voltage threshold, the device
progresses through a full System Reset sequence, as described in the Power-On Reset sec-
tion. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control
(WDTCTL) register is set to 1. Figure 9 illustrates Voltage Brown-Out operation. Refer to
the Electrical Characteristics chapter for the VBO and POR threshold voltages (VVBO
and VPOR).
The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode.
Operation during STOP mode is set by the VBO_AO Option Bit. Refer to the Option Bits
chapter for information on configuring VBO_AO.
WDT Clock
Primary
Oscillator
Internal RESET
signal
WDT XTAL
counter delay counter delay
48
49
out and the Z8F642x family device is configured to respond to interrupts, the eZ8 CPU
services the Watch-Dog Timer interrupt request following the normal STOP Mode Recov-
ery sequence.
Caution: In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled.
The Port Input Data registers record the Port transition only if the signal
stays on the Port pin through the end of the STOP Mode Recovery delay.
Thus, short pulses on the Port pin can initiate STOP Mode Recovery with-
out being written to the Port Input Data register or without initiating an in-
terrupt (if enabled for that pin).
50
Low-Power Modes
Overview
The Z8F642x family products contain power-saving features. The highest level of power
reduction is provided by STOP mode. The next level of power reduction is provided by
the HALT mode.
STOP Mode
Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In
STOP mode, the operating characteristics are:
• Primary crystal oscillator is stopped; XIN and XOUT pins are driven to VSS.
• System clock is stopped
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• If enabled for operation during STOP mode, the Watch-Dog Timer and its internal RC
oscillator continue to operate.
• If enabled for operation in STOP mode via the associated Option Bit, the Voltage
Brown-Out protection circuit continues to operate.
• All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection
should be disabled, and the Watch-Dog Timer should be disabled. The device can be
brought out of STOP mode using STOP Mode Recovery. For more information on STOP
Mode Recovery refer to the Reset and STOP Mode Recovery chapter beginning on
page 44.
Caution: To prevent excess current consumption, STOP Mode must not be used if
the device is driven with an external clock source.
51
HALT Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
• Primary crystal oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• Watch-Dog Timer’s internal RC oscillator continues to operate
• If enabled, the Watch-Dog Timer continues to operate
• All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
• Interrupt
• Watch-Dog Timer time-out (interrupt or reset)
• Power-on reset
• Voltage-brown out reset
• External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
52
General-Purpose I/O
Overview
The Z8F642x family products support a maximum of seven 8-bit ports (Ports A-G) and
one 4-bit port (Port H) for general-purpose input/output (I/O) operations. Each port con-
tains control and data registers. The GPIO control registers are used to determine data
direction, open-drain, output drive current and alternate pin functions. Each port pin is
individually programmable.
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
Z8Fxx21 40-pin [7:0] [7:0] [6:0] [6:3,2:0] - - - -
Z8Fxx21 44-pin [7:0] [7:0] [7:0] [6:0] - - - -
Z8Fxx22 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8Fxx23 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Architecture
Figure 10 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength are not
illustrated.
53
Q D Q D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus D Q Port
Pin
System
Clock
54
55
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). Refer to the Interrupt Controller chapter for more information on
interrupts using the GPIO pins.
56
BITS 7 6 5 4 3 2 1 0
FIELD PADDR[7:0]
RESET 00H
R/W R/W
57
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A-H Control Registers
00H No function. Provides some protection against accidental Port reconfiguration.
01H Data Direction
02H Alternate Function
03H Output Control (Open-Drain)
04H High Drive Enable
05H STOP Mode Recovery Source Enable.
06H-FFH No function.
BITS 7 6 5 4 3 2 1 0
FIELD PCTL
RESET 00H
R/W R/W
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
58
BITS 7 6 5 4 3 2 1 0
RESET 1 1 1 1 1 1 1 1
ADDR If 01H in Port A-H Address Register, accessible via Port A-H Control Register
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A-H Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A-H Input Data Reg-
ister. The output driver is tri-stated.
Caution: Do not enable alternate function for GPIO port pins which do not have an
associated alternate function. Failure to follow this guideline may result in
unpredictable operation.
BITS 7 6 5 4 3 2 1 0
FIELD AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 0 0 0 0 0 0 0 0
ADDR If 02H in Port A-H Address Register, accessible via Port A-H Control Register
59
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR If 03H in Port A-H Address Register, accessible via Port A-H Control Register
60
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR If 04H in Port A-H Address Register, accessible via Port A-H Control Register
61
Table 20. Port A-H STOP Mode Recovery Source Enable Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 0 0 0 0 0 0 0 0
ADDR If 05H in Port A-H Address Register, accessible via Port A-H Control Register
BITS 7 6 5 4 3 2 1 0
RESET X X X X X X X X
R/W R R R R R R R R
62
BITS 7 6 5 4 3 2 1 0
FIELD POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0 0 0 0 0 0 0 0
63
Interrupt Controller
Overview
The interrupt controller on the Z8F642x family products prioritizes the interrupt requests
from the on-chip peripherals and the GPIO port pins. The features of the interrupt control-
ler include the following:
• 24 unique interrupt vectors:
– 12 GPIO port pin interrupt sources
– 12 on-chip peripheral interrupt sources
• Flexible GPIO interrupts
– 8 selectable rising and falling edge GPIO interrupts
– 4 dual-edge interrupts
• 3 levels of individually programmable interrupt priority
• Watch-Dog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for
more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man-
ual is available for download at www.zilog.com.
64
Program Memory
Priority Vector Address Interrupt Source
Highest 0002h Reset (not an interrupt)
0004h Watch-Dog Timer (see Watch-Dog Timer chapter)
0006h Illegal Instruction Trap (not an interrupt)
0008h Timer 2
000Ah Timer 1
000Ch Timer 0
000Eh UART 0 receiver
0010h UART 0 transmitter
0012h I2C
0014h SPI
0016h ADC
0018h Port A7 or Port D7, rising or falling input edge
001Ah Port A6 or Port D6, rising or falling input edge
001Ch Port A5 or Port D5, rising or falling input edge
001Eh Port A4 or Port D4, rising or falling input edge
0020h Port A3 or Port D3, rising or falling input edge
0022h Port A2 or Port D2, rising or falling input edge
0024h Port A1 or Port D1, rising or falling input edge
0026h Port A0 or Port D0, rising or falling input edge
0028h Timer 3 (not available in 44-pin packages)
002Ah UART 1 receiver
002Ch UART 1 transmitter
002Eh DMA
0030h Port C3, both input edges
0032h Port C2, both input edges
0034h Port C1, both input edges
Lowest 0036h Port C0, both input edges
65
Architecture
Figure 11 illustrates a block diagram of the interrupt controller.
High
Port Interrupts Priority
Interrupt Request Latches and Control
Vector
Priority
Mux IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Operation
66
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt
request.
Caution: The following style of coding to clear bits in the Interrupt Request registers
is NOT recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
67
To avoid missing interrupts, the following style of coding to set bits in the
Interrupt Request registers is recommended:
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC0H
68
69
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC3H
70
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC6H
71
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC1H
72
BITS 7 6 5 4 3 2 1 0
FIELD T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
RESET 0 0 0 0 0 0 0 0
ADDR FC2H
73
BITS 7 6 5 4 3 2 1 0
FIELD PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
RESET 0 0 0 0 0 0 0 0
ADDR FC4H
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC5H
74
BITS 7 6 5 4 3 2 1 0
FIELD T3ENH U1RENH U1TENH DMAENH C3ENH C2ENH C1ENH C0ENH
RESET 0 0 0 0 0 0 0 0
ADDR FC7H
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FC8H
75
Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FCDH
BITS 7 6 5 4 3 2 1 0
FIELD PAD7S PAD6S PAD5S PAD4S PAD3S PAD2S PAD1S PAD0S
RESET 0 0 0 0 0 0 0 0
ADDR FCEH
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
76
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
R/W R/W R R R R R R R
ADDR FCFH
77
Timers
Overview
The Z8F642x family products contain up to four 16-bit reloadable timers that can be used
for timing, event counting, or generation of pulse-width modulated (PWM) signals. The
timers’ features include:
• 16-bit reload counter
• Programmable prescaler with prescale values from 1 to 128
• PWM output generation
• Capture and compare capability
• External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
• Timer output pin
• Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I2C peripherals may also be used to provide basic timing function-
ality. Refer to the respective serial communication peripheral chapters for information on
using the Baud Rate Generators as timers. Timer 3 is unavailable in the 44-pin package
devices.
Architecture
Figure 12 illustrates the architecture of the timers.
78
Timer Block
Data Timer
Bus Control
Block
Control
16-Bit Interrupt, Timer
Compare
Reload Register PWM, Interrupt
and
Timer Output
System Timer
Control
Clock 16-Bit Counter Output
Compare
Gate
16-Bit
Input
PWM / Compare
Capture
Input
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
One-Shot Mode
In One-Shot mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and
stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is desired to have the Timer Output make a permanent state change upon One-Shot time-
79
out, first set the TPOL bit in the Timer Control 1 Register to the start value before begin-
ning One-Shot mode. Then, after starting the timer, set TPOL to the opposite bit value.
The steps for configuring a timer for One-Shot mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for One-Shot mode.
– Set the prescale value.
– If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In One-Shot mode, the system clock always provides the timer input. The timer period is
given by the following equation:
( Reload Value – Start Value ) × Prescale
One-Shot Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Continuous Mode
In Continuous mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt, the count value in the Timer High and
Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output
alternate function is enabled, the Timer Output pin changes state (from Low to High or
from High to Low) upon timer Reload.
The steps for configuring a timer for Continuous mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for Continuous mode.
– Set the prescale value.
80
– If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This only affects the first pass in Continuous mode. After the first timer
Reload in Continuous mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Continuous mode, the system clock always provides the timer input. The timer period is
given by the following equation:
Reload Value × Prescale
Continuous Mode Time-Out Period (s) = ----------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first time-out period.
Counter Mode
In Counter mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer
Control 1 Register selects whether the count occurs on the rising edge or the falling edge
of the Timer Input signal. In Counter mode, the prescaler is disabled.
Caution: The input frequency of the Timer Input signal must not exceed one-fourth
the system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
The steps for configuring a timer for Counter mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for Counter mode.
81
– Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter mode. After the first timer Reload in Counter
mode, counting always begins at the reset value of 0001H. Generally, in Counter
mode the Timer High and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control 1 register to enable the timer.
In Counter mode, the number of Timer Input transitions since the timer start is given by
the following equation:
Counter Mode Timer Input Transitions = Current Count Value – Start Value
PWM Mode
In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16-
bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The Timer Output signal returns to a High (1) after the timer reaches the Reload
value and is reset to 0001H.
If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload
value and is reset to 0001H.
The steps for configuring a timer for PWM mode and initiating the PWM operation are as
follows:
1. Write to the Timer Control 1 register to:
82
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by:
PWM Value
PWM Output High Time Ratio (%) = ---------------------------------- × 100
Reload Value
Capture Mode
In Capture mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the
83
Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting.
The steps for configuring a timer for Capture mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for Capture mode.
– Set the prescale value.
– Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000H after the
interrupt, then the interrupt was generated by a Reload.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Capture mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
Compare Mode
In Compare mode, the timer counts up to the 16-bit maximum Compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon Com-
pare.
84
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
The steps for configuring a timer for Compare mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for Compare mode.
– Set the prescale value.
– Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Compare mode, the system clock always provides the timer input. The Compare time is
given by the following equation:
( Compare Value – Start Value ) × Prescale
Compare Mode Time (s) = ------------------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Gated Mode
In Gated mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
The steps for configuring a timer for Gated mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
– Disable the timer
85
Capture/Compare Mode
In Capture/Compare mode, the timer begins counting on the first external Timer Input
transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the
Timer Control 1 Register. The timer input is the system clock.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte registers is reset to 0001H, and counting resumes.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes.
The steps for configuring a timer for Capture/Compare mode and initiating the count are
as follows:
1. Write to the Timer Control 1 register to:
– Disable the timer
– Configure the timer for Capture/Compare mode.
– Set the prescale value.
– Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
86
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control 1 register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In Capture/Compare mode, the elapsed time from timer start to Capture event can be cal-
culated using the following equation:
87
BITS 7 6 5 4 3 2 1 0
FIELD TH
RESET 0 0 0 0 0 0 0 0
BITS 7 6 5 4 3 2 1 0
FIELD TL
RESET 0 0 0 0 0 0 0 1
88
BITS 7 6 5 4 3 2 1 0
FIELD TRH
RESET 1 1 1 1 1 1 1 1
BITS 7 6 5 4 3 2 1 0
FIELD TRL
RESET 1 1 1 1 1 1 1 1
89
BITS 7 6 5 4 3 2 1 0
FIELD PWMH
RESET 0 0 0 0 0 0 0 0
BITS 7 6 5 4 3 2 1 0
FIELD PWML
RESET 0 0 0 0 0 0 0 0
90
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
CSC—Cascade Timers
0 = Timer Input signal comes from the pin.
1 = For Timer 0, Input signal is connected to Timer 3 output.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
For Timer 3, Input signal is connected to Timer 2 output.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
91
One-Shot mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Continuous mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Counter mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
Capture mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
Compare mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Gated mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
Capture/Compare mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
92
PRES—Prescale value.
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE—Timer mode
000 = One-Shot mode
001 = Continuous mode
010 = Counter mode
011 = PWM mode
100 = Capture mode
101 = Compare mode
110 = Gated mode
111 = Capture/Compare mode
93
Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which may place the Z8 Encore!® into unsuitable
operating states. The Watch-Dog Timer includes the following features:
• On-chip RC oscillator
• A selectable time-out response: Short Reset or interrupt
• 24-bit programmable time-out value
Operation
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
Z8F642x family device when the WDT reaches its terminal count. The Watch-Dog Timer
uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer
has only two modes of operation—on and off. Once enabled, it always counts and must be
refreshed to prevent a time-out. An enable can be performed by executing the WDT
instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog
Timer to operate all the time, even if a WDT instruction has not been executed.
The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
given by the following equation:
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator
frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H.
The WDT Reload Value must not be set to values below 000004H. Table 46 provides
information on approximate time-out delays for the minimum and maximum WDT reload
values.
94
95
mode. Refer to the Reset and STOP Mode Recovery chapter for more information on
STOP Mode Recovery.
If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and
executing code from the vector address.
96
BITS 7 6 5 4 3 2 1 0
FIELD POR STOP WDT EXT Reserved SM
R/W R R R R R R R R
ADDR FF0H
97
98
Caution: The 24-bit WDT Reload Value must not be set to a value less than
000004H.
BITS 7 6 5 4 3 2 1 0
FIELD WDTU
RESET 1 1 1 1 1 1 1 1
ADDR FF1H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
BITS 7 6 5 4 3 2 1 0
FIELD WDTH
RESET 1 1 1 1 1 1 1 1
ADDR FF2H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
99
BITS 7 6 5 4 3 2 1 0
FIELD WDTL
RESET 1 1 1 1 1 1 1 1
ADDR FF3H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
100
UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communica-
tion channel capable of handling asynchronous data transfers. The UART uses a single
8-bit data mode with selectable parity. Features of the UART include:
• 8-bit asynchronous data transfer
• Selectable even- and odd-parity generation and checking
• Option of one or two Stop bits
• Separate transmit and receive interrupts
• Framing, parity, overrun and break detection
• Separate transmit and receive enables
• 16-bit Baud Rate Generator (BRG)
• Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
• Baud Rate Generator timer mode
• Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate
generator. The UART’s transmitter and receiver function independently, but employ the
same baud rate and data format. Figure 13 illustrates the UART architecture.
101
Parity Checker
Receiver Control
with address compare
RXD
Receive Shifter
Receive Data
Register Control Registers
System Bus
Transmit Data
Register Status Register Baud Rate
Generator
Transmit Shift
TXD Register
Transmitter Control
Parity Generator
CTS
DE
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits.
Figures 14 and 15 illustrates the asynchronous data format employed by the UART with-
out parity and with parity, respectively.
102
103
– Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data
register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data
register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data register becomes available to receive new data.
6. Write the UART Control 1 register to select the outgoing address bit.
– Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it
if sending a data byte.
7. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
8. If desired and multiprocessor mode is enabled, make any changes to the
Multiprocessor Bit Transmitter (MPBT) value.
9. To transmit additional bytes, return to Step 5.
104
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data register is empty, an interrupt is generated immediately. When the UART
Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Write the UART Control 1 register to select the outgoing address bit:
– Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it
if sending a data byte.
2. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
105
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the desired priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode
functions, if desired.
– Set the Multiprocessor Mode Select (MPEN) to Enable Multiprocessor mode.
– Set the Multiprocessor Mode Bits, MPMD[1:0], to select the desired address
matching scheme.
– Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a
DMA block)
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the UART Control 0 register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if desired and if multiprocessor mode is not enabled, and select
either even or odd parity.
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Check the UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was due to data available, read the data from the UART Receive Data
register. If operating in Multiprocessor (9-bit) mode, further actions may be required
depending on the Multiprocessor Mode bits MPMD[1:0].
3. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
106
In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the Multiproces-
sor control bit. The UART Control 1 and Status 1 registers provide Multiprocessor (9-bit)
mode control and status information. If an automatic address matching scheme is enabled,
the UART Address Compare register holds the network address of the device.
107
108
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Regis-
ter before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The DEPOL bit in the UART Control Register 1 sets the polarity of
the Driver Enable signal.
1
DE
0
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
⎛ ------------------------------------
1 -⎞ ≤ DE to Start Bit Setup Time (s) ≤ ⎛ ------------------------------------
2 -⎞
⎝ Baud Rate (Hz)⎠ ⎝ Baud Rate (Hz)⎠
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first
bit of data out. At this point, the Transmit Data register may be written with the next char-
acter to send. This provides 7 bit periods of latency to load the Transmit Data register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data register clears the TDRE bit to 0.
109
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
• A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
Note that in multiprocessor mode (MPEN = 1), the receive data interrupts are
dependent on the multiprocessor configuration and the most recent address byte.
• A break is received
• An overrun is detected
• A data framing error is detected
110
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
111
High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
System Clock Frequency (Hz) -
UART Data Rate (bits/s) = ---------------------------------------------------------------------------------------------
16 × UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the UART Control 1 register to 1.
BITS 7 6 5 4 3 2 1 0
FIELD TXD
RESET X X X X X X X X
R/W W W W W W W W W
TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
112
BITS 7 6 5 4 3 2 1 0
FIELD RXD
RESET X X X X X X X X
R/W R R R R R R R R
RXD—Receive Data
UART receiver data byte from the RXDx pin
BITS 7 6 5 4 3 2 1 0
FIELD RDA PE OE FE BRKD TDRE TXE CTS
RESET 0 0 0 0 0 1 1 X
R/W R R R R R R R R
113
114
CTS—CTS signal
When this bit is read it returns the level of the CTS signal.
BITS 7 6 5 4 3 2 1 0
FIELD Reserved NEWFRM MPRX
RESET 0 0 0 0 0 0 0 0
Reserved—Must be 0.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data register resets this bit to 0.
BITS 7 6 5 4 3 2 1 0
FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 0 0 0 0 0 0 0 0
115
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
116
BITS 7 6 5 4 3 2 1 0
FIELD MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN
RESET 0 0 0 0 0 0 0 0
MPMD[1:0]—Multiprocessor Mode
If Multiprocessor (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the Address Compare Register.
MPEN—Multiprocessor (9-bit) Enable
This bit is used to enable Multiprocessor (9-bit) mode.
0 = Disable Multiprocessor (9-bit) mode.
1 = Enable Multiprocessor (9-bit) mode.
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register).
When the UART receiver is not enabled, this bit determines whether the Baud Rate Gener-
ator will issue interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The Baud Rate Generator generates a receive interrupt when it counts down to zero.
117
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low
Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
BITS 7 6 5 4 3 2 1 0
FIELD COMP_ADDR
RESET 0 0 0 0 0 0 0 0
COMP_ADDR—Compare Address
This 8-bit value is compared to the any incoming address bytes.
118
BITS 7 6 5 4 3 2 1 0
FIELD BRH
RESET 1 1 1 1 1 1 1 1
BITS 7 6 5 4 3 2 1 0
FIELD BRL
RESET 1 1 1 1 1 1 1 1
For a given UART data rate, the integer baud rate divisor value is calculated using the fol-
lowing equation:
UART Baud Rate Divisor Value (BRG) = Round ⎛ ----------------------------------------------------------------------------⎞
System Clock Frequency (Hz)
⎝ 16 × UART Data Rate (bits/s) ⎠
The baud rate error relative to the desired baud rate is calculated using the following equa-
tion:
119
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 60 provides information on data rate errors for popular baud rates and commonly
used crystal oscillator frequencies.
Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error
Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error
120
121
Infrared Encoder/Decoder
Overview
The Z8F642x family products contain two fully-functional, high-performance UART to
Infrared Encoder/Decoders (Endecs). Each Infrared Endec is integrated with an on-chip
UART to allow easy communication between the Z8 Encore!® and IrDA Physical Layer
Specification, Version 1.3-compliant infrared transceivers. Infrared communication pro-
vides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell
phones, printers and other infrared enabled devices.
Architecture
Figure 19 illustrates the architecture of the Infrared Endec.
System
Clock ZiLOG
ZHX1810
RxD RXD
RXD
TxD Infrared TXD
UART Encoder/Decoder TXD
Baud Rate (Endec) Infrared
Clock
Transceiver
122
Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver via the TXD pin. Likewise, data received from the infrared transceiver is
passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then
passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared
Endec data rate is calculated using the following equation:
123
16-clock
period
Baud Rate
Clock
UART’s Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
TXD
3-clock
pulse
IR_TXD
7-clock
delay
124
16-clock
period
Baud Rate
Clock
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
IR_RXD
min. 1.6µs
pulse
UART’s
RXD Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
8-clock
delay 16-clock 16-clock 16-clock 16-clock
period period period period
Caution: The system clock frequency must be at least 1.0MHz to ensure proper re-
ception of the 1.6µs minimum width pulses allowed by the IrDA standard.
125
Caution: To prevent spurious signals during IrDA data transmission, set the IREN
bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder/
Decoder before enabling the GPIO Port alternate function for the corre-
sponding pin.
126
Architecture
The SPI may be configured as either a Master (in single or multi-master systems) or a
Slave as illustrated in Figures 22 through 24.
SPI Master
To Slave’s SS Pin SS
To Slave MOSI
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System
127
VCC
SPI Master
SS
To Slave #2’s SS Pin GPIO
To Slave #1’s SS Pin GPIO
8-bit Shift Register
From Slave
MISO Bit 7 Bit 0
To Slave MOSI
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master SS
SCK
From Master
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
128
During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an
multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
• MISO (Master-In, Slave-Out)
• MOSI (Master-Out, Slave-In)
• SCK (SPI Serial Clock)
• SS (Slave Select)
The following paragraphs discuss these SPI signals. Each signal is described in both Mas-
ter and Slave modes.
Master-In, Slave-Out
The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out, Slave-In
The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator cre-
ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig-
nal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (XIN) clock period.
129
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register).
In both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sam-
pled on the opposite edge where data is stable. Edge polarity is determined by the SPI
phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. For communication between the Z8F642x family device’s SPI
Master and external Slave devices, the SS signal, as an output, can assert the SS input pin
on one of the Slave devices. Other GPIO output pins can also be employed to select exter-
nal SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin must
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the
SPI Status register.
Table 61. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
130
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
SS
131
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
SS
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
open-drain mode to prevent bus contention. At any one time, only one SPI device is con-
figured as the Master and all other SPI devices on the bus are configured as Slaves. The
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves
(including those which are not enabled). The enabled Slave drives data out its MISO pin to
the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Regis-
ter. The COL bit indicates the occurrence of a multi-master collision (mode fault error con-
dition).
Slave Operation
The SPI block is configured for slave mode operation by setting the SPIEN bit to 1 and the
MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE reg-
132
ister. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS
field in the SPIMODE register must be set to be consistent with the other SPI devices. The
STR bit in the SPICTL register may be used if desired to force a “startup” interrupt. The
BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in
slave mode. The SPI baud rate generator is not used in slave mode so the SPIBRH and
SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT regis-
ter is not written prior to the slave transaction, the MISO pin outputs whatever value is
currently in the SPIDAT register.
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in slave mode is the sys-
tem clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status register indicates when a
data transmission error has been detected.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception completes in both master and slave modes. A character can be defined to be
133
1 through 8 bits by the NUMBITS field in the SPI Mode register. In slave mode it is not
necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave
mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits
in a character (see description of slave abort error above). Writing a 1 to the IRQ bit in the
SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared
to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer pro-
cess, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL
register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the BIRQ bit in the SPICTL register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just
the SPI interrupt bit in the interrupt controller.
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the SPI Control register to 1.
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8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be writ-
ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
BITS 7 6 5 4 3 2 1 0
FIELD DATA
RESET X X X X X X X X
ADDR F60H
DATA—Data
Transmit and/or receive data.
135
BITS 7 6 5 4 3 2 1 0
FIELD IRQE STR BIRQ PHASE CLKPOL WOR MMEN SPIEN
RESET 0 0 0 0 0 0 0 0
ADDR F61H
136
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 1
ADDR F62H
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
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SLAS—Slave Select
If SPI enabled as a Slave,
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0
ADDR F63H
Reserved—Must be 0.
DIAG - Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPI-
BRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.
Caution: Exercise caution if reading the values while the BRG is counting.
138
110 = 6 bits
111 = 7 bits.
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0
R/W R R R
ADDR F64H
139
BITS 7 6 5 4 3 2 1 0
FIELD BRH
RESET 1 1 1 1 1 1 1 1
ADDR F66H
BITS 7 6 5 4 3 2 1 0
FIELD BRL
RESET 1 1 1 1 1 1 1 1
ADDR F67H
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I2C Controller
Overview
The I2C Controller makes the Z8F642x family products bus-compatible with the I2CTM
protocol. The I2C Controller consists of two bidirectional bus lines—a serial data signal
(SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
• Transmit and Receive Operation in Master mode
• Maximum data rate of 400kbit/sec
• 7- and 10-bit Addressing Modes for Slaves
• Unrestricted Number of Data Bytes Transmitted per Transfer
The I2C Controller in the Z8F642x family products does not operate in Slave mode.
Operation
The I2C Controller operates in Master mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
• Master transmits to a 7-bit slave
• Master transmits to a 10-bit slave
• Master receives from a 7-bit slave
• Master receives from a 10-bit slave
141
level. When the slave has released the clock, the I2C Controller continues the transaction.
All data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl-
edge (NAK) and baud rate generator. These four interrupt sources are combined into a sin-
gle interrupt request signal to the interrupt controller.
NAK interrupts occur when a Not Acknowledge is received from the slave or sent by the
I2C Controller and the Start or Stop bit is not set. The NAK event sets bit 0 of the
I2CSTAT register and can only be cleared by setting the Start or Stop bit. When this inter-
rupt occurs, the I2C Controller waits until it is cleared before performing any action. In an
interrupt service routine, the NAK interrupt must be the first thing polled.
Receive interrupts occur when a byte of data has been received by the I2C master. The
receive interrupt is cleared by reading from the I2C Data register. If no action is taken, the
I2C Controller waits until this interrupt is cleared before performing any other action.
For Transmit interrupts to occur, the TXI bit must be 1 in the I2C Control register. Trans-
mit interrupts occur under the following conditions when the transmit data register is
empty:
• The I2C Controller is enabled
• The first bit of the byte of an address is shifting out and the RD bit of the I2C Status
register is deasserted.
• The first bit of a 10-bit address shifts out.
• The first bit of write data shifted out.
Note: Writing to the I2C Data register always clears the TRDE bit to 0.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled (IEN
bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an interrupt is
generated when the baud rate generator counts down to 1.
142
143
17. The I2C Controller completes transmission of the data on the SDA signal.
18. The I2C Controller sends the STOP condition to the I2C bus.
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7-
bit addressing.
The procedure for a transmit operation on a 10-bit addressed slave is as follows:
1. Software asserts the IEN bit in the I2C Control register.
2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts because the I2C Data register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. The I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL. The I2C Controller sets the ACK bit in the I2C Status register.
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
144
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by writing the data to be written out to the I2C Control register.
15. The I2C Controller shifts out the rest of the second byte of slave address by the SDA
signal.
16. The I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL. The I2C Controller sets the ACK bit in the I2C Status register.
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
Transmit interrupt is asserted.
18. Software responds by asserting the STOP bit of the I2C Control register.
19. The I2C Controller completes transmission of the data on the SDA signal.
20. The I2C Controller sends the STOP condition to the I2C bus.
Figure 29. Receive Data Transfer Format for a 7-Bit Addressed Slave
145
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a read operation to a 10-bit addressed slave is as follows:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data register.
2. Software asserts the START bit of the I2C Control register.
3. The I2C Controller sends the Start condition.
4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
5. After the first bit has been shifted out, a Transmit interrupt is asserted.
6. Software responds by writing eight bits of address to the I2C Data register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL.
9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (lower byte of 10 bit address).
146
10. The I2C Controller shifts out the next eight bits of address. After the first bit is shifted,
the I2C Controller generates a Transmit interrupt.
11. Software responds by setting the START bit of the I2C Control register to generate a
repeated START.
12. Software responds by writing 11110B followed by the 2-bit slave address and a 1
(read) to the I2C Data register.
13. If you want to read only one byte, software responds by setting the NAK bit of the
I2C Control register.
14. After the I2C Controller shifts out the address bits mentioned in step 9 (2nd address
transfer), the I2C slave sends an acknowledge by pulling the SDA signal Low during
the next high period of SCL.
15. The I2C Controller sends the repeated START condition.
16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (third address transfer).
17. The I2C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL.
19. The I2C Controller shifts in a byte of data from the slave.
20. A Receive interrupt is generated.
21. Software responds by reading the I2C Data register.
22. Software responds by setting the STOP bit of the I2C Control register.
23. A NAK condition is sent to the I2C slave.
24. A STOP condition is sent to the I2C slave.
147
register during a read from a slave. The I2C Shift Register is not accessible in the Register
File address space, but is used only to buffer incoming and outgoing data.
BITS 7 6 5 4 3 2 1 0
FIELD DATA
RESET 0 0 0 0 0 0 0 0
ADDR F50H
BITS 7 6 5 4 3 2 1 0
RESET 1 0 0 0 0 0 0 0
R/W R R R R R R R R
ADDR F51H
148
When set, this bit indicates that an Acknowledge was received for the last byte transmitted
or received.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I2C Shift register after the
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I2C Shift register.
DSS—Data Shift State
This bit is active high while data is being shifted to or from the I2C Shift register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing the user to specify whether he
wants to perform a STOP or a repeated START.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR F52H
IEN—I2C Enable
This bit enables the I2C transmitter and receiver.
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it
sends the START condition or by deasserting the IEN bit. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there
149
is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the
I2C Controller waits until data is loaded. If this bit is set while the I2C Controller is shift-
ing out data, it generates a START condition after the byte shifts and the acknowledge
phase completes. If the STOP bit is also set, it also waits until the STOP condition is sent
before the START condition.
STOP—Send Stop Condition
This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift
register has completed transmission or after a byte has been received in a receive opera-
tion. Once set, this bit is reset by the I2C Controller after a Stop condition has been sent or
by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the regis-
ter.
BIRQ—Baud Rate Generator Interrupt Request
This bit causes an interrupt to occur every time the baud rate generator counts down to
one. This bit allows the I2C Controller to be used as an additional timer when the I2C Con-
troller is disabled. This bit is ignored when the I2C Controller is enabled.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I2C Data register is empty on the I2C Controller.
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
bit is deasserted.
FLUSH—Flush Data
Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data register when an NAK is received after the data has been sent to
the I2C Data register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
Setting this bit to 1 enables low-pass digital filters on the SDA and SCL input signals.
These filters reject any input pulse with periods less than a full system clock cycle. The fil-
ters introduce a 3-system clock cycle latency on the inputs.
150
BITS 7 6 5 4 3 2 1 0
FIELD BRH
RESET 1 1 1 1 1 1 1 1
ADDR F53H
BITS 7 6 5 4 3 2 1 0
FIELD BRL
RESET 1 1 1 1 1 1 1 1
ADDR F54H
151
BITS 7 6 5 4 3 2 1 0
RESET X X 0 00000
R/W R R R R
ADDR F55H
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
R/W R R R R R R R R/W
ADDR F56H
DIAG = Diagnostic Control Bit - Selects read back value of the Baud Rate Reload regis-
ters. In diagnostic mode the Baud Rate Counter may be read back.
0 = Normal mode
1 = Diagnostic mode
152
Operation
153
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the Register File. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
controller that two-bytes of ADC data are ready for transfer.
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
ADC output value to the Register File and then returns system bus control back to the
eZ8 CPU.
4. If the current ADC Analog Input is the highest numbered input to be converted:
– DMA_ADC resets the ADC Analog Input number to 0 and initiates data
conversion on ADC Analog Input 0.
– If configured to generate an interrupt, DMA_ADC sends an interrupt request to
the Interrupt Controller
154
If the current ADC Analog Input is not the highest numbered input to be converted,
DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
Caution: When using the DMA_ADC to perform conversions on multiple ADC in-
puts, the Analog-to-Digital Converter must be configured for Single-Shot
mode. If the ADC_IN field in the DMA_ADC Control Register is greater
than 000b, the ADC must be in Single-Shot mode.
155
BITS 7 6 5 4 3 2 1 0
FIELD DEN DLE DDIR IRQEN WSEL RSS
RESET 0 0 0 0 0 0 0 0
DEN—DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address
data is transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address
and continues operating.
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral
control register must be an even address.
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Con-
troller to initiate a DMA transfer. However, if the Request Trigger Source can enable or
disable the interrupt request sent to the Interrupt Controller, the interrupt request must be
enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data. DMA1
Control register: UART0 Transmit Data register empty.
156
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
110 = DMA0 Control register: I2C Receiver Interrupt. DMA1 Control register: I2C Trans-
mitter Interrupt register empty.
111 = Reserved.
BITS 7 6 5 4 3 2 1 0
FIELD DMA_IO
RESET X X X X X X X X
BITS 7 6 5 4 3 2 1 0
RESET X X X X X X X X
157
BITS 7 6 5 4 3 2 1 0
FIELD DMA_START
RESET X X X X X X X X
158
BITS 7 6 5 4 3 2 1 0
FIELD DMA_END
RESET X X X X X X X X
159
BITS 7 6 5 4 3 2 1 0
RESET X X X X X X X X
ADDR FBDH
DMAA_ADDR—DMA_ADC Address
These bits specify the seven most-significant bits of the 12-bit Register File addresses
used for storing the ADC output data. The ADC Analog Input Number defines the five
least-significant bits of the Register File address. Full 12-bit address is
{DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}.
Reserved
This bit is reserved and must be 0.
160
BITS 7 6 5 4 3 2 1 0
FIELD DAEN IRQEN Reserved ADC_IN
RESET 0 0 0 0 0 0 0 0
ADDR FBEH
DAEN—DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
IRQEN—Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC Analog
Input specified by the ADC_IN field.
Reserved
These bits are reserved and must be 0.
ADC_IN—ADC Analog Input Number
These bits set the number of ADC Analog Inputs to be used in the continuous update (data
conversion followed by DMA data transfer). The conversion always begins with ADC
Analog Input 0 and then progresses sequentially through the other selected ADC Analog
Inputs.
0000 = ADC Analog Input 0 updated.
0001 = ADC Analog Inputs 0-1 updated.
0010 = ADC Analog Inputs 0-2 updated.
0011 = ADC Analog Inputs 0-3 updated.
0100 = ADC Analog Inputs 0-4 updated.
0101 = ADC Analog Inputs 0-5 updated.
0110 = ADC Analog Inputs 0-6 updated.
0111 = ADC Analog Inputs 0-7 updated.
1000 = ADC Analog Inputs 0-8 updated.
1001 = ADC Analog Inputs 0-9 updated.
1010 = ADC Analog Inputs 0-10 updated.
1011 = ADC Analog Inputs 0-11 updated.
1100-1111 = Reserved.
161
fore, software interrupt service routines that read this register must process all three inter-
rupt sources from the DMA.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
R/W R R R R R R R R
ADDR FBFH
162
Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
• 12 analog input sources are multiplexed with general-purpose I/O ports
• Interrupt upon conversion complete
• Internal voltage reference generator
• Direct Memory Access (DMA) controller can automatically initiate data conversion
and transfer of the data from 1 to 12 of the analog inputs
Architecture
Figure 31 illustrates the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 12-input analog multiplexer selects one of the 12 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage ref-
erence for the conversion may be input through the external VREF pin or generated inter-
nally by the voltage reference generator.
163
VREF
Internal Voltage
Reference Generator Analog Input
Multiplexer
ANA0
ANA1
ANA2
Analog-to-Digital
Converter ANA3
ANA4
ANA5
Reference Input
ANA6
ANA7
ANA8
Analog Input
ANA9
ANA10
ANA11
ANAIN[3:0]
Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a conver-
sion is requested using the ADC Control register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion
are as follows:
164
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control register to configure the ADC and begin the conversion.
The bit fields in the ADC Control register can be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources.
– Clear CONT to 0 to select a single-shot conversion.
– Write to the VREF bit to enable or disable the internal voltage reference generator.
– Set CEN to 1 to start the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following
operations:
– 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
– CEN resets to 0 to indicate the conversion is complete.
– An interrupt request is sent to the Interrupt Controller.
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
Caution: In Continuous mode, users must be aware that ADC updates are limited by
the input signal bandwidth of the ADC and the latency of the ADC and its
digital filter. Step changes at the input are not seen at the next output from
the ADC. The response of the ADC (in all modes) is limited by the input
signal bandwidth and the latency.
The steps for setting up the ADC and initiating continuous conversion are as follows:
1. Enable the desired analog input by configuring the general-purpose I/O pins for
alternate function. This disables the digital input and output driver.
2. Write to the ADC Control register to configure the ADC for continuous conversion.
The bit fields in the ADC Control register may be written simultaneously:
– Write to the ANAIN[3:0] field to select one of the 12 analog input sources.
165
BITS 7 6 5 4 3 2 1 0
FIELD CEN Reserved VREF CONT ANAIN[3:0]
RESET 0 0 1 0 0000
ADDR F70H
166
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Reserved—Must be 0.
VREF
0 = Internal voltage reference generator enabled. The VREF pin should be left uncon-
nected (or capacitively coupled to analog ground) if the internal voltage reference is
selected as the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
CONT
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system
clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN—Analog Input Select
These bits select the analog input for conversion. Not all Port pins in this list are available
in all packages for the Z8F642x family of products. Refer to the Signal and Pin Descrip-
tions chapter for information regarding the Port pins available with each package style. Do
not enable unavailable analog inputs.
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = ANA8
1001 = ANA9
1010 = ANA10
1011 = ANA11
11XX = Reserved.
167
BITS 7 6 5 4 3 2 1 0
FIELD ADCD_H
RESET X
R/W R
ADDR F72H
BITS 7 6 5 4 3 2 1 0
RESET X X
R/W R R
ADDR F73H
168
Flash Memory
Overview
The products in the Z8F642x family feature up to 64KB (65,536 bytes) of non-volatile
Flash memory with read/write/erase capability. The Flash memory can be programmed
and erased in-circuit by either user code or through the On-Chip Debugger.
The Flash memory array is arranged in 512-byte per page. The 512-byte page is the mini-
mum Flash block size that can be erased. The Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.
Table 88 describes the Flash memory configuration for each device in the Z8F642x fam-
ily. Table 89 lists the sector address ranges. Figure 32 illustrates the Flash memory
arrangement.
Table 88. Flash Memory Configurations
169
64KB Flash
Program Memory
Addresses
FFFFH
FE00H
FDFFH
FC00H
FBFFH
FA00H
128 Pages
512 Bytes per Page
05FFH
0400H
03FFH
0200H
01FFH
0000H
170
Information Area
Table 90 describes the Z8F642x family Information Area. This 512-byte Information Area
is accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled,
the Information Area is mapped into Program Memory and overlays the 512 bytes at
addresses FE00H to FFFFH. When the Information Area access is enabled, LDC instruc-
tions return data from the Information Area. CPU instruction fetches always comes from
Program Memory regardless of the Information Area access bit. Access to the Information
Area is read-only.
Table 90. Z8F642x family Information Area Map
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page
Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection
mechanism, via the Flash Control register (FCTL), to prevent accidental programming or
erasure. The following subsections provide details on the various operations (Lock,
Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
171
Caution: Flash programming and erasure are not supported for system clock fre-
quencies below 20kHz, above 20MHz, or outside of the device operating
frequency range. The Flash Frequency High and Low Byte registers must
be loaded with the correct value to insure proper Flash programming and
erase operations.
172
2. Write the page to be programmed or erased to the Flash Page Select register.
3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
5. Re-write the page written in step 2 to the Flash Page Select register.
Byte Programming
When the Flash Controller is unlocked, writes to Program Memory from user code will
program a byte into the Flash if the address is located in the unlocked page. An erased
Flash byte contains all ones (FFH). The programming operation can only be used to
change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one
requires a Page Erase or Mass Erase operation.
Byte Programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions.
Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions.
173
While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a Program-
ming operation is in progress will be serviced once the Programming operation is com-
plete. To exit Programming mode and lock the Flash Controller, write 00H to the Flash
Control register.
User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page will be
programmed. Memory writes outside of the unlocked page are ignored.
Caution: Each memory location should not be programmed more than twice before
an erase occurs.
The proper steps to program the Flash from user code are:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Flash Page Select register.
3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
5. Re-write the page written in step 2 to the Flash Page Select register.
6. Write Program Memory using LDC or LDCI instructions to program the Flash.
7. Repeat step 6 to program additional memory locations on the same page.
8. Write 00H to the Flash Control register to lock the Flash Controller.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Flash Page Select register identi-
fies the page to be erased. While the Flash Controller executes the Page Erase operation,
the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The
eZ8 CPU resumes operation after the Page Erase operation completes. Interrupts that
occur when the Page Erase operation is in progress will be serviced once the Page Erase
operation is complete. When the Page Erase operation is complete, the Flash Controller
returns to its locked state. Only pages located in unprotected sectors can be erased.
The proper steps to perform a Page Erase operation are:
1. Write 00H to the Flash Control register to reset the Flash Controller.
2. Write the page to be erased to the Flash Page Select register.
3. Write the first unlock command 73H to the Flash Control register.
4. Write the second unlock command 8CH to the Flash Control register.
174
5. Re-write the page written in step 2 to the Flash Page Select register.
6. Write the Page Erase command 95H to the Flash Control register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
175
BITS 7 6 5 4 3 2 1 0
FIELD FCMD
RESET 0 0 0 0 0 0 0 0
R/W W W W W W W W W
ADDR FF8H
FCMD—Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page erase command.
63H = Mass erase command
5EH = Flash Sector Protect register select.
* All other commands, or any command out of sequence, will lock the Flash Controller.
176
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
R/W R R R R R R R R
ADDR FF8H
Reserved
These bits are reserved and must be 0.
FSTAT—Flash Controller Status
00_0000 = Flash Controller locked.
00_0001 = First unlock command received.
00_0010 = Second unlock command received.
00_0011 = Flash Controller unlocked.
00_0100 = Flash Sector Protect register selected.
00_1xxx = Program operation in progress.
01_0xxx = Page erase operation in progress.
10_0xxx = Mass erase operation in progress.
177
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FF9H
178
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
ADDR FF9H
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).
SECTn—Sector Protect
0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
* User code can only write bits from 0 to 1.
179
Caution: Flash programming and erasure is not supported for system clock frequen-
cies below 20kHz, above 20MHz, or outside of the valid operating fre-
quency range for the device. The Flash Frequency High and Low Byte
registers must be loaded with the correct value to insure proper program
and erase times.
BITS 7 6 5 4 3 2 1 0
FIELD FFREQH
RESET 0 0 0 0 0 0 0 0
ADDR FFAH
BITS 7 6 5 4 3 2 1 0
FIELD FFREQL
RESET 0 0 0 0 0 0 0 0
ADDR FFBH
180
Option Bits
Overview
Option Bits allow user configuration of certain aspects of the Z8F642x family operation.
The feature configuration data is stored in the Program Memory and read during Reset.
The features available for control via the Option Bits are:
• Watch-Dog Timer time-out response selection–interrupt or Reset.
• Watch-Dog Timer enabled at Reset.
• The ability to prevent unwanted read access to user code in Program Memory.
• The ability to prevent accidental programming and erasure of the user code in
Program Memory.
• Voltage Brown-Out configuration-always enabled or disabled during STOP mode to
reduce STOP mode power consumption.
• Oscillator mode selection-for high, medium, and low power crystal oscillators, or
external RC oscillator.
Operation
181
0000H configures user options. The byte at Program Memory address 0001H is reserved
for future use and must be left in its unprogrammed state.
BITS 7 6 5 4 3 2 1 0
FIELD WDT_RES WDT_AO OSC_SEL[1:0] VBO_AO RP Reserved FWP
RESET U U U U U U U U
182
RP—Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
FWP—Flash Write Protect
FWP Description
0 Programming, Page Erase, and Mass Erase via User Code is disabled. Mass Erase is
available through the On-Chip Debugger.
1 Programming, Page Erase, and Mass Erase are enabled for all of Flash Program
Memory.
BITS 7 6 5 4 3 2 1 0
FIELD Reserved
RESET U U U U U U U U
Reserved
These Option Bits are reserved for future use and must always be 1. This setting is the
default for unprogrammed (erased) Flash.
183
On-Chip Debugger
Overview
The Z8F642x family products contain an integrated On-Chip Debugger (OCD) that pro-
vides advanced debugging features including:
• Reading and writing of the Register File
• Reading and writing of Program and Data Memory
• Setting of Breakpoints
• Execution of eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
auto-baud generator, and debug controller. Figure 33 illustrates the architecture of the On-
Chip Debugger
Transmitter
Debug Controller
DBG
Pin Receiver
184
Operation
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bi-directional open-drain interface that transmits and receives data.
Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously.
The serial data on the DBG pin is sent using the standard asynchronous data format
defined in RS-232. This pin can interface the Z8F642x family products to the serial port of
a host PC using minimal external hardware.Two different methods for connecting the
DBG pin to an RS-232 interface are depicted in Figures 34 and 35.
Caution: For operation of the On-Chip Debugger, all power pins (VDD and AVDD)
must be supplied with power, and all ground pins (VSS and AVSS) must be
properly grounded.
The DBG pin is open-drain and must always be connected to VDD through
an external pull-up resistor to ensure proper operation.
VDD
RS-232
Transceiver 10K Ohm
Diode
RS-232 TX DBG Pin
RS-232 RX
Figure 34. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)
185
VDD
RS-232
Transceiver 10K Ohm
Open-Drain
Buffer
RS-232 TX DBG Pin
RS-232 RX
Figure 35. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
Debug Mode
The operating characteristics of the Z8F642x family devices in Debug mode are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
• The system clock operates unless in STOP mode.
• All enabled on-chip peripherals operate unless in STOP mode.
• Automatically exits HALT mode.
• Constantly refreshes the Watch-Dog Timer, if enabled.
186
• Power-on reset
• Voltage Brown Out reset
• Asserting the RESET pin Low to initiate a Reset.
• Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
System Clock Frequency Recommended Maximum Baud Rate Minimum Baud Rate
(MHz) (kbits/s) (kbits/s)
20.0 2500 39.1
1.0 125.0 1.96
0.032768 (32KHz) 4.096 0.064
187
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured
by sending 80H.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are
enabled, the OCD idles the eZ8 CPU and enters Debug mode. If Breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter Debug
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the inter-
rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debug-
ging software should not automatically enable interrupts when using this feature, since
interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
188
Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop-
ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it
is looping on, software should not set the DBGMODE bit of the OCDCTL register. The
CPU may have vectored to and be in the middle of an interrupt service routine when this
bit gets set. Instead, software should clear the BRKLP bit. This allows the CPU to finish
the interrupt service routine it may be in and return the BRK instruction. When the CPU
returns to the BRK instruction it was previously looping on, it automatically sets the
DBGMODE bit and enter Debug mode.
Software should detect that the majority of the OCD commands are still disabled when the
eZ8 CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part
must be in Debug mode before these commands can be issued.
OCDCNTR Register
The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used
for the following:
• Count system clock cycles between Breakpoints.
• Generate a BRK when it counts down to zero.
• Generate a BRK when its value matches the Program Counter.
When configured as a counter, the OCDCNTR register starts counting when the On-Chip
Debugger leaves Debug mode and stops counting when it enters Debug mode again or
when it reaches the maximum count of FFFFH. The OCDCNTR register automatically
resets itself to 0000H when the OCD exits Debug mode if it is configured to count clock
cycles between breakpoints.
Caution: The OCDCNTR register is used by many of the OCD commands. It counts the
number of bytes for the register and memory read/write commands. It holds the
residual value when generating the CRC. Therefore, if the OCDCNTR is being
used to generate a BRK, its value should be written as a last step before leaving
Debug mode.
Because this register is overwritten by various OCD commands, it should only be used to
generate temporary breakpoints, such as stepping over CALL instructions or running to a
specific instruction and stopping.
189
190
In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by ’DBG ← Command/Data’. Data sent from the
On-Chip Debugger back to the host is identified by ’DBG → Data’
• Read OCD Revision (00H)—The Read OCD Revision command determines the
version of the On-Chip Debugger. If OCD commands are added, removed, or
changed, this revision number changes.
DBG ← 00H
DBG → OCDREV[15:8] (Major revision number)
DBG → OCDREV[7:0] (Minor revision number)
• Write OCD Counter Register (01H)—The Write OCD Counter Register command
writes the data that follows to the OCDCNTR register. If the device is not in Debug
mode, the data is discarded.
DBG ← 01H
DBG ← OCDCNTR[15:8]
DBG ← OCDCNTR[7:0]
• Read OCD Status Register (02H)—The Read OCD Status Register command reads
the OCDSTAT register.
DBG ← 02H
DBG → OCDSTAT[7:0]
• Read OCD Counter Register (03H)—The OCD Counter Register can be used to
count system clock cycles in between Breakpoints, generate a BRK when it counts
down to zero, or generate a BRK when its value matches the Program Counter. Since
this register is really a down counter, the returned value is inverted when this register
is read so the returned result appears to be an up counter. If the device is not in Debug
mode, this command returns FFFFH.
DBG ← 03H
DBG → ~OCDCNTR[15:8]
DBG → ~OCDCNTR[7:0]
• Write OCD Control Register (04H)—The Write OCD Control Register command
writes the data that follows to the OCDCTL register. When the Read Protect Option
Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be
191
cleared to 0 and the only method of putting the device back into normal operating
mode is to reset the device.
DBG ← 04H
DBG ← OCDCTL[7:0]
• Read OCD Control Register (05H)—The Read OCD Control Register command
reads the value of the OCDCTL register.
DBG ← 05H
DBG → OCDCTL[7:0]
• Write Program Counter (06H)—The Write Program Counter command writes the
data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in
Debug mode or if the Read Protect Option Bit is enabled, the Program Counter (PC)
values are discarded.
DBG ← 06H
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
• Read Program Counter (07H)—The Read Program Counter command reads the
value in the eZ8 CPU’s Program Counter (PC). If the device is not in Debug mode or
if the Read Protect Option Bit is enabled, this command returns FFFFH.
DBG ← 07H
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
• Write Register (08H)—The Write Register command writes data to the Register File.
Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to
zero). If the device is not in Debug mode, the address and data values are discarded. If
the Read Protect Option Bit is enabled, then only writes to the Flash Control Registers
are allowed and all other register write data values are discarded.
DBG ← 08H
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1-256 data bytes
• Read Register (09H)—The Read Register command reads data from the Register
File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to
zero). If the device is not in Debug mode or if the Read Protect Option Bit is enabled,
this command returns FFH for all the data values.
DBG ← 09H
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG → 1-256 data bytes
192
• Write Program Memory (0AH)—The Write Program Memory command writes data
to Program Memory. This command is equivalent to the LDC and LDCI instructions.
Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size
to zero). The on-chip Flash Controller must be written to and unlocked for the
programming operation to occur. If the Flash Controller is not unlocked, the data is
discarded. If the device is not in Debug mode or if the Read Protect Option Bit is
enabled, the data is discarded.
DBG ← 0AH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
• Read Program Memory (0BH)—The Read Program Memory command reads data
from Program Memory. This command is equivalent to the LDC and LDCI
instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by
setting size to zero). If the device is not in Debug mode or if the Read Protect Option
Bit is enabled, this command returns FFH for the data.
DBG ← 0BH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
• Write Data Memory (0CH)—The Write Data Memory command writes data to Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be
written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). If
the device is not in Debug mode or if the Read Protect Option Bit is enabled, the data
is discarded.
DBG ← 0CH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
• Read Data Memory (0DH)—The Read Data Memory command reads from Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be
read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the
device is not in Debug mode, this command returns FFH for the data.
DBG ← 0DH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
193
DBG ← Size[7:0]
DBG → 1-65536 data bytes
• Read Program Memory CRC (0EH)—The Read Program Memory CRC command
computes and returns the CRC (cyclic redundancy check) of Program Memory using
the 16-bit CRC-CCITT polynomial. If the device is not in Debug mode, this command
returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a
delay from issuing of the command until the OCD returns the data. The OCD reads the
Program Memory, calculates the CRC value, and returns the result. The delay is a
function of the Program Memory size and is approximately equal to the system clock
period multiplied by the number of bytes in the Program Memory.
DBG ← 0EH
DBG → CRC[15:8]
DBG → CRC[7:0]
• Step Instruction (10H)—The Step Instruction command steps one assembly
instruction at the current Program Counter (PC) location. If the device is not in Debug
mode or the Read Protect Option Bit is enabled, the OCD ignores this command.
DBG ← 10H
• Stuff Instruction (11H)—The Stuff Instruction command steps one assembly
instruction and allows specification of the first byte of the instruction. The remaining
0-4 bytes of the instruction are read from Program Memory. This command is useful
for stepping over instructions where the first byte of the instruction has been
overwritten by a Breakpoint. If the device is not in Debug mode or the Read Protect
Option Bit is enabled, the OCD ignores this command.
DBG ← 11H
DBG ← opcode[7:0]
• Execute Instruction (12H)—The Execute Instruction command allows sending an
entire instruction to be executed to the eZ8 CPU. This command can also step over
Breakpoints. The number of bytes to send for the instruction depends on the opcode. If
the device is not in Debug mode or the Read Protect Option Bit is enabled, the OCD
ignores this command
DBG ← 12H
DBG ← 1-5 byte opcode
194
A “reset and stop” function can be achieved by writing 81H to this register. A “reset and
go” function can be achieved by writing 41H to this register. If the device is in Debug
mode, a “run” function can be implemented by writing 40H to this register.
BITS 7 6 5 4 3 2 1 0
RESET 0 0 0 0 0 0 0 0
DBGMODE—Debug Mode
Setting this bit to 1 causes the device to enter Debug mode. When in Debug mode, the eZ8
CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start running
again. This bit is automatically set when a BRK instruction is decoded and Breakpoints
are enabled. If the Read Protect Option Bit is enabled, this bit can only be cleared by reset-
ting the device, it cannot be written to 0.
0 = The Z8F642x family device is operating in Normal mode.
1 = The Z8F642x family device is in Debug mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded if
breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automat-
ically set to 1 and the OCD entered Debug mode. If BRKLOOP is set to 1, then the eZ8
CPU loops on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
195
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR == 0000H
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to 0000H. If this bit is set, the OCDCNTR register is not reset
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to 0000H
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H
Reserved
These bits are reserved and must be 0.
RST—Reset
Setting this bit to 1 resets the Z8F642x family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the Z8F642x family device.
BITS 7 6 5 4 3 2 1 0
FIELD IDLE HALT RPEN Reserved
RESET 0 0 0 0 0 0 0 0
R/W R R R R R R R R
IDLE—CPU idling
This bit is set if the part is in Debug mode (DBGMODE is 1), or if a BRK instruction
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
196
197
On-Chip Oscillator
Overview
The products in the Z8F642x family feature an on-chip oscillator for use with external
crystals with frequencies from 32KHz to 20MHz. In addition, the oscillator can support
external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with
oscillation frequencies up to 20MHz. This oscillator generates the primary system clock
for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the
XIN input pin can also accept a CMOS-level clock input signal (32kHz–20MHz). If an
external clock generator is used, the XOUT pin must be left unconnected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (that is, no
internal clock divider). In RC operation, the system clock is driven by a clock divider
(divide by 2) to ensure 50% duty cycle.
Operating Modes
The Z8F642x family products support 4 different oscillator modes:
• On-chip oscillator configured for use with external RC networks (<4MHz).
• Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).
• Medium power for use with medium frequency crystals or ceramic resonators
(0.5MHz to 10.0MHz).
• Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz
to 20.0MHz).
The oscillator mode is selected via user-programmable Option Bits. Please refer to the
Option Bits chapter for information.
198
stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the
values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN XOUT
R1 = 220Ω
Crystal
C1 = 22pF C2 = 22pF
199
XIN
6
1 ×10
Oscillator Frequency (kHz) = -------------------------------
-
( 1.5 × R × C )
Figure 39 illustrates the typical (3.3V and 250C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 15kΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
200
1000
900
800
700
600
F (kHz)
500
400
300
200
100
0
0 100 200 300 400 500 600 700 800 900 1000
C (pF)
Figure 39. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 15kΩ Resistor
201
Electrical Characteristics
All data in this chapter is pre-qualification and pre-characterization and is subject to
change.
202
203
DC Characteristics
Table 105 lists the DC characteristics of the Z8F642x family products. All voltages are
referenced to VSS, the primary system ground.
Table 105. DC Characteristics
TA = -400C to 1050C
204
TA = -400C to 1050C
205
Figure 40 illustrates the typical current consumption while operating at 25ºC, 3.3V, versus
the system clock frequency.
stics
TBD
Figure 40. Nominal ICC Versus System Clock Frequency
206
Figure 41 illustrates the typical current consumption in HALT mode while operating at
25ºC, 3.3V, versus the system clock frequency.
TBD
Figure 41. Nominal HALT Mode ICC Versus System Clock Frequency
Table 106. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
TA = -400C to 1050C
1 Data in the typical column is from characterization at 3.3V and 00C. These values are provided for design guidance
only and are not tested in production.
207
TA = -400C to 1050C
Table 108 list the Flash Memory electrical characteristics and timing. Table 109 lists the
Watch-Dog Timer electrical characteristics and timing.
208
Table 110 lists the Analog-to-Digital Converter electrical characteristics and timing.
209
AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing
information assumes a standard load of 50pF on all outputs. Table 111 lists the Z8F642
family AC characteristics and timing.
Table 111. AC Characteristics
210
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Delay (ns)
211
TCLK
XIN
T1 T2
Port Output
Delay (ns)
212
TCLK
XIN
T1 T2
T3 T4
Delay (ns)
213
SCK
T1
T2 T3
Delay (ns)
214
SCK
T1
T2 T3
T4
SS
(Input)
Delay (ns)
215
I2C Timing
Figure 47 and Table 117 provide timing information for I2C pins.
SCL
(Output)
T1
T3
T2
Delay (ns)
216
UART Timing
Figure 48 and Table 118 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has
been loaded with data prior to CTS assertion.
CTS
(Input)
T1
DE
(Output)
T2 T3
TXD Stop
Start Bit 0 Bit 1 Bit 7 Parity
(Output)
End of
Stop Bit(s)
Delay (ns)
217
Figure 49 and Table 119 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data register is writ-
ten with the next character before the current character has completed.
DE
(Output)
T1 T2
TXD Stop
Start Bit 0 Bit 1 Bit 7 Parity
(Output)
End of
Stop Bit(s)
Delay (ns)
218
219
; value 01H, is the source. The value 01H is written into the
; Register at address 234H.
Example 2: In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0 - 255 or, using Escaped Mode
Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is:
Assembly Language Syntax Example 2
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
220
.
Table 120. Notational Shorthand
Table 121 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.
221
Symbol Definition
dst Destination Operand
src Source Operand
@ Indirect Address Prefix
SP Stack Pointer
PC Program Counter
FLAGS Flags Register
RP Register Pointer
# Immediate Operand Prefix
B Binary Number Suffix
% Hexadecimal Number Prefix
H Hexadecimal Number Suffix
222
Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc), which forms Bits 7:4 of the conditional jump instruc-
tions. The condition codes are summarized in Table 122. Some binary condition codes can
be created using more than one assembly code mnemonic. The result of the flag test oper-
ation decides if the conditional jump is executed.
Assembly
Binary Hex Mnemonic Definition Flag Test Operation
0000 0 F Always False –
0001 1 LT Less Than (S XOR V) = 1
0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1
0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1
0100 4 OV Overflow V=1
0101 5 Ml Minus S=1
0110 6 Z Zero Z=1
0110 6 EQ Equal Z=1
0111 7 C Carry C=1
0111 7 ULT Unsigned Less Than C=1
1000 8 T (or blank) Always True –
1001 9 GE Greater Than or Equal (S XOR V) = 0
1010 A GT Greater Than (Z OR (S XOR V)) = 0
1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) = 1
1100 C NOV No Overflow V=0
1101 D PL Plus S=0
1110 E NZ Non-Zero Z=0
1110 E NE Not Equal Z=0
1111 F NC No Carry C=0
1111 F UGE Unsigned Greater Than or Equal C = 0
223
224
225
226
227
228
229
230
231
232
233
RLC dst R 10 * * * * - - 2 2
C D7 D6 D5 D4 D3 D2 D1 D0
dst IR 11 2 3
RR dst R E0 * * * * - - 2 2
D7 D6 D5 D4 D3 D2 D1 D0 C
dst IR E1 2 3
RRC dst R C0 * * * * - - 2 2
D7 D6 D5 D4 D3 D2 D1 D0 C
dst IR C1 2 3
234
SRL dst 0 D7 D6 D5 D4 D3 D2 D1 D0 C R 1F C0 * * 0 * - - 3 2
dst
IR 1F C1 3 3
235
236
237
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z
and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at
initial power-up and are unaffected by Reset. Figure 50 illustrates the flags and their bit
positions in the Flags Register.
Bit Bit
7 0
C Z S V D H F2 F1 Flags Register
User Flags
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
U = Undefined
Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all write
the value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruc-
tion restores the value saved on the stack into the Flags Register.
238
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 51 and
Table 132. Figures 52 and 53 provide information on each of the eZ8 CPU instructions.
Opcode
Lower Nibble
3.3
Opcode
Upper Nibble A CP
R2,R1
239
240
2.2 2.3 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.2
7 PUSH PUSH TM TM TM TM TM TM TMX TMX HALT
R2 IR2 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.5 2.6 2.5 2.9 3.2 3.3 3.4 3.5 3.4 3.4 1.2
8 DECW DECW LDE LDEI LDX LDX LDX LDX LDX LDX DI
RR1 IRR1 r1,Irr2 Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2 2.3 2.5 2.9 3.2 3.3 3.4 3.5 3.3 3.5 1.2
9 RL RL LDE LDEI LDX LDX LDX LDX LEA LEA EI
R1 IR1 r2,Irr1 Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5 2.6 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.4
A INCW INCW CP CP CP CP CP CP CPX CPX RET
RR1 IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.5
B CLR CLR XOR XOR XOR XOR XOR XOR XORX XORX IRET
R1 IR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.5 2.9 2.3 2.9 3.4 3.2 1.2
C RRC RRC LDC LDCI JP LDC LD PUSHX RCF
R1 IR1 r1,Irr2 Ir1,Irr2 IRR1 Ir1,Irr2 r1,r2,X ER2
2.2 2.3 2.5 2.9 2.6 2.2 3.3 3.4 3.2 1.2
D SRA SRA LDC LDCI CALL BSWAP CALL LD POPX SCF
R1 IR1 r2,Irr1 Ir2,Irr1 IRR1 R1 DA r2,r1,X ER1
2.2 2.3 2.2 2.3 3.2 3.3 3.2 3.3 4.2 4.2 1.2
E RR RR BIT LD LD LD LD LD LDX LDX CCF
R1 IR1 p,b,r1 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.6 2.3 2.8 3.3 3.3 3.4
F SWAP SWAP TRAP LD MULT LD BTJ BTJ
R1 IR1 Vector Ir1,r2 RR1 R2,IR1 p,b,r1,X p,b,Ir1,X
241
6
Upper Nibble (Hex)
3.2 3.3
C SRL SRL
R1 IR1
242
Packaging
Figure 54 illustrates the 40-pin PDIP (plastic dual-inline package) available for the
Z8F1601, Z8F2401, Z8F3201, Z8F4801, and Z8F6401 devices.
243
Figure 55 illustrates the 44-pin LQFP (low profile quad flat package) available for the
Z8F1621, Z8F2421, Z8F3221, Z8F4821, and Z8F6421 devices.
HD A
D A2
A1
E HE
DETAIL A
LE
e b
0-7°
244
Figure 56 illustrates the 44-pin PLCC (plastic lead chip carrier) package available for the
Z8F1621, Z8F2421, Z8F3221, Z8F4821, and Z8F6421 devices.
A
D A1
D1 0.71/0.51
D2
E1 E M
D/E 17.40 17.65 0.685 0.695
Figure 56 illustrates the 64-pin LQFP (low-profile quad flat package) available for the
Z8F1622, Z8F2422, Z8F3222, Z8F4822, and Z8F6422 devices.
HD A
D A2
A1
E HE
DETAIL A
LE
c
e b
0-7°
245
Figure 58 illustrates the 68-pin PLCC (plastic lead chip carrier) package available for the
Z8F1622, Z8F2422, Z8F3222, Z8F4822, and Z8F6422 devices.
246
Figure 59 illustrates the 80-pin QFP (quad flat package) available for the Z8F4823 and
Z8F6423 devices.
HD
A2
D
64 41 A1 MILLIMETER INCH
SYMBOL
MIN MAX MIN MAX
A1 0.10 0.38 .004 .015
65 40
A2 2.60 2.80 .102 .110
b 0.30 0.45 .012 .018
c 0.13 0.20 .005 .008
E HE HD 23.70 24.15 .933 .951
D 19.90 20.10 .783 .791
HE 17.70 18.15 .697 .715
E 13.90 14.10 .547 .555
80 25
e 0.80 BSC .0315 BSC
L 0.70 1.10 .028 .043
1 24 c
b e DETAIL A
NOTES:
CONTROLLING DIMENSIONS : MILLIMETER
2. LEAD COPLANARITY : MAX .10
.004"
0-10°
DETAIL A
247
Ordering Information
Table 133. Ordering Information
248
249
To gain access to technical and customer support, hardware and software development
tools, visit the ZiLOG web site at www.zilog.com. The latest released version of ZDS can
be downloaded from this site.
250
Packages A = LQFP
F = QFP
P = PDIP
V = PLCC
Pin Count M = 40 pins
N = 44 pins
R = 64 pins
S = 68 pins
T = 80 pins
Speed 020 = 20MHz
Temperature E = -40ºC to +105ºC
S = 0ºC to +70ºC
Environmental Flow C = Plastic-Standard
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not com-
pleted the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times, due to start-up yield issues.
ZiLOG, Inc.
251
Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document
contains unique identifying attributes, as indicated by the example in the following table:
PS Product Specification
0176 Unique Document Number
01 Revision Number
0702 Month and Year Published
252
Customer Information
Name Country
Company Phone
Address Fax
City/State/Zip E-Mail
Product Information
Part #, Serial #, Board Fab #, or Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126
Fax: (408) 558-8536
Email: tools@zilog.com
253
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______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
254
255
256
257
258
259
M O
master interrupt enable 65 OCD
master-in, slave-out and-in 128 architecture 183
memory auto-baud detector/generator 186
program 18 baud rate limits 186
MISO 128 block diagram 183
mode breakpoints 187
capture 91 commands 189
capture/compare 91 control register 193
continuous 91 data format 186
counter 91 DBG pin to RS-232 Interface 184
gated 91 debug mode 185
one-shot 91 debugger break 226
PWM 91 interface 184
modes 91 serial errors 187
MOSI 128 status register 195
MULT 223 timing 212
multiply 223 OCD commands
multiprocessor mode, UART 106 execute instruction (12H) 193
read data memory (0DH) 192
read OCD control register (05H) 191
N read OCD revision (00H) 190
read OCD status register (02H) 190
NOP (no operation) 225
read program counter (07H) 191
not acknowledge interrupt 141 read program memory (0BH) 192
notation read program memory CRC (0EH) 193
b 220 read register (09H) 191
cc 220 read runtime counter (03H) 190
DA 220 step instruction (10H) 193
ER 220 stuff instruction (11H) 193
IM 220 write data memory (0CH) 192
IR 220 write OCD control register (04H) 190
Ir 220 write program counter (06H) 191
IRR 220 write program memory (0AH) 192
Irr 220 write register (08H) 191
p 220 on-chip debugger 5
R 220 on-chip debugger (OCD) 183
r 220 on-chip debugger signals 15
RA 220 on-chip oscillator 197
RR 220 one-shot mode 91
rr 220 opcode map
vector 220 abbreviations 239
X 220 cell description 238
notational shorthand 220 first 240
260
261
262
263
103 CNTL 47
TRAP 226 control register 96
electrical characteristics and timing 207
U interrupt in noromal operation 94
UART 4
interrupt in STOP mode 94
architecture 100
asynchronous data format without/with parity operation 93
102 refresh 94, 225
baud rate generator 110
baud rates table 119 reload unlock sequence 95
control register definitions 111 reload upper, high and low registers 97
controller signals 14
reset 47
data format 101
interrupts 108 reset in normal operation 95
multiprocessor mode 106 reset in STOP mode 95
receiving data using interrupt-driven method
104 time-out response 94
receiving data using the polled method 104 WDTCTL register 96
transmitting data usin the interrupt-driven
WDTH register 98
method 103
transmitting data using the polled method 102 WDTL register 99
x baud rate high and low registers 118 working register 220
x control 0 and control 1 registers 114
x status 0 and status 1 registers 112, 114 working register pair 220
UxBRH register 118 WTDU register 98
UxBRL register 118
UxCTL0 register 114, 117
UxCTL1 register 116 X
UxRXD register 112
UxSTAT0 register 112 X 220
UxSTAT1 register 114 XOR 226
UxTXD register 111
XORX 226
V
vector 220 Z
voltage brown-out reset (VBR) 46
Z8 Encore!
block diagram 3
W features 1
watch-dog timer
approximate time-out delay 94 introduction 1
approximate time-out delays 93 part selection guide 2
264