Analog Integrated Circuits and Signal Processing, 40, 71–74, 2004

c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.

Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

ANTONIO J. LÓPEZ-MARTÍN,1,∗ ALFONSO CARLOSENA1 AND JAIME RAMIREZ-ANGULO2

1
Department of Electrical and Electronic Engineering, Public University of Navarra, Campus Arrosadı́a. E-31006, Pamplona (Spain)
2
Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA
E-mail: antonio.lopez@unavarra.es; carlosen@unavarra.es; jramirez@nmsu.edu

Received November 13, 2002; Revised December 23, 2002; Accepted December 23, 2002

Abstract. A novel technique for operating MOS Translinear loops at very low supply voltages is described, based
on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS
processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multi-
pliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider
circuit demonstrate on silicon the usefulness of this technique.

Key Words: voltage-translinear circuits, low-voltage analog circuits, analog CMOS circuits

1. Introduction as Voltage-TL loops [2]. A novel biasing scheme

The ongoing reduction of supply voltage driven by
submicron digital CMOS circuits and battery-operated
equipment forces CMOS analog circuits aimed to
mixed-mode designs to conform to this trend. Analog
signal processing at supply voltages close to the MOS
threshold voltage is best performed in current-mode,
so that voltage swings are nonlinearly compressed and
therefore become less constrained by supply voltage
limitations. Both static and dynamic circuits based on
the TransLinear (TL) principle [1] show this current-
mode behavior. Unfortunately, most of their proposed
CMOS implementations do not optimally exploit the
potential of this technique for very low supply voltage
(e.g., [2, 3]).
Recently a TL technique in CMOS technology has
been proposed [4], suited to very low supply volt-
ages. Loop transistors are operated in weak inversion,
which leads to low power consumption but also to
poor matching characteristics and bandwidths in the
order of tens of kHz. In this Letter we propose an al-
ternative approach that does not have the aforemen-
tioned limitations and still allows low-voltage opera-
tion. Loop transistors are operated in strong inversion
and saturation, so that the MOS square law is exploited,
leading to the so-called MOS TL loops, also known
∗ Corresponding author.
based on the Flipped-Voltage Follower (FVF) cell [5]
leads to a significant performance improvement and
to reduced supply voltage requirements. The resulting
topology can replace conventional ones employed for
implementing static nonlinear computational circuits
(e.g., geometric-mean, squarer/divider, multiplier, vec-
tor normalization) or dynamic linear and nonlinear cir-
cuits (e.g., companding filters, oscillators, RMS-DC
converters) using the techniques described in [3, 6].
2. Circuit Description
Figure 1 shows a folded second-order MOS TL loop,
where it is assumed that all transistors are operating in
strong inversion and saturation. The sum of voltages
around the loop is zero, so that
VGS1 + VGS2 = VGS3 + VGS4 (1)
Using the MOS square law, the MOS gate-to-source
voltage V GS is related to its drain current I D by


2 
VGS = I D + VTH (2)
kn (W/L)
where all the parameters have their usual meanings.
Using (2) in (1) and assuming that all transistors are
72 López-Martı́n, Carlosena and Ramirez-Angulo

From (1), the operation of TL loops only deter-

mines the relative values of nodal voltages, but they
are not set in an absolute sense. However, in prac-
tice a reference DC voltage must be set in some node
of the loop (hence determining that of all the nodes)
for proper operation. This voltage is usually set by
the additional circuitry that is anyway necessary for
injecting the loop currents with the functional depen-
Fig. 1. Second-order folded Voltage-Translinear Loop. dence required for a certain application (e.g., Eq. (4)
in our case). In particular, the well-known structure of
Fig. 2(a) [2, 3] is frequently employed for this purpose.
equal, loop currents become related by However, the diode-connected MOSFET of the cur-
    rent mirror precludes very low voltage operation due
I1 + I2 = I3 + I4 (3) to the stacking of two gate-source voltages. Moreover,
the impedance at its drain terminal, where the reference
Hence, several nonlinear current-mode functions can DC level is established, is not very low. This fact makes
be implemented by properly injecting such currents. the loop nodal voltages dependent on the current sink
For instance, if we force by this diode-connected transistor, thus notably lim-
I1 + I2 + 2I5 iting the range of current levels achievable for a cer-
I3 = I4 = (4) tain supply voltage. In addition, it influences the loop
4
bandwidth.
being I5 a certain current, after squaring both sides in The novel topology shown in Fig. 2(b) imple-
(3) and rearranging it can be shown that the TL loop ments (5) solving all these issues. Now a FVF, formed
forces this current I5 to be by transistors M F1 − M F2 and current source I B , sets
 the proper DC voltage at the loop nodes. It is a very
I5 = I1 I2 (5) simple feedback circuit that creates an extremely low
impedance node (the source of M F1 ) with an ac-
Therefore, a geometric-mean circuit is obtained if I1 curately controllable DC voltage (determined by I B
and I2 are the input currents and the output current is a and the dimensions of transistor M F1 ). Hence volt-
copy of I5 . Alternatively, a squarer/divider is obtained age at this node is kept essentially constant regard-
if the output is a copy of I2 and the inputs are I5 and I1 . less of the input and output current levels. This fact

Fig. 2. Biasing of Voltage-Translinear loops: (a) conventional approach and (b) Proposed approach.
 Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers
Fig. 3. Measured and ideal geometric-mean outputs for different
input currents.
enhances the sinking capability of transistor M F2
and improves loop bandwidth. If the aspect ratio
of M F1 is properly chosen, I B can be made small,
so that the increase in current consumption is very
modest.
3. Measurement Results
In order to validate the proposed technique, a
geometric-mean circuit and a squarer/divider circuit
were fabricated in a 2.4-µm DPDM n-well CMOS pro-
cess. Both topologies correspond to Fig. 2(b), being
the only difference between them that the output cur-
rent was a copy of I5 for the geometric-mean cell and
a copy of I2 for the squarer/divider cell, as mentioned
previously. Simple current mirrors were employed for
injecting the currents shown in Fig. 2(b). The aspect
ratio of the loop transistors was 80 µm/4.8 µm, and
bias current was I B = 2µA. The supply voltage em-
ployed was 1.5 V. Figure 3 shows the output current
of the geometric-mean cell for input current I1 varying
from 0 to 10 µA and input current I2 stepped from
2 to 6 µA in 2 µA steps. The theoretical response
is shown in the dotted curves, whereas the measured
one corresponds to the solid curves. Note how the
circuit can operate as a variable-gain square-rooting
cell.
Figure 4 shows the output of the squarer/divider cell
for input currents I5 = 10µA and I1 varying from 0
to 10 µA. The relative error of the output is less than
73
Fig. 4. Measured and ideal outputs of the squarer/divider circuit.
2.5%. A similar accuracy is observed for the geometric-
mean cell. The total silicon area employed for ei-
ther the geometric-mean circuit or the squarer/divider
circuit (pads excluded) was 0.09 mm2 . The power
consumption in both cases was 210 µW, using 10-
µA DC input currents. Bandwidth was only simu-
lated due the influence of breadboard parasitics. It
was relatively poor (approx. 5 MHz in both cases)
due to the large gate length of the loop transistors.
Nevertheless, the bandwidth of the geometric-mean
circuit and the squarer/divider circuit using the con-
ventional configuration of Fig. 2(a) and identical tran-
sistor dimensions and bias currents was even lower
(3.9 MHz), so that the FVF cell led to a 28% increase in
bandwidth.
A better technology allows further reduction of the
supply voltage. Simulation results using BISM3v3
models for a 0.8-µm DPDM n-well CMOS technology
show similar performance using a single 1.2-V supply
voltage.
4. Conclusions
A novel technique for MOS Translinear loops is
proposed, that allows operation at very low sup-
ply voltages. It can be employed in standard CMOS
processes, so that it is an interesting choice in
mixed-signal designs. Experimental results for a
geometric-mean cell and a squarer/divider fabri-
cated using this technique validate the proposed
approach.
74 López-Martı́n, Carlosena and Ramirez-Angulo
Acknowledgment
This work has been supported by the Spanish Dirección
General de Investigación under grant TIC2003-07307-
C02-02.
References
1. B. Gilbert, “Translinear circuits: An historical overview.” Analog
Integrated Circuits and Signal Processing, vol. 9, no. 2, pp. 95–
118, 1996.
2. E. Seevinck and R.J. Wiegerink, “Generalized translinear circuit
principle.”IEEE J. Solid-State Circuits, vol. 26, no. 8, pp. 1098–
1102, 1991.
3. A.J. Lopez-Martin and A. Carlosena, “Current-mode multi-
plier/divider circuits based on the MOS translinear principle.”
Analog Integrated Circuits and Signal Processing, vol. 28, no. 3,
pp. 265–278, 2001.
4. E. Seevinck, E. Vittoz, M. Du Plessis, T.H. Joubert, and W.
Beetge, “CMOS translinear circuits for minimum supply volt-
age.” IEEE Tran. Circ. Syst. II, vol. 47, no. 12, pp. 1560–1564,
2000.
5. J. Ramirez-Angulo, R.G. Carvajal, A. Torralba, A. Galan, A.P.
Vega-Leal, and J. Tombs, “The flipped voltage follower: A useful
cell for low-voltage low-power circuit design,” in Proc. ISCAS
2002, Phoenix, AZ, pp. III615–III618.
6. A.J. Lopez-Martin and A. Carlosena, “Systematic design of com-
panding systems by component substitution.” Analog Integrated
Circuits and Signal Processing, vol. 28, no. 1, pp. 91–106,
2001.