VCS VirSim

and VirSim
TM

Tutorial
Version 4.4

September 2003
Copyright Notice and Proprietary Information
Copyright  2001 Synopsys, Inc. All rights reserved. This software and documentation are owned by Synopsys,
Inc., and furnished under a license agreement. The software and documentation may be used or copied only in
accordance with the terms of the license agreement. No part of the software and documentation may be repro-
duced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or other-
wise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Right to Copy Documentation
The license agreement with Synopsys permits licensee to make copies of the documentation for its in-
ternal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary
rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall con-
tain the following legend on the cover page:
“This document is duplicated with the permission of Synopsys, Inc. for the exclu-
sive use of __________________________________________ and its employ-
ees. This is copy number __________.”

Destination Control Statement

All technical data contained in this publication is subject to the export control laws of the United States
of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is
the reader’s responsibility to determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IM-
PLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys, the Synopsys logo, Arcadia, BiNMOS-CBA, CMOS-CBA, COSSAP, DESIGN (ARROWS),
DesignPower, DesignWare, dont_use, EPIC, ExpressModel, in-Sync, LM-1000, LM-1200, Logic
Modeling, Logic Modeling (logo), Memory Architect, ModelAccess, ModelTools, PathMill, PLdebug,
RailMill, SmartLicense, SmartLogic, SmartModel, SmartModels, SNUG, SOLV-IT!, SourceModel
Library, Stream Driven Simulator, Synopsys, Synopsys (logo), Synopsys VHDL Compiler, Synthetic
Designs, Synthetic Libraries, TestBench Manager, and TimeMill are registered trademarks of
Synopsys, Inc
3-D Debugging, AMPS, Behavioral Compiler, CBA Design System, CBA-Frame, characterize, Chip
Architect, Compiled Designs, Core Network, Core Store, Cyclone, Data Path Express, DataPath
Architect, DC Expert, DC Expert Plus, DC Professional, DelayMill, Design Advisor, Design Analyzer,
Design Compiler, DesignSource, DesignTime, DesignWare Developer, Direct RTL, Direct Silicon
Access, dont_touch, dont_touch_network, ECL Compiler, ECO Compiler, Embedded System
Prototype, Floorplan Manager, Formality, FoundryModel, FPGA Compiler, FPGA Express, Frame
Compiler, General Purpose Post-Processor, GPP, HDL Advisor, HDL Compiler, Integrator, Interactive
Waveform Viewer, Library Compiler, LM-1400, LM-700, LM-family, Logic Model, ModelSource,
ModelWare, Module Compiler, MS-3200, MS-3400, Power Compiler, PowerArc, PowerGate,
PowerMill, PrimeTime, RTL Analyzer, Shadow Debugger, Silicon Architects, SimuBus, SmartCircuit,
SmartModel Windows, Source-Level Design, SourceModel, SWIFT, SWIFT Interface, Synopsys
Graphical Environment, Test Compiler, Test Compiler Plus, Test Manager, TestSim, Timing Annotator,
Trace-On-Demand, VCS, VCSi, VHDL System Simulator, VirSim, Visualyze, Vivace, VSS Expert,
and VSS Professional are trademarks of Synopsys, Inc.
All other product or company names may be trademarks of their respective owners.

Printed in the U.S.A.

Document Order Number 37569-000 KB
VirSim Tutorial version 4.4
 Table of Contents

Chapter 1 - Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Tutorial Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introducing Virsim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
VirSim Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Tool Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Getting Started with VCS VirSim or VirSim . . . . . . . . . . . . . . . . . . . . . . . 1-5
Verilog Code Instrumentation and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Starting VCS VirSim or VirSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Chapter 2 - Delta Cycle Debugging . . . . . . . . . . . . . . . . . . . 2-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Analyzing Data from Two Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Viewing Delta Cycles, Glitches and User-Defined Events . . . . . . . . . . . . . . . 2-4
Determining Origins of Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Editing Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Chapter 3 - Debugging Functional Designs . . . . . . . . . . . . . . 3-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Using the Hierarchy Browser Search Features . . . . . . . . . . . . . . . . . . . . . 3-3
Searching for and Marking a Value of Interest . . . . . . . . . . . . . . . . . . . . 3-11
Stepping Value Changes on Signals of Interest . . . . . . . . . . . . . . . . . . . 3-12
Tracing a Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Debugging with the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Testing a Code Fix with Expressions . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Zooming the Time Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Using Vertical Zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Editing the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Chapter 4 - Debugging a Bus Contention . . . . . . . . . . . . . . . . 4-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

VirSim Tutorial i
Synopsys

Verifying Verilog Code Fixes from Risc 1 . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Tracing the Sources of an X Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Tracing the Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Chapter 5 - Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . 5-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Introducing the Interactive Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Checking Results of the Current Simulation . . . . . . . . . . . . . . . . . . . . . . 5-4
Editing the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Rebuilding and Re-executing the Simulation . . . . . . . . . . . . . . . . . . . . . . 5-9
Go To Next/Previous Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Chapter 6 - New Visibility Features . . . . . . . . . . . . . . . . . . . 6-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Viewing Contents of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Tracing a Memory Data Path using the Multiple Net Display . . . . . . . . . . . . . . 6-5
Viewing Annotated Source code in the Source Window . . . . . . . . . . . . . . . . 6-7
Viewing and Creating Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Chapter 7 - Managing Large Amounts of Data . . . . . . . . . . . . . 7-1

Preparing for this Lesson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Open and Close VCD+ Files During Simulation . . . . . . . . . . . . . . . . . . . . 7-2
Loading a Partial VCD+ File into VirSim . . . . . . . . . . . . . . . . . . . . . . . . 7-5

ii VirSim Tutorial
 Chapter 1
Introduction
In This Chapter VCS VirSim and VirSim ships
„ Tutorial Objectives with a tutorial directory with six
„ Introducing Virsim versions of a Verilog design to
„ Getting Started with VCS VirSim or VirSim help you become familiar with
VirSim features. The tutorial will
guide you through debugging
three errors in the example
design.

NOTE: In order to use this tutorial, the

following licenses are required:

Synopsys VCS or Synopsys VirSim

Synopsys VCS (for Chapter 5)

VirSim Tutorial 1-1

Synopsys

Tutorial Objectives
In the tutorial, you accomplish the following objectives:
„ Learn VirSim system tasks needed to collect signal data.
„ Learn to use six of the VirSim windows.
„ Become familiar with Virsim features.
„ Debug Verilog simulation results in post-simulation mode. Post-simulation mode
enables you to extract and analyze simulation data from VCD+ history files after
simulation has been completed.
„ Use a configuration file to quickly return to a window configuration of interest.
„ Trace the cause of the errors and correct them in the Verilog source code.
„ Run a Verilog simulation in Interactive Mode (VCS license required). Interactive
Mode enables you to extract and analyze simulation data during simulation.
„ View register memory contents, anotate source code signal values, and create
buses of signals.

Introducing Virsim
This section includes an overview of the VirSim windows and the command icons
used in the tutorial. The following topics are covered:
„ VirSim Windows
„ Tool Bar

VirSim Windows
VirSim contains graphic windows that present various views of your design. These
windows may be linked so that operations initiated in one view may affect other views.
All VirSim windows have a Window menu which can be used to open other VirSim
windows. The VirSim tutorial demonstrates the use of the following windows:

Hierarchy The Hierarchy Browser displays the hierarchy of scopes used by

Browser the simulation. Scopes can consist of modules, tasks, functions,
named forks, and named blocks. You use the Hierarchy Browser to
navigate the scope hierarchy, search for scopes and signals, select
scopes, display signals, and drag-and-drop scopes and signals to
other windows for analysis.

1-2 VirSim Tutorial

 Introduction

Waveform The Waveform Window displays groups of signal waveforms, cur-

Window sors, and markers. A time field shows the time range of signal
events for the simulation and correlating signal values at specific
points in time. You use the Waveform Window to view signal wave-
forms, view unique events, create and search on expressions, cre-
ate and view buses, and create and view user defined markers.
Delta Cycle lets you see signal change within a single simulation
time unit. Event origin takes you to the cause, or "origin," of a sig-
nal transaction. Context sensitive menus are used to trace the
source of event origins, expand simulation time into delta time,
select radix, set drawing mode, set waveform height, and add
blank lines.

Register The Register Window can display text and block diagrams of simu-
Window lation modules and signal events at specific times in the simulation.
You use the Register Window to view input and output values and
events at specific times. Values highlighted in pink indicate values
that have changed at that time.

Source The Source Window displays source code for selected instances.
Window In the tutorial, the Verilog source code contains several errors. You
use the Source Window to debug and correct these errors in post
simulation mode. Several features help you to isolate problems in
the code: Show Values annotates signal values in the source code,
breakpoints let you stop execution at specific lines, and single step
execution lets you execute one line at-a-time.

Logic The Logic Browser displays hierarchical schematics of net connec-

Browser tions between scopes. The net connectivity is extracted directly
from the source files. You use the Logic Browser to trace net con-
nectivity up and down the hierarchy by selecting module ports or
primitive terminals.

Interactive The Interactive Window provides an interactive control panel to

Window control the running of a simulator. This window can be linked in
time to other VirSim windows, providing complete debug with a live
simulator.

VirSim Tutorial 1-3

Synopsys

Tool Bar
Table 1-1, Command Icons, shows tool bar icons that are referenced in the tutorial
and the windows in which they are found. If you do not recognize the icon by its icon
name, refer to this table.

Table 1-1. Command Icons

Icon Icon Name VirSim Window

Marker Waveform Window, Register
Window

Search Expression Waveform Window

Zoom Cursors Waveform Window

Vertical Compress Waveform Window

Load Value Changes Source Window

Zoom Percent Waveform Window

Next Breakpoint Source Window

Window Link All windows except the Hier-

archy Browser

Previous/Next value Change Register Window, Logic

Browser

Step to Previous/Next Line Source Window

Continue Simulation Interactive Window

Select Root Hierarchy Window

1-4 VirSim Tutorial

 Introduction

Getting Started with VCS VirSim or VirSim

VirSim is a tool used to present Verilog simulation results to a designer. To present
these results using VirSim, the designer needs to instrument the Verilog source code
prior to running the simulation. The simulator then creates the VCD+ history file
containing design hierarchy, signal change data, and optional other simulation data.
All VirSim documentattion is on line in PDF format. To access the documentation from
the Main menu or any VirSim window, click "help." Acroread starts, and the VirSim
context Sensitive Help Menu is displayed.

Verilog Code Instrumentation and Simulation

In order to collect simulation data into a VCD+ history file, the $vcdpluson system task
must be applied to your design. More system tasks may be added to save additional
data of interest.
In this tutorial we have included the following system tasks:
Collect basic hierarchy and value change data

module instrument; Collect signal change data within each

Initial begin simulation time
$vcdpluson; Collect line trace data during a simulation.
$vcdplusdeltacycleon;
$vcdplustraceon;
Automatically detect and record that a glitch is
$vcdplusglitchon; present
$vcdplusevent(test.risc1.data[7:0],"Data Creates a Green Triangle user defined event at
is Unknown","IT"); time 0 which displays "Data is Unknown" when
vcdplusevent(test.risc1.data[7:0],"Data the cursor is pointed to it in an analysis window.
is Unconnected","ED");
$vcdplusmemorydump(memory,0,3);
Creates a Red Diamond user defined event at
$vcdplusmemorydump(memory,25); time 20 which displays "Data is Unconnected"
$vcdplusmemorydump(test.risc1.mem1.memory);
when the cursor is pointed to it in an analysis
window.
end
Dump 4 locations of register memory
Dump 1 location of register memory

Dump all locations of register memory

To handle these $vcdplus system tasks, the VirSim pli must be linked to the simulator.
In the tutorial, we used the following command line during VCS simulation:
vcs -line -R -I -f run_bad.f +simargs+"+vpdfile+vcs.vpd +vpddrivers
+vpdports"

The -I option is the option that links these tasks and enables interactive/
postprocessing debugging capabilities.
See the Installation Notes for information on linking the VirSim PLI to the Cadence
Verilog simulator.

VirSim Tutorial 1-5

Synopsys

The default VCD+ file name is vcdplus.vpd. We can override this by specifying a
VCD+ file to create.
On the VCS command line, we added:
+vpdfile+vcs.vpd -line +simargs+"+vpdfile+vcs.vpd \
+vpddrivers +vpdports"

In addition, VCS requires the -line option to save line execution data. The
+vpddrivers switch saves all net driver data, which helps resolve multiply driven nets.
The +vpdports switch saves port direction data for display in the Hierarchy Window.
On the Verilog-XL command line, we used:
verilog -f run_bad.f
+loadpli=$VIRSIMHOME/Solaris/vcdplus/vxl2_6/
virsim:virsim_bootstrap
+vpdfile+vxl.vpd +vpddrivers +vpdports

The +vpddrivers switch saves all net driver data, which helps resolve multiply driven
nets. The +vpdports switch saves port direction data for display in the Hierarchy
Window.
We completed these preliminary steps and ran simulations that created VCD+ history
files that will be read by VirSim.

Starting VCS VirSim or VirSim

The following lesson explains how to start VirSim from the command line. After VirSim
is installed, start VirSim with one of the virsim commands.
1. To access the risc design, go to one of the following directories:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc

2. To start the tutorial, do one of the following:

„ Enter the script file which contains the full VirSim command line:
run_risc
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP -f run_bad.f +vpdfile+vcs.vpd +vpdfile+vxl.vpd \
+cfgfile+delta1.cfg &

• For VirSim:
virsim -f run_bad.f +vpdfile+vcs.vpd +vpdfile+vxl.vpd \
+cfgfile+delta1.cfg &

Where:
-f filename.f Contains a list of .v files to compile
for use with the Source Window and

1-6 VirSim Tutorial

 Introduction

Logic Browser. It may also contain

other simulation arguments.
+vpdfile+vpdfilename.vpd Specifies which .vpd file to open. In
the tutorial we open the history files
for both VCS and Verilog-XL.
+cfgfile+cfgfilename.cfg Specifies which VirSim configuration
file to load at start up. VirSim has the
capability to save a window
configuration so that the user can
quickly return to a desired view of
the design. We use this feature in all
six parts of the tutorial to jump to
different points of the debug
process.
After entering this command, you will see two Hierarchy Browsers and two Waveform
Windows. The upper Hierarchy Browser is displaying the vcs.vpd file. The lower
Hierarchy Browser is displaying the vxl.vpd file. This is denoted in the Hierarchy
Browser title bar. See Figure 1-1, Two Hierarchy Browsers.

Figure 1-1. Two Hierarchy Browsers

You will also notice a V1 and V2 next to the vpd file name. These file designators
reference a single VCD+ file and are used by the configuration file. As shown here,

VirSim Tutorial 1-7

Synopsys

multiple VCD+ files and multiple VirSim windows can be open simultaneously for
viewing with a single VirSim license.
Both Hierarchy Browsers are displaying the same design; however, we descended to
the risc1 module in the vxl.vpd file and saved the display to show part of the
configuration capability.
More detail regarding Hierarchy Browser features is given in the risc1 section of the
tutorial.

1-8 VirSim Tutorial


Delta Cycle Debugging
In This Chapter
„ Preparing for this Lesson
„ Analyzing Data from Two Simulators
„ Viewing Delta Cycles, Glitches and User-
Defined Events
„ Determining Origins of Events
„ Editing Verilog Code
VirSim Tutorial
Chapter 2
In this lesson you will use the
knowledge based debug
capabilities of VirSim to analyze
data from two simulators.
Because the design has a race
condition bug, the two
simulators produce different
results. You will be guided to the
cause of the race condition and
directed to the source code file
where it can be fixed.
2-1
Synopsys

Preparing for this Lesson

Files for this lesson are located in the risc directory.
1. To the access the risc design go to the following directory:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc
2. Start the tutorial by doing one of the following:
„ Enter the script file which contains the full VirSim command line:
run_risc
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP -f run_bad.f +vpdfile+vcs.vpd +vpdfile+vxl.vpd \
+cfgfile+delta1.cfg &

• For VirSim:
virsim -f run_bad.f +vpdfile+vcs.vpd +vpdfile+vxl.vpd \
+cfgfile+delta1.cfg &

Analyzing Data from Two Simulators

1. To view the test risc1 signals in the risc design generated by the VCS simulator,
use your middle mouse button to drag and drop the test.risc1 module from the
upper Hierarchy Browser (V1) to the upper Waveform Window (WW1). Refer to
Figure 2-1, Dragging Signals from the Hierarchy Browser to the Waveform
Window.

NOTE: To drag-and-drop signals: With a three-button mouse, click and hold down the middle mouse
button on a signal or a selection and drag-and-drop it to the destination. With a two-button
mouse, first perform a selection, then click and hold down the left mouse on the item and drag-
and-drop it. (If you are using Exceed and a two button mouse, click the right and left mouse
buttons together to drag and drop.)

2-2 VirSim Tutorial

 Delta Cycle Debugging

Figure 2-1. Dragging Signals from the Hierarchy Browser to the Waveform Window

2. To view the test risc1 signals generated by the Verilog-XL simulator, drag and
drop (using your middle mouse button) the test.risc1 module from the lower Hier-
archy Browser (V2) to the lower Waveform Window (WW2).

VirSim Tutorial 2-3

Synopsys

Viewing Delta Cycles, Glitches and User-Defined Events

To clarify the differences between the VCS and Verilog-XL data:
1. In WW1, place your cursor over the yellow diamond at time 10 of the inc_pc sig-
nal. You will notice the "multiple value changes" description in the status bar
denoting a glitch. These glitch indicators appear because you added the $vcd-
plusglitchon system task to the design. See Figure 2-2, Multiple Value Changes.

Yellow diamond indicating a

glitch, along with "multiple
value changes" description in
the status bar.

Figure 2-2. Multiple Value Changes

2. Right click and hold your mouse button down on time 10 in WW1; then select
Expand Time from the context sensitive menu (CSM) to expand it into delta time.
This delta cycle information defines the sequence of signal changes within simula-
tion time 10. Repeat this in WW2. Figure 2-3, Expanding Time.

2-4 VirSim Tutorial

 Delta Cycle Debugging

Expanded time in
VCS simulation

Expanded time in
Verilog-XL simulation

Notice that the

glitch in inc_pc
shows up in the
VCS simulation but
not the Verilog-XL
simulation.

Figure 2-3. Expanding Time

You are able to view the delta time because the $vcdplusdeltacycleon call was
added to the design. For delta time, VirSim displays exactly what the simulators
report. With this design we see that the two simulators behave differently. This
delta time is non-determinate. The simulator reported multiple value changes in a
given simulation time, and Virsim assigns an incremental delta cycle value to each
change in the order it was received.
The $vcdplusevent call was also used in the design to create two user-defined
unique events. These can be placed anywhere in the code to help you quickly
locate a signal of interest.
always @(negedge test.risc1.clock
if(test.risc1.data==8’h00)
$vcdplusevent(test.risc1.data[7:0], "Data is unknown","IT");

always @(posedge test.risc1.fetch)

if(test.risc1.alu1.opcode==3’h6)
$vcdplusevent(test.risc.alu1.opcode, "Data is Unconnected","ED");

VirSim Tutorial 2-5

Synopsys

3. Data[7:0] shows two events indicated by a small green triangle at time 0 and a red
diamond at time 20. When you place your cursor over either indicator, a user
defined description appears in the status bar. Figure 2-4, Unconnected Data in
Status Bar.

When you place the cursor

over the red diamond, the
user defined message
"Data is Unconnected"
appears in the status bar.

Figure 2-4. Unconnected Data in Status Bar

Viewing the expanded inc_pc signal in the two Waveform Windows shows the
glitch in the VCS inc_pc signal within time 10. The Verilog-XL simulator shows
signal change from 0 to 1, i.e. no glitch.
4. In both Waveform Windows, right click within simulation time 10, hold down your
mouse button, and select Collapse Time from the CSM.

Determining Origins of Events

Debugging a design or a test bench generally starts with a number of signals
exhibiting less desirable values. Finding the cause of such problems has always been
a challenge. VirSim can make this process easier. Here’s how.
In this procedure we determine the Event Origin of the inc_pc signal glitch and the
sequence of statement execution for the event.
1. In WW1 right click the signal inc_pc at time 10, hold down your mouse, and select
Event Origin>Automatically Select Window from the CSM.
Since there is more than one driver on the inc_pc signal, the Multiple Drivers
Dialog appears. The Bit Pane shows the inc_pc signal. If you did Event Origin on
a vector with multiple drivers, you would see each changed bit in the Bit Pane.
The drivers are in module decoder instance test.risc1.instdec. See Figure 2-5,
Multiple Drivers Dialog.

2-6 VirSim Tutorial

 Delta Cycle Debugging

Figure 2-5. Multiple Drivers Dialog

2. In the Multiple Drivers Dialog, double click on the second test.risc1.instdec

instance.
A Source Window opens with the decoder.v file, and you see a large arrow point-
ing to line 22, where @posedge fetch, inc_pc=1. See Figure 2-6, Source Win-
dow.

Figure 2-6. Source Window

VirSim Tutorial 2-7

Synopsys

3. Double click on the first instance listed. The Source Window jumps to line 58
where @posedge fetch, inc_pc=0. Both lines executed at time 10. This is the
cause of the glitch. See Figure 2-7, Jump to Second Instance.
.

Figure 2-7. Jump to Second Instance

Editing Verilog Code

To resolve the race condition located in Determining Origins of Events, one of the
"always" statements needs to be changed. Knowledge of the design indicates that the
inc_pc signal should be a one at the end of time 10, so line 19 in the decoder.v file
should be changed to "always @(negedge fetch)." We can do this from the Source
Window via the Edit->Edit Source. We would then resimulate, create new VCD+ files
and reopen the VCD+ files. We have done this for you.
To view the results of this change, close VirSim and reinvoke it by doing one of the
following:
„ Enter the script file which contains the full VirSim command line:
run_risc_good
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP +vpdfile+vcs_good.vpd +vpdfile+vxl_good.vpd
+cfgfile+delta2.cfg -f run_good.f &

• For VirSim:
virsim +vpdfile+vcs_good.vpd +vpdfile+vxl_good.vpd
+cfgfile+delta2.cfg -f run_good.f &

2-8 VirSim Tutorial

 Chapter 3
Debugging Functional Designs
In This Chapter In this lesson you will learn how
„ Preparing for this Lesson to use VCS VirSim and VirSim to
„ Using the Hierarchy Browser Search debug incorrect execution of
Features
one of the Risc ALU
„ Searching for and Marking a Value of instructions.
Interest
„ Stepping Value Changes on Signals of
Interest
„ Tracing a Signal Connection
„ Debugging with the Source Code
„ Testing a Code Fix with Expressions
„ Zooming the Time Range
„ Editing the Source Code

VirSim Tutorial 3-1

Synopsys

Preparing for this Lesson

You performed the lessons in the previous chapter in the risc directory. Files for this
lesson are located in the risc1 directory.
1. To access the risc1 directory go to the following directory:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc1
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc1
2. Start the tutorial by doing one of the following:
„ Enter the script file which contains the VirSim command line:
run_risc1
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP +vpdfile+risc1.vpd +cfgfile+risc1.cfg -f run.f
• For VirSim:
virsim -f run.f vpdfile+risc1.vpd +cfgfile+risc1.cfg

The following VirSim windows appear:

„ Hierarchy Browser
„ Waveform Window
„ Register Window
„ Source Window
With all windows open at once, some windows might overlay other windows.
The Register Window, named "VirSim - Register - A - Autoview0", displays the
ALU data flow for the RISC processor.
3. Click left on the Register Window to bring it forward. See Figure 3-1, Register
Window.

3-2 VirSim Tutorial

 Debugging Functional Designs

Notice that the ALU performs

operations on the inputs
data[7:0] and accum[7:0].
The opcode determines the
operation. We will find the XOR
behavior to be incorrect.

At the bottom of the Register Win-

dow we prepared a view to debug
this operation using the Register
Window graphics utilities. The
accum ^ data expression shows
the ALU input and the resultant
output values.

Figure 3-1. Register Window

In the following procedures, you view and debug events associated with the XOR
operation.

Using the Hierarchy Browser Search Features

This procedure uses the Hierarchy Browser to select the ALU scope and copy its
signals to the Waveform Window.
1. Click on the Hierarchy Browser, named "VirSim - Hierarchy - V1- risc1.vpd", to
bring it forward.
The Hierarchy Browser initially displays in "Tree View" format when using the
default ~/.virsimrc file. Select Display>Block View if the Hierarchy Browser is not
displayed in "Block View" format.
Note that in Block View, the scopes are color-coded with gray modules, green
functions, and blue tasks. This pane contain a root scope icon called test, along
with its subscopes. See Figure 3-2, Block View of Hierarchy.

VirSim Tutorial 3-3

Synopsys

Figure 3-2. Block View of Hierarchy

2. Select Display>Outline View to display the design in a hierarchy tree format.

Browse down the hierarchy tree by clicking the + or - icons. See Figure 3-3, Hier-
archy Browser.

Click icons to browse

hierarchy tree.

Figure 3-3. Hierarchy Browser

3-4 VirSim Tutorial

 Debugging Functional Designs

3. Return to Block View by clicking Display>Block View.

4. Use the arrows to move up and down the hierarchy without displaying associated
signals. (You may have thousands of signals in which you have no interest.). See
Figure 3-4, Moving Through Block View.

Click left on the down

arrow in risc1 to descend
the hierarchy without dis-
playing its associated sig-
nals.

You can create Bookmarks to quickly

return to a specific module in the Hier-
archy: Highlight the alu1 module, then
press and hold down the right mouse
button, and select Create Bookmark
from the CSM. You can return to the
alu1 module by clicking the Root Icon
and selecting test.risc1.alu1.

Click left on the up arrow

in test.risc1 to get to the
top again.

Figure 3-4. Moving Through Block View

VirSim Tutorial 3-5

Synopsys

5. Click on the test1.risc1 box to display all the signals associated with risc1 in the
right pane. See Figure 3-5, Displaying Signals.

Click on test.risc1 box to display signals

Scroll to view all signals

Figure 3-5. Displaying Signals

3-6 VirSim Tutorial

 Debugging Functional Designs

6. Enter *es* in the Filter text entry box, and click Filter to select all signals with "es"
in their name. Three signals are displayed. See Figure 3-6, Filtering Signal
Names.

Vector
Scaler
Port

Figure 3-6. Filtering Signal Names

7. Click the + box in front of the vector, address [4:0], to expand this vector to individ-
ual bits. See

Figure 3-7. Expanding a vector

8. Click the - box in front of the vector address [4:0] to collapse this vector.
9. Enter * in the Filter text entry box and click Filter to select all signals in risc1.
10. Use the Search function to locate the scopes of interest: See Figure 3-8, Search-
ing Scopes.

VirSim Tutorial 3-7

Synopsys

A) Click the Search

tab, then enter *es*
in the Search text
entry box.

B) Click the Search

button to find all
scopes below the
Selected scope,
risc1, with "es" in
their name.

One scope, reseter,

is displayed.

Click the Selected menu

and select All; then click
Search to find all scopes
with "es" in their name.

Three scopes — test,

reset_cpu, and reseter —
are displayed.

Figure 3-8. Searching Scopes

11. Use the Search function to locate signals of interest. See Figure 3-9, Searching
Signals and Scopes.

3-8 VirSim Tutorial

 Debugging Functional Designs

Make sure *es* is entered

in the text field, click
Signals, then click Search.
Seven signals with "es" in
their name are displayed.

Enter * in the Search text

entry box, and click
Search. All signals in the
design will be displayed.
Scroll the Search pane to
see all signals.

Click Scopes and click

Search. All modules in the
design will be displayed.
Scroll the Search pane to
see all modules.

Figure 3-9. Searching Signals and Scopes

VirSim Tutorial 3-9

Synopsys

12. Use a bookmark to view signals for a specific module as described below in Fig-
ure 3-10, Using Bookmarks.

To use a bookmark,
click the Root button in
the toolbar.

Select test.risc1.alu1 in
the CSM.

Click the Signals tab

and make sure a wild-
card (*) is entered in
the Filter text field.

Note that all signals in

the alu1 module are
displayed in the Signal
pane.

Figure 3-10. Using Bookmarks

13. In the Signals pane, hold down the Ctrl key and click left on signals in the follow-
ing order: clock, opcode[2:0], accum[7:0], data [7:0], alu_out[7:0]. Note that
holding down the Ctrl key enables you to select multiple signals.
14. Drag-and-drop the signals you selected as a group to the Waveform Window.
Note that the Signal Name, Signal Value, and Waveform panes are legal drop
sites.
The signals appear in the Waveform Window in the order you selected them. See
Figure 3-11, Dragging and Dropping Signals into Waveform Window.

3-10 VirSim Tutorial

 Debugging Functional Designs

Figure 3-11. Dragging and Dropping Signals into Waveform Window

Searching for and Marking a Value of Interest

In this procedure, you use the Waveform Window to:
„ Search signals for a specific event in simulation history.
„ Place a marker at this event.
You execute the previously defined search expression xor_trigger to locate the
specific time at which the exclusive or (XOR) operation starts execution. We later will
define our own expressions. When you search for the xor_trigger condition, the C1
cursor moves to 690, the start time for the XOR operation. The Signal Name and
Signal Value panes display the signal names and values for the ALU signals at that
time.
After you locate the event, you then place a marker at 690. The marker returns the
cursor to the event when you click on the Marker icon and choose a marker.
1. In the Waveform Window, click left on the Zoom Percent icon to display zoom
percents for the waveform time field.

VirSim Tutorial 3-11

Synopsys

2. Click left on 50%.

3. Click left on the forward Search Expression icon to find the first XOR event.
The C1 cursor moves to 690.
4. Set the marker:

a. Click left on Edit.

b. Choose Markers. The Markers Dialog opens.
c. Enter mk1 in the Name field. The Time field displays event time 690.
d. Click left on Add to save the marker. The marker name mk1 appears in the
Markers pane.
e. Click left on Done to close the Markers Dialog.
5. To see how the marker works:
a. Move the C1 cursor to anywhere to the left of 690. Click left in the time scale.
b. Click left on the Marker icon to select the marker.
c. Click left on mk1.
The C1 cursor moves to the marker at 690.

Stepping Value Changes on Signals of Interest

In this procedure you use the Register Window and Source Window to debug an error
in the ALU output. The ALU does not produce the correct output for the XOR
operation. The ALU should perform an XOR operation on the data and accum input
signals to produce exclusive or output.
In the Register Window, you view four time-based events performed by the XOR
operation. The Register Window documents the operations that the ALU should
perform for each event. Variables for the expression
alu_out = accum ^ data
show the actual inputs and output produced for each event. The XOR operation
begins at time 690. The data value becomes high impedance (8’hzz) at time 700. A
new data value (8’h90) arrives at time 710. The ALU performs the XOR operation on
inputs data (value 8’h90) and accum (value 8’h01) at time 720.
1. Click left on the Register Window to bring it forward.
The opcode has a value of XOR highlighted in pink. The pink highlighting
indicates the start of the XOR operation.
2. Click left on the Next Change icon to view each of the four time-based events (at
times 690, 700, 710, and 720).
Each time you press the Next Change icon, the time increments by 10. The
Register expression variables display the ALU input and output values at that
time. In the Waveform Window, the C1 cursor also advances by 10 because the
windows are linked (as indicated by the link letter next to the Link Icon).
Notice at time 720 the ALU output value 8’h00 is incorrect. The XOR of input
value 8’h90 and 8’h01 should equal 8’h91, not 8’h00. You can use the Signal
Properties context sensitive menu to view signal values in different notations:
binary, hexadecimal, etc.

3-12 VirSim Tutorial

 Debugging Functional Designs

To change the value notation:

1. Click right on the signal to open the Signal Properties menu.
2. Choose Radix and then the signal notation.
The signal value changes to the notation you select.
3. Click left on the Previous Change icon to backup in time.

Tracing a Signal Connection

In the Waveform Window and Logic Browser, you trace the opcode to determine if
XOR is the correct operation. The opcode determines which operation is performed
by the ALU.

NOTE: In the Logic Browser, click left on a port symbol to move up in the hierarchy and on the inside
of a port instance symbol to move down in the hierarchy.

1. In the Register Window, click left on the Next Change icon to view the XOR oper-
ation at time 720.
2. Click left on Windows in the menu bar and choose Waveform.
A second Waveform Window opens.
3. In the Hierarchy Browser, if necessary click left on the up arrow to scroll up the
hierarchy to test.risc1.
4. Drag-and-drop the test.risc1 scope to the second Waveform Window.
All the signals associated with test.risc1 appear in the Waveform Window in
alphabetical order.
5. In the second Waveform Window menu bar, click left on Window and choose
Logic.
The Logic Browser opens.
6. Drag-and-drop the clock signal from the second Waveform Window to the Logic
Browser.
The clock net appears.
7. Scroll the Logic Browser up to display the alu1 scope.
The clock signal feeds into the lower-left port.
8. Click right on the ireghi[8:6] port to open the Port Instance menu.
9. Hold down the right mouse button and choose View Connection.
The Connections Dialog opens. The Connections Dialog displays how signals
are connected between the definition and the instantiation of the port. Notice that
the input register bits 8-6 equal the hexadecimal value 4.
10. Click left on Cancel to close the Connections Dialog.
11. In the second Waveform Window, click left on the Marker icon and then on mk1.
The C1 cursor moves to time 690.
12. Scroll the Waveform Window down until you see the ireghi[8:5] waveform.
13. Double-click left on ireghi[8:5] in the Signal Name pane to expand the vector. The
three bits used as opcode are at 4, i.e. XOR. Thus opcode is not at fault.

VirSim Tutorial 3-13

Synopsys

Debugging with the Source Code

In the Source Window, you debug the cause of the error in ALU output. You find the
statement in the source code responsible for the error and correct it.
You have determined that XOR is the correct opcode value but ALU does not
produce the correct output value. You now use the Source Window to determine if the
error is in the Verilog source code. The alu_out statement in the source code should
be the same as the XOR operation documented in the Register Window.
1. In the second Waveform Window, click left on the small Z icon to zoom out three
times. Then click left on the transition of the alu_out signal at time 720 to set the
C1 cursor to time 720.
2. Drag-and-drop the alu_out signal in the Waveform Window into the Logic
Browser.
3. Close the second Waveform Window. Select Close Window from the File menu.
4. In the Logic Browser, click left on the inside of port alu_out on the alu1 instance
to descend into alu1.
The Logic Browser displays the alu_out net. The drivers on the left are assign
statements from a behavioral module.
5. Drag-and-drop one of the assign statement blocks into the already opened
Source Window. It is the alu module.
6. In the Source Window, click the Forward Icon to step forward to line 23.
7. Compare the alu_out statement on line 23 in the Source Window with the XOR
operation in the Register Window.
Notice that alu_out is defined as accum ^ data in the Register Window and as
accum & data in the Source Window. Since you determined that XOR is the
correct operation (when you debugged the opcode), you can now see that the
AND function in the source statement is incorrect.
8. In the Source Window, point at any signal to see its value at the current time as a
tooltip. A tooltip value of "NA" means that the signal is not available as it was not
saved in the database. A value of "NL" means that the signal data is not yet
loaded into memory. Click the Load Signal Values icon to load data for all signals
in this instance.
Point the cursor at the three signals on line 23 (alu_out, accum, and data). The
values 8'h00, 8'h01, and 8'h90 are displayed.
9. You can select a bunch of Verilog code in the SW and drag it to other analysis win-
dows. VirSim extracts all signals (even from comments!), putting them in the order
they appeared in the text, removing duplicates. To view this capability:
a. In the Source Window, select Window->Register to open a new Register
Window, RW2.
b. Highlight and drag line 17 through line 23 of the alu1 module from the Source
Window to RW2 and see the values of all the selected signals at once.
10. In the Source Window, click left on the green bullet at line 23 to set a breakpoint
at that line.
The green bullet is replaced by a red breakpoint mark.

3-14 VirSim Tutorial

 Debugging Functional Designs

Testing a Code Fix with Expressions

In order to correct the ALU output, you must change the AND function in the source
code to an XOR function. But first, you need to verify the correction. To verify the
correction, you create two expressions in the Waveform Window, one called bug for
the AND function and one called fix for the XOR function.
1. Create an expression called bug:
a. In the Waveform Window, click left on Edit.
b. Choose Expressions. The Expressions Dialog opens.
c. Enter bug in the Name field.
d. In the Source Window, find the scope path test.risc1.alu1 and drag-
and-drop it into the Scope field in the Expressions Dialog.
e. In the Source Window, highlight the expression accum & data on line 23 and
drag-and-drop it into the Expression field in the Expressions Dialog. (To high-
light text, hold down the left mouse button and drag the cursor across the
text.)
f. Click left on Add.
2. Create a second expression called fix:
a. In the Expressions Dialog, click left on bug. The scope and expression you
defined for bug appear in the Scope field and Expression pane.
b. In the Name field, replace bug with fix.
c. In the expression pane, replace the & with a ^ to change the expression
accum & data to accum ^ data.
d. Click left on Add.
3. Drag-and-drop bug from the Expressions Dialog to the Waveform Window.
4. Drag-and-drop fix from the Expressions Dialog to the Waveform Window.
5. In the Waveform Window, compare the waveform values for bug and fix.
6. Notice that fix displays the correct value 8’h91

Zooming the Time Range

You can zoom waveform time to a set time range.
1. Click left in the time field to set cursor C1 at approximately 680.
2. Click middle (or both on a 2-button mouse) to set cursor C2 at approximately 750.
3. Click left on the Zoom Cursors icon to zoom the signals in the time range from
C1 to C2. You also can click right in the timscale area to Zoom Cursors.
You can also use drag-zoom to zoom the time range:
1. Click left on the Z% icon and select 100%.
2. Press and hold down the left mouse button at a time in the Waveform Window or
Time Window, then slide the mouse right or left. Two vertical lines will appear.
Release the mouse button to zoom.

VirSim Tutorial 3-15

Synopsys

Using Vertical Zoom

There are signals that are not visible at the bottom of the Wave Window. Use the
Vertical Compress Icon to switch back and forth between the normal mode and a
compressed mode so you can maximize the number of signals you see at once. If you
normally see 15 signals, the compressed mode will fit 24 signals, and the names are
still readable! The height is configurable in the resource file for even smaller
waveforms.

Editing the Source Code

The following steps demonstrate how to find and edit the source code in a text editor.
If you were going to edit the source code, you would change the code in the text editor
and save it.

NOTE: If you intend to reuse the tutorial, you should not make actual corrections. Just note how it can
be done.

NOTE: The editor used is defined by the EDITOR environment variable in X Resources.

1. In the Source Window, click left on Edit.

2. Click left on Edit Source.
This command opens a text editor and displays the source code in the text editor.
3. Close the text editor.

3-16 VirSim Tutorial


Debugging a Bus Contention
In This Chapter
„ Preparing for this Lesson
„ Verifying Verilog Code Fixes from Risc 1
„ Tracing the Sources of an X Value
„ Tracing the Signal Source
VirSim Tutorial
Chapter 4
In this lesson you debug two
modules that simultaneously
drive values on the alu_out net.
The simulator resolves the two
signal values as an unknown
signal value 8’h0X. VirSim
allows you to locate the drivers
and the Verilog source code
responsible for the unknown
signal value.
4-1
Synopsys

Preparing for this Lesson

You performed the lessons in the previous chapter in the risc1 directory. Files for this
lesson are located in the risc2 directory.
1. If you are running VirSim in the risc1 directory, exit VirSim. To exit, choose Exit
from the File menu on any VirSim window.
2. When the save prompt appears, select No.
3. To access the risc2 directory go to the following directory:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc2
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc2
4. Start the tutorial by doing one of the following:
„ Enter the script file which contains the VirSim command line:
run_risc2
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP +vpdfile+risc2.vpd +cfgfile+risc2.cfg -f run.f
• For VirSim:
virsim -f run.f vpdfile+risc1.vpd +cfgfile+risc2.cfg

Verifying Verilog Code Fixes from Risc 1

Before you view the ALU net, verify that the XOR operation produces the correct
output.
1. In the Source Window, click left on the Next Breakpoint icon.
The simulation time 690 is displayed (the time for the expression xor_trigger).
2. Click left on the Next Breakpoint icon again to reach the breakpoint on line 23.
The statement displays the changes you made to accum ^ data.
3. In the Register Window, notice that the XOR expression for alu_out now pro-
duces the correct output value 8’h91 at 720.
4. In the Waveform Window, notice that the waveform value for alu_out also displays
the correct output value 8’h91 at 720.

Tracing the Sources of an X Value

Now check the output of the alu_out net to determine if the net is functioning correctly
for all simulation time. If the net functions correctly, the output signal should have a
valid hex value. An X in the signal indicates that the signal value is unknown.
1. Ensure that the zoom in the Waveform Window is at 100% by clicking the Zoom
Percent icon (Z%) and selecting 100%. At the right end of the display you will see
red waveforms indicating undefined values.
2. Double click left (quickly) on alu_out[7:0] in the Signal Name Pane to expand the
vector.

4-2 VirSim Tutorial

 Debugging a Bus Contention

3. Hold down the right mouse button at the time 2000 transition of alu_out[2] and
choose Event Origin>Automatically Select Window.
The Multiple Drivers Dialog opens showing alu_out[2] driven by eight inputs.
To open a Source Window and load the source code for ALU, select the first
alu_out[2] signal listed.
In the Source Window, the case statement is controlled by the signal opcode[2:0].
In the Waveform Window, click left on the alu_out[2] signal at time 2000 to set the
C1 cursor at time 2000.
In the Value Pane, the opcode[2:0] signal is reported as "LOAD". Right on this
"LOAD" value, and select Hexadecimal to see the value 8'h5 reported.
In the Source Window the opcode[2:0] value of five causes statement 24 to
execute.
The expression alu_out = data assigns the input value data to alu_out. Point to
the data and alu_out signals. A tool tip shows that the data and alu_out values
equal 8’h0X.
4. Drag-and-drop the data signal from the Source Window to the Logic Browser.
5. If necessary, click the Logic Browser window to bring it forward, then click left on
the data input port to move up to the next level in the hierarchy. Scroll vertically to
the top of the Logic Browser window.
Notice that the tricon port has a value of 8’h05 and the net wire[7:0] data has a
value of 8’h0X.
Notice that the module mem1 has an input/output port connected to the same net
as tricon and that the hierarchical resolution of the mem1 port is 8’h03. The value
X indicates that both the tricon and mem1 modules are driving on the same net
at the same time, creating a signal error of an unknown value.

Tracing the Signal Source

In the following steps, you trace the source of the unknown output signal in mem1 and
tricon to determine which module is at fault.
1. Trace the source of the wire [7:0] data from mem1.
On mem1, click left on the inside half of the data port to move down a level.
2. Trace the source of the wire [7:0] data signal from tribuf.
On tribuf, click left on the inside half of the data port to move down to the next
level of the net. At this level, there are eight drivers (VBUFIF) generating the
mem1 signal. Click left on the inside half of the data[1] port on the g1 module to
see the assign statement that feeds the out port. Click left on the out port to move
up one level. Note the values for each driver.
3. Click the I/O port data [7:0] to move back up the hierarchy one level. Click the I/O
port data [7:0] again to return to the data [7:0] net in the Logic Browser.
4. Trace the source of the tricon signal:
a. In tricon, click left on the inside half of the data port to move down a level.
b. Note that the 8’h05 signal comes from the makex module.
5. Compare signal values from the tricon and mem1 modules, as shown in the fol-
lowing table. The cause of the unknown signal should become apparent.

VirSim Tutorial 4-3

Synopsys

7 6 5 4 3 2 1 0

tricon 8’h05 0 0 0 0 0 1 0 1

mem1 8’h03 0 0 0 0 0 0 1 1

Result 8’h0x 0 0 0 0 0 x x 1

The X result for bits 1 and 2 indicate that tricon and mem are generating opposite
values at the same time.
The Logic Browser handles assignments as well as structural elements and dis-
plays significant information. Use the Logic Browser to navigate and debug struc-
tural design, continuous and register assignments.
6. In makex, click left on the inside half of the o port to move down a level.
The purple boxes representing the behavioral model appears.
Above the middle box an assigned statement is displayed: #2000,0=8’h5. This is
the cause of the 8"h5 value being driven on to the net.
7. Drag-and-drop the middle purple box to the Source Window.
8. In the Source Window, observe statement lines 19 and 20.
Notice that line 19 executes at time 2000. Line 20 drives the 8’h05 signal at the
tricon port. These two lines cause the signal value conflict between tricon and
mem1 at time 2000.
Removing line 19 and line 20 would correct the problem. However, if you intend to
reuse the tutorial, you should not make actual corrections. Just note how it can be
done.

4-4 VirSim Tutorial


In This Chapter
„ Preparing for this Lesson
„ Introducing the Interactive Window
„ Checking Results of the Current
Simulation
„ Editing the Source Code
„ Rebuilding and Re-executing the
Simulation
VirSim Tutorial
Chapter 5
Interactive Mode
In this lesson you will run the
VCS simulator in Interactive
Mode. To do so you need write
access, so you must copy the
example directory into your
work area. The VirSim
Interactive Window is used to
run a current simulation and
compare results to a VPD file
from a previous simulation. You
then edit source code and
rebuild and re-execute the
simulation to verify a source
code fix.
A VCS Simulator license must
be installed and active to run
this lesson.
5-1
Synopsys

Preparing for this Lesson

You performed the "Debugging a Bus Contention" lesson in the risc2 directory. Files
for this lesson are located in the risc3 directory.
1. If you are running in the risc2 directory, exit VirSim. To exit, choose Exit from the
File menu on any VirSim window.
2. When the save prompt appears, select No.
3. To access the risc3 directory and have write permission, create a directory,
your_risc_dir, in a writable area of the disk. Then, copy the system risc3 directory
to your your_risc_dir.
Example:
cp -r $VCS_HOME/virsimdir/examples/tutorial/verilog/
risc3 your_risc_dir

Then:
cd your_risc_dir/risc3

At the prompt, run the script file which contains theVCS compile and VCS/VirSim
command lines:
run_risc3
The Interactive, Hierarchy, and two Waveform Windows open.

Introducing the Interactive Window

The Interactive Window provides an interactive control panel for the simulator.
Included are start/stop buttons, a simulator output message transcript area, a
simulator command line interface, user programmable buttons (including step time,
show drivers, show scopes, break @posedge, radix formatting) and real time status
(drivers, current scope, simulation time and status).
The unique feature of this window is that you can link it (using the SIM link) to the
other windows in the VirSim debug environment so that any VirSim window can
control the simulator and display output results.
Output results can be traced backward in any design without having to save a history
file since simulation results are buffered.

5-2 VirSim Tutorial

 Interactive Mode

Window Link for the Inter-

active Window is always
linked to SIM, the active
simulator. When linked to
SIM you can not move back
in time in the window.
History Pane displays
simulator history and sta-
tus. In this lesson VCS
has been started and
should be active and
stopped at time zero. If so,
the last message dis-
played is $stop at time 0

Command Pane is
used for simulator
input commands.

User Defined
Buttons Pane is
used to control the
simulator.

Simulator
Control Pane
includes switches to
control the simulator.

Figure 5-1. Interactive Window

VirSim Tutorial 5-3

Synopsys

Checking Results of the Current Simulation

1. Compare the signals in Wave1 and Wave2.

In the first Wave-

form Window
(Wave1), the Label
Pane has "I1" in it
indicating that these
are signals from the
Interactive Simula-
tion. All signal data
is gray implying no
simulation data is
available.

In the second
Waveform Window
(Wave 2), part of the
signals are from the
Interactive Simula-
tion (I1) and the rest
are from a vpd file
(V1) which has data
from a previous sim-
ulation (risc2).

Figure 5-2. Comapring Waveforms

2. In Wave2, view (V1)alu_out at time 20,000 picoseconds. Notice that the value is
8'h0X — same as in the previous lesson.
3. In the Interactive Window, run the simulation by clicking the Green Arrow icon until
the simulator stops at time 20,800 picoseconds , as displayed at the bottom of the
Interactive Window.

5-4 VirSim Tutorial

 Interactive Mode

4. In Wave2, view the interactive alu_out (I1) waveform. It has the same result at
time 20,000 picoseconds .
5. In Wave2, right click on the (I1)alu_out signal at time 20,000 picoseconds and select
Event Origin->Automatically Select Window from the context sensitive menu.

Figure 5-3. Event Origin

6. The Multiple Drivers Dialog opens because of the multiple drivers on this net. See
Figure 5-4, Multiple Drivers Dialog.

Figure 5-4. Multiple Drivers Dialog

VirSim Tutorial 5-5

Synopsys

7. In the Multiple Drivers Dialog, all possible drivers to alu-out are listed. This is
because trace data is captured only for source code in the Source Window, thus
none has been captured, so all drivers are listed.
8. Double click the first entry alu_out[1] to cause the Source Window to open with a
hollow arrow pointing to line 26. The statement on this line is executed within the
case statement, which is controlled by the signal opcode.

Figure 5-5. Source Window

9. From the previous lesson, we know that data is the signal causing the 8’h0X. Ver-
ify this by pointing the cursor to data on one of the lines. The tool tip displays
8’h0X.

Figure 5-6. Tool Tip Display

5-6 VirSim Tutorial

 Interactive Mode

10. Still pointing to data, right click and select Event Origin>Point To Preferred Win-
dow from the context sensitive menu, then left click on data. The Multiple Drivers
Dialog is refreshed because of the multiple drivers on this net.

Figure 5-7. Refresh of Multiple Drivers Dialog

11. Double click the second entry, data[1], in the Multiple Drivers dialog.
The tricon.v module is displayed in the open Source Window.
12. In the Interactive Window, select Sim>Re-Exec to restart the simulation and trace
statement execution for the alu.v and tricon.v module.
13. In the Interactive Window Simulator Control pane, enter a step time of 19900,
then click OK to run the simulation to time 19900.

VirSim Tutorial 5-7

Synopsys

14. Link the Source Window to SIM, then click the Next Line icon. The solid arrow
indicates line 20 executed setting 0 to the 8’h05 that caused the Multiple Drivers
at time 20000. See Figure 5-8, Locating the Cause of Multiple Drivers.

Link the Source

Window to SIM
by clicking the
Link button on
the toolbar.

Click the Next

Line button.

Solid arrow indicates

cause of multiple drivers

Figure 5-8. Locating the Cause of Multiple Drivers

15. Click the Next Line icon nine more times to trace statement execution through the
source code. Notice that the 8’h0X is displayed in the Wave2 alu_out(I1) wave-
form.

5-8 VirSim Tutorial

 Interactive Mode

Editing the Source Code

1. Pop the Source Window to the front.
2. Left click the Select Instance icon and pick test.risc1.tricon.mx.
3. Click Edit->Edit Source. The editor of your choice opens with the tricon.v file.
4. Add double "/" in front of line 20 "o = 8'h05;", save, and close the file.

Rebuilding and Re-executing the Simulation

1. In the Interactive Window, click Sim->Rebuild and Re-exec. VCS will recompile
then restart the simulator.
2. Run the simulation by clicking the Green Arrow icon in the interactive window until
the simulator stops at t7,040 (t70400 according to the History Pane).
3. In Wave2, view the signal alu_out(I1) compared to the ali_out](V1). The Unknown
result seen above is now replaced with a value of 03.
4. In the Source Window, click the forward yellow arrow icon to move forward in time
enough times to see the simulator advance from t70,400 to t71,200.
5. In Wave2, C1 is at time zero. Clicking the Link icon and selecting SIM links Wave2
to the active simulation and adds the Icur cursor set to time 7,120.
6. In the Interactive Window, click Sim->Re-exec. VCS will restart the simulator.
7. In the Interactive Window, enter a Step time of 1,000. Then click OK. The simula-
tor will advance to time 1000, and the Wave Window C1 cursor will follow.

Go To Next/Previous Change
1. In the Waveform Window, select the alu_out (I1) signal by clicking the left mouse
button over the signal in the signal name pane.
2. Use shortcut key “N” to locate the next change on the selected signal. Notice that
the Interactive simulation is advanced.
3. if you are not linked to SIM, you can use “P” to locate the previous change.

VirSim Tutorial 5-9

Synopsys

5-10 VirSim Tutorial


New Visibility Features
In This Chapter
„ Preparing for this Lesson
„ Viewing Contents of Memory
„ Tracing a Memory Data Path using the
Multiple Net Display
„ Viewing Annotated Source code in the
Source Window
„ Viewing and Creating Buses
VirSim Tutorial
Chapter 6
Using VirSim, you can view
register memory contents along
with Signal data. To capture
memory data, add a
$vcdplusmemorydump; task call
to the source code where and
when a strobe is desired, then
simulate.VirSim will then dump
the specified contents of
register memory every time the
task is called. VirSim can dump
a range of register memory, a
specific location of register
memory, or all of register
memory.
6-1
Synopsys

Preparing for this Lesson

You should have already performed Lesson 5 in the risc3 directory. Files for your next
lesson are located in the risc4 directory.
1. If you are running VirSim in the risc3 directory, exit VirSim. To exit, choose Exit
from the File menu on any VirSim window.
2. When the save prompt appears, select No.
3. To access the risc4 directory, go to the following directory:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc4
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc4
4. Start the tutorial by doing one of the following:
„ Enter the script file which contains the VirSim command line:
run_risc4
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP +vpdfile+risc4.vpd +cfgfile+risc4.cfg -f run.f
• For VirSim:
virsim +vpdfile+risc4.vpd +cfgfile+risc4.cfg -f run.f

Viewing Contents of Memory

1. View the source code (module mem) in the lower left Source Window. A 32-word
register memory is declared in the source code statement line 35.
2. View the source code (module I1) in the upper left Source Window, and note the
Verilog Source file comments on line 15, 22, and 26 that document the register
memory dumped by VirSim.
3. The Waveform Window is displaying a portion of the 32 word register memory
declared in the mem module.
reg [7:0] memory [0:8'h1f];
4. Figure 6-1, Contents of Memory, shows the initial appearance of the Waveform
Window.
The partial register memory display is a result of displaying all of memory[0:31],
then expanding memory[0:31] into 32 separate words of memory, memory[31]
through memory[0], and deleting unwanted words.

6-2 VirSim Tutorial

 New Visibility Features

A blank line in the

Waveform Window.

Seven signals from the

risc4 design.

Location 25 of register
memory dumped at
time 250.

Locations 0 to 3 of reg-
ister memory dumped
at time 30, 1st "read."

All of register memory

dumped at time 330,
490, 650, etc., every
"write."

Figure 6-1. Contents of Memory

VirSim Tutorial 6-3

Synopsys

5. Enlarge the Waveform Window by Dragging and Dropping the upper left corner of
the Waveform Window to fill most of your screen.
6. Quickly double click on memory[0:31] to collapse it.
7. Quickly double click on memory[0:31] to expand it.
8. Quickly double click memory[0] to expand it into individual bits.
9. View the bits of memory[0][7] through memory[0][0].
10. Quickly double click on memory[0][7:0] to collapse it.
11. Select memory[14] through memory[24] in the Signals pane. Then select
Edit>Delete to delete these unused memory words.
Now evaluate memory data respective to the signal data.
12. Point to the memory[0] signal value (8'he3) in the Signal Value Pane, and press
the right mouse key to bring up the Radix popup menu, then select Binary. The
upper 3 bits are displayed as "111" at time 30.

Figure 6-2. Viewing Binary Bit Data

6-4 VirSim Tutorial

 New Visibility Features

13. Look at the signal addr[4:0] in the Wave Window to see value 5'h00. This selects
the contents of address zero to be read to the data[7:0] signal, and on to become
the three bit opcode "111".
14. Point to the opcode[2:0] signal value "HALT" in the Signal Value Pane, and press
the right mouse key to bring up the Radix popup menu, then select Binary. The
three bits are displayed as "111" at time 130.

Tracing a Memory Data Path using the Multiple Net Display

1. Select Logic from the Window menu to open a Logic Browser Window.
2. Reposition the Logic Browser Window to the lower right of your screen.
3. Drag and Drop the signal opcode[2:0] from the Waveform Window to the Logic
Browser Window.
4. Enlarge the Logic Browser Window to fit most of your screen
5. Click on the input port opcode[2:0] to traverse up one level of the design. It is fed
by instreg which is fed by the data[7:0] signal.

Figure 6-3. Traversing up the Logic Browser

VirSim Tutorial 6-5

Synopsys

6. Click on data[7:0] to see it being fed by the mem1 module bi-directional port.
7. Click inside the mem1 module on the data[7:0] pin to traverse down inside the
mem1 memory module.
See Figure 6-4, Traversing Inside the mem1 Module. Note that data[7:0] is fed
by the tbo (tribuf) module bi-directional port. It has an input memaddr[7:0].

Figure 6-4. Traversing Inside the mem1 Module

8. Click on memaddr[7:0] port to see it fed by an assign statement

memaddr=memory[addr];
9. Click on the input to the assign statement memory[0:31] to see it fed by register
memory.
10. Point to the net name memory[0:31] to view the value of all memory in the status
bar. This data is the data you expanded in the Waveform Window.
11. In the Logic Browser Window, select Close Window from the File menu to close
this Logic Browser Window.

6-6 VirSim Tutorial

 New Visibility Features

Viewing Annotated Source code in the Source Window

1. Click the upper left Source Window to bring it to the front.
2. Select the Show Values from the Display menu in the Source Window.
Additional lines that contain the value for each signal will be added in the Source
Window. Values displayed in pink have changed value at the current simulation
time. Values in white have not changed this simulation time.

Figure 6-5. Displaying Values in the Source Window

Viewing and Creating Buses

Bus Builder is available to quickly bus signals together for display.
1. From any VirSim window, select Load Configuration from the File menu to open
the Load Configuration Dialog.
2. In the Configuration Dialog, select mem4.cfg, and click OK.
A new set of VirSim windows open with two buses displayed in the Waveform
Window.
3. In the Waveform Window, click on Edit->Buses to open the Bus Builder Dialog.
Notice the two buses, mem_ctrl, and mem_interface, are listed in the Buses pane.
See Figure 6-6, Bus Builder Dialog.

VirSim Tutorial 6-7

Synopsys

Figure 6-6. Bus Builder Dialog

4. Click on the mem_ctrl bus in the Buses pane.

The contents of the bus are now displayed in the Components pane. The
mem_ctrl[6:0] bus is made up of read, write, and addr[4:0], making a seven bit
bus.
5. Click on the mem_interface bus in the Buses pane.
The contents of the bus are now displayed in the components pane. The
mem_interface bus is made up of the signals mem_ctrl[6:0], and data[7:0], mak-
ing a 15 bit bus.
6. In the Waveform Window, quickly double click the mem_interface bus in the Sig-
nal Name pane.
The bus is expanded to mem_ctrl[6:0] and data[7:0].
7. Quickly double click the mem_ctrl[6:0] to expand it to the read, write, and
addr[4:0] signals. See Figure 6-7, Expanding Signals in the Waveform.

6-8 VirSim Tutorial

 New Visibility Features

Figure 6-7. Expanding Signals in the Waveform

8. Quickly double click the addr[4:0] signal to expand it into five separate bits.
9. Quickly double click the data[7:0] signal to expand it into eight separate bits.
10. In the Bus Builder Dialog, deselect both buses by clicking on them if selected.
11. Drag and Drop the following four signals from the Waveform Window to the Com-
ponents pane in the Bus Builder Dialog:
read write addr[4] data[7]
See Figure 6-8, Dragging and Dropping Signals into the Bus Builder Dialog.

VirSim Tutorial 6-9

Synopsys

Figure 6-8. Dragging and Dropping Signals into the Bus Builder Dialog

12. Click Add in the Bus Builder Dialog to create a new four bit bus named bus1.
Notice in the Hierarchy Browser that bus1 is now listed as a signal in the Signal
Pane.

6-10 VirSim Tutorial

 New Visibility Features

Figure 6-9. New Signal, bus1, in the Signals Pane of the Hierarchy Browser

13. Drag and Drop bus1 into the Waveform Window to see it displayed. Then expand
bus1.

VirSim Tutorial 6-11

Synopsys

6-12 VirSim Tutorial


Managing Large Amounts of Data
In This Chapter
„ Preparing for this Lesson
„ Open and Close VCD+ Files During
Simulation
„ Loading a Partial VCD+ File into VirSim
Chapter 7
In this lesson you will learn how
to save data into more than one
VCD+ file during a simulation
run, which creates multiple
smaller files for quicker
reference during debug. You will
also learn how to load a partial
VCD+ file when you need only
debug part of the file data. You
can control (copy, move, or
delete) the VCD+ files during a
simulation run with system calls
once a VCD+ file is closed.You
can, for instance, delete a file
from within the simulation once
you see the results are as
expected and then automatically
continue with the next test.

NOTE: Being selective with data saved via

the arguments to the $vcdplus
commands will also reduce the size
of VCD+ files.

VirSim Tutorial 7-1

Synopsys

Preparing for this Lesson

You performed the last lesson in the risc4 directory. Files for this lesson are located in
the risc5 directory.
1. If you are running VirSim in the risc4 directory, exit VirSim. To exit, choose Exit
from the File menu on any VirSim window.
2. When the save prompt appears, select No.
3. To the access the risc5 directory, go to the following location:
„ For VCS VirSim:
$VCS_HOME/virsimdir/examples/tutorial/verilog/risc5
„ For VirSim:
$VIRSIMHOME/examples/tutorial/verilog/risc5
4. Start the tutorial by doing one of the following:
„ Enter the script file which contains the full VirSim command line:
run_risc5
„ Enter one of the following full command lines:
• For VCS VirSim:
vcs -RPP +vpdfile+file1.vpd +vpdfile+file2.vpd
+cfgfile+risc5.cfg -f run.f

• For VirSim:
virsim +vpdfile+file1.vpd +vpdfile+file2.vpd
+cfgfile+risc5.cfg -f run.f

Open and Close VCD+ Files During Simulation

Two new VirSim tasks are used in this lesson:
„ $vcdplusfile("filename")
„ $vcdplusclose
To open and close VCD+ files. Add a $vcdplusclose; to close an existing file and
vcdplusfile("filename"); and $vcdpluson(...); to open a new one. VirSim will then dump
VCD+ data as specified.
The function "$vcdplusfile" takes one argument. The argument is a double quoted
string giving the name to use for the next opened VPD file. It overrides the default
name and any name specified on the command line. It does not change the name of
the currently opened VPD file, only the next one to be opened.
The function "$vcdplusclose" takes no arguments. It causes all value change and line
trace recording to be turned off and the VPD file to be marked as complete and
closed.
VirSim supports one VPD file being open at a time. These functions do allow a single
simulation to create multiple VPD files from one simulation run. They are serial and do
not overlap.
1. View the source code (module test.i1) in the Source Window. Module instrument
has the statements as seen in the figure below.

7-2 VirSim Tutorial

 Managing Large Amounts of Data

Figure 7-1. Initial View of Source Window

2. Already displayed in the Waveform Window are:

a. Six signals from the file1.vpd file.
b. A blank line in the Waveform Window.
c. Six signals from the file2.vpd file.
See Figure 7-2, Initial Appearance of Waveform Window.

VirSim Tutorial 7-3

Synopsys

Figure 7-2. Initial Appearance of Waveform Window

3. Viewing the results in the Waveform Window, you can see data displayed for the
"V1" file file1.vpd, from time 0 to time 100. The file name is defined in the $vcd-
plusfile("file1.vpd"); statement, the data collection started at time 0 with the first
$vcdpluson; statement, and the file closed at time 100 with the #100 and the first
$vcdplusclose; statements
4. Viewing the results in the Waveform Window, you can see data displayed for the
"V2" file file2.vpd, from time 110 to time 310. The file name is defined in the $vcd-
plusfile("file2.vpd"); statement, the data collection started at time 110 with the sec-
ond $vcdpluson; statement, and the file closed at time 310 with the #200 and the
second $vcdplusclose; statements.
5. In the Waveform Window, point to the V1 clock signal at time 80, press the right
mouse, and select Expand Time from the popup menu. Delta cycle data is dis-
played as a result of the $vcdplusdeltacycleon statement.
6. In the Waveform Window, point to the V2 clock signal at time 160, press the right
mouse, and select Expand Time from the popup menu. Delta cycle data is dis-
played as a result of the same $vcdplusdeltacycleon statement.

7-4 VirSim Tutorial

 Managing Large Amounts of Data

Loading a Partial VCD+ File into VirSim

VirSim has the ability to load part of a VCD+ file to improve load and signal access
time.
In the risc5 directory there is a large VCD+ file called file3.vpd. It has signal data
stored from time 0 to time 502,000.
You can load part of a VCD+ file by either specifying the start and/or end time on the
VirSim command line if you know the times in the file, or you can use the File->Open
dialog to view the simulation times in the file and select the amount of signal data time
you want to load.
1. If you are running VirSim in the risc5 directory, exit VirSim. To exit, either
a. Click left on Exit on the Main menu.
or
b. Choose Exit from the File menu on any VirSim window.
2. When the save prompt appears, select No.
3. Still in the risc5 directory, at the command prompt, either enter the full command
line:
virsim +vpdfile+file3.vpd+start+8000+end+14000 +cfgfile+large.cfg
or run the script file which contains the full VirSim command line:
large_run_risc5
4. View the data in the Waveform Window. Data is displayed from time 800 to time
1400. This is the time specified in the command line in step 3 with allowance for
the time scale factor in the design.

Figure 7-3. Viewing a Partial VCD + File

VirSim Tutorial 7-5

Synopsys

5. In any window select File->Open to open the Open File Dialog.

6. Select file3.vpd in the dialog to see the File Range Start Time of 0.0 and the File
Range End Time of 502,000 displayed. Also displayed is the Load Range of 800
and 1,400 which is the load time selected on the VirSim command line.

Figure 7-4. Open File Dialog

7. Modify the Load Range Start time to 1,200 and the Load Range End Time to
46,500.
8. Click Apply. The file3.vpd data now available to view is time 1,200 to 46,500.
9. Data displayed in the Waveform Window starts at time 1,200. Scroll right in the
Waveform Window to see data to time 46,500.

7-6 VirSim Tutorial