Flip-flop (electronics)

In electronics, a flip-flop is a circuit that has two stable states and can be used to store state
information. The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. A circuit incorporating flip-flops has the attribute of state;
its output depends not only on its current input, but also on its previous inputs. Such a circuit is
described as sequential logic. Where a single input is provided, the circuit changes state every time a
pulse appears on the input signal. Since the flip-flop retains the state after the signal pulses are
removed, one type of flip-flop circuit is also called a "latch". Other types of flip-flops may have
inputs that set a particular state, set the opposite state, or change states, depending on which
input is pulsed.

Flip-flops are used as data storage elements, for counting of pulses, and for synchronizing
randomly-timed input signals to some reference timing signal. Flip-flops are a fundamental
building block of digital electronics systems used in computers, communications, and many other
types of systems.

History
The first electronic flip-flop was invented in 1918 by William Eccles and F. W. Jordan. It was initially
called the Eccles–Jordan trigger circuit and consisted of two active elements (vacuum tubes). Such
circuits and their transistorized versions were common in computers even after the introduction of
integrated circuits, though flip-flops made from logic gates are also now common.

Early flip-flops were known variously as trigger circuits or multivibrators. A multivibrator is a two-
state circuit; they come in several varieties, based on whether each state is stable or not: an
astable multivibrator is not stable in either state, so it acts as a relaxation oscillator; a monostable
multivibrator makes a pulse while in the unstable state, then returns to the stable state, and is
known as a one-shot; a bistable multivibrator has two stable states, and this is the one usually
known as a flip-flop. However, this terminology has been somewhat variable, historically. For
example:

• 1942 – multivibrator implies astable: "The multivibrator circuit (Fig. 7-6) is somewhat similar
to the flip-flop circuit, but the coupling from the anode of one valve to the grid of the other
is by a condenser only, so that the coupling is not maintained in the steady state."
• 1942 – multivibrator as a particular flip-flop circuit: "Such circuits were known as 'trigger' or
'flip-flop' circuits and were of very great importance. The earliest and best known of these
circuits was the multivibrator."
• 1943 – flip-flop as one-shot pulse generator: "It should be noted that an essential difference
between the two-valve flip-flop and the multivibrator is that the flip-flop has one of the
valves biased to cutoff."
• 1949 – monostable as flip-flop: "Monostable multivibrators have also been called 'flip-
flops'."
• 1949 – monostable as flip-flop: "... a flip-flop is a monostable multivibrator and the ordinary
multivibrator is an astable multivibrator."

According to P. L. Lindley, a JPL engineer, the flip-flop types discussed below (RS, D, T, JK) were
first discussed in a 1954 UCLA course on computer design by Montgomery Phister, and then
appeared in his book Logical Design of Digital Computers. Lindley was at the time working at
Hughes Aircraft under Dr. Eldred Nelson, who had coined the term JK for a flip-flop which changed
states when both inputs were on. The other names were coined by Phister. They differ slightly from
some of the definitions given below. Lindley explains that he heard the story of the JK flip-flop from
Dr. Eldred Nelson, who is responsible for coining the term while working at Hughes Aircraft. Flip-flops
in use at Hughes at the time were all of the type that came to be known as J-K. In designing a
logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3:
E & F, #4: G & H, #5: J & K.

Table 1. Flip-flop Types

FLIP-FLOP FLIP-FLOP CHARACTERISTIC CHARACTERISTI EXCITATION

NAME SYMBOL TABLE C EQUATION TABLE

Q(next) = S + R'Q

SR = 0
Q Qt)(nex S R
S R Q(next)
SR
0 0 0 X
0 0 Q
0 1 1 0
0 1 0
1 0 0 1
1 0 1 1 1 X 0
1 1 ?

Q(next) = JQ' + K'Q

JK J K Q(next)
Q Q(nex J K
0 0 Q t)

0 1 0 0 0 0 X
1 0 1 0 1 1 X
1 1 Q' 1 0 X 1
1 1 X 0

Q(next) = D
D Q Q(next) D
D Q(next)
0 0 0
0 0
0 1 1
1 1
1 0 0
 Q(next) = TQ' + T'Q
Q Q(next) T
0 0 0
T
0 1 1
T Q(next)
1 0 1
0 Q
1 1 0
1 Q'

The characteristic table in the third column of Table 1 defines the state of each flip-flop as a function of its inputs and
previous state. Q refers to the present state and Q(next) refers to the next state after the occurrence of the clock pulse. The
characteristic table for the RS flip-flop shows that the next state is equal to the present state when both inputs S and R are
equal to 0. When R=1, the next clock pulse clears the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation
mark (?) for the next state when S and R are both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S and R respectively,
except for the indeterminate case. When both J and K are equal to 1, the next state is equal to the complement of the present
state, that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and independent of the present state.
The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.
The characteristic table is useful during the analysis of sequential circuits when the value of flip-flop inputs are known and
we want to find the value of the flip-flop output Q after the rising edge of the clock signal. As with any other truth table, we
can use the map method to derive the characteristic equation for each flip-flop, which are shown in the third column of
Table 1.
During the design process we usually know the transition from present state to the next state and wish to find the flip-flop
input conditions that will cause the required transition. For this reason we will need a table that lists the required inputs for a
given change of state. Such a list is called theexcitation table, which is shown in the fourth column of Table 1. There are
four possible transitions from present state to the next state. The required input conditions are derived from the information
available in the characteristic table. The symbol X in the table represents a "don't care" condition, that is, it does not matter
whether the input is 1 or 0.

Flip-flop types

SR NOR latch
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and
reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If
S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly,
if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

SR latch operation
S R Action
0 0 Keep state
0 1 Q=0
1 0 Q=1
1 1 Restricted combination The symbol for an SR latch.
The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output
zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go
low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the
propagation time relations between the gates (arace condition). In certain implementations, it could also lead to longer
ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-
frequency digital circuits. Although this condition is usually avoided, it can be useful in some applications.

To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-
restricted combinations. That can be:

• Q = 1 (1,0) – referred to as an S-latch

• Q = 0 (0,1) – referred to as an R-latch
• Keep state (0,0) – referred to as an E-latch
Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.

Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.