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Design Entry
Advanced Design HDL Edit and Entry
¾
Map
To simulate a design:
In the Sources in Project window,
select a testbench file
In the Processes for Source window,
expand ModelSim Simulator
Double-click Simulate
Behavioral Model or
Simulate Post-Place & Route
Model
• Can also simulate after Translate
or after Map
ISE 6.1i is designed and tested to run with the leading HDL simulators in the
industry
Cadence NC-Sim
Model Technology ModelSim
Synopsys VCS-MX and Scirocco
All Xilinx libraries and netlists conform to IEEE VHDL-93, VITAL-2000 and Verilog-
2001 standards
Other simulators are available to perform Xilinx CPLD and FPGA verification
Synplify/Pro 7.3.1
Ability to use the parity bit in Virtex™-II, Virtex-II Pro™, and Spartan™-3
devices to optimize Block RAM implementations
Improved area optimization for Virtex-II, Virtex-II Pro, and Spartan-3 devices
Precision 2003b
Support Virtex-E/-II/-II Pro, Spartan-II/-IIE/-3
Advanced design analysis
LeonardoSpectrum 2003b
Support Spartan-3 family
FCII v3.8
Support for Spartan-3 devices
Support for all Virtex-II Pro devices
ModelSim
Data values
1, 0 ,X ,Z, U
Assignments
Double-click bit signal to toggle value
Pattern wizard assigns a range of cell values
WaveTable assign signals like a spreadsheet
By default, decimal values are shown in the WaveTable
Waveform values are checked as they are entered
Validation check for non-binary inputs only (for example, hex, or decimal)
Available patterns
Pattern description
Changes depending on the
pattern selected
To view testbench:
In Sources in Project Window, select the TBW file
Then in the Processes for Current Source window,
click View Behavioral Testbench
•Functional Simulation
•Does function match RTL
Golden model
Simulation process
A core is a ready-made function that you can instantiate into your design as a
“black box”
Cores can range in complexity
Simple arithmetic operators, such as adders, accumulators, and multipliers
System-level building blocks, including filters, transforms, and memories
Specialized functions, such as bus interfaces, controllers, and microprocessors
Some cores can be customized
LogiCORE solutions
DSP functions AllianceCORE solutions
• Time skew buffers, FIR filters, Peripherals
correlators
• DMA controllers
Math functions
• Programmable interrupt controllers
• Accumulators, adders, multipliers,
integrators, square root • UARTs
Memories Communications and networking
• Pipelined delay elements, single • ATM
and dual-port RAM • Reed-Solomon encoders / decoders
• Synchronous FIFOs • T1 framers
PCI master and slave interfaces, PCI Standard bus interfaces
bridge • PCMCIA, USB
Features
Functionality
Pinout
Resource utilization
Frequency synthesizer
Select M / D value
OR
Specify frequency
“Calculate” button for jitter
Period jitter is evaluated for CLKFX output