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1, SEPTEMBER 2009 1
- EC
Cgs /Cox -- --
øm - q*psiSi
1 HFCV
Ef
qVapp Ei
GATE
EV
BULK
OXIDE
LFCV
OHMIC CONTACT
0 VTH,n VGS
(a)
(b) (c)
Fig. 1: (a) MOS device [4](b) Ideal CV curves of a nMOS capacitor [1] (c) Band bending of MOS capacitor for VT < VG [9]
B. Thermal Oxidation
Thermal oxidation is carried out for the wafers G2W1 and
G2W2 for the growth of SiO2 layer on the cleaned Si surfaces.
The wafers are loaded in the furnace at 1000◦ C and having an
initial N2 ambient. Then oxygen gas is passed for 25 minutes.
At the end of this duration, the ambient is again switched to
N2 and wafers are then unloaded.
Fig. 2: Fabrication steps of (a) SiO2 and (b) Eu2 O3 as
dielectric materials. C. RF Sputtering
The RF magnetron sputtering technique is used to deposit
High-K dielectric layer of Eu2 O3 on the cleaned wafer sam-
deposition of Eu2 O3 , p-type wafer are annealed as described ples G2W3 and G2W4. Parameters in the sputtering process
in Sec. II-D. The final step of fabrication involves forming gas are shown in Tab. III. First, vacuum is created by bringing
annealing described in Sec. II-J. down the pressure of sputtering chamber to 2×10−5 mbar.
Then flushing is carried out using Ar gas and the pressure
A. Wafer Cleaning increases to 7×10−3 mbar. Pre-sputtering for 10 min is carried
All the four wafers described in Tab. I are cleaned as to avoid the deposition of any impurities on the wafer which
described by the steps shown in Tab. II [6]. The following may be present on the surface of the target. In the present
precautions are observed during wafer cleaning. experiment, the oxide thickness required is 10 nm and the
1) All the chemicals are CMOS grade and they are taken rate of deposition is 1.6 nm/min. Hence the sputtering time is
only in Quartz beaker. allowed for 6 min.
2) Above 80◦ C H2 O2 can dissociate and Si Wafer can get
oxidized in an uncontrolled way. D. Annealing
3) During HF dip, the solution is always taken in teflon The p-type wafers are annealed at 1000◦ C in the inert
beaker. atmosphere of N2 with flow rate of 3 Lts/min for about 30
4) Si is hydrophobic, while SiO2 is hydrophilic. The min.This process decreases the lattice defects present in the
completion of the etching of the native oxide layer is sample and hence reduces the fixed oxide charges.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 3
r,Si 11.7
measurement instrument is limited to 2 W. Hence for a DC r,SiO2 3.9
voltage of 20 V, the current is limited to 50 mA. The results r,Eu2 O3 24 [5, High-K]
of IV measurements is shown in Sec. V. KB 1.38×1023 J/K
T 298 K
q 1.6×10−19 C
IV. CV M EASUREMENT R ESULTS h̄ 1.0545×10−34 Js
mO 9.1×10−31 Kg
The CV plots from the measured data is shown in Fig. 4 m∗SiO 0.0.39mO
2
m∗Eu O 0.11mO [8]
and Fig. 5. 2 3
χAl 4.1 eV
χSi 4.05 eV
Eg,Si 1.12 eV
ni 1.15×1016 m−3
The procedure used to analyse measured CV data is de- Fig. 7: Oxide thickness of different wafers. The oxide thick-
scribed in Appendix A. In accordance to this procedure, a ness of SiO2 conforms with the FTP measurement described
software program is written to process the measured data. in Sec. III-B, while the thickness of Eu2 O3 is higher than the
predicted deposited value of 10 nm (Sec. II-C)
The figures Fig. 6 to Fig. 10 show different parameters
obtained through extraction of measured data.
The plot of interface trap density Dit for all the four wafers
is shown in Fig. 10. A. F-N Tunneling
2
The plots of J/EOX vs EOX shown in Fig. 11 and ig. 12
V. IV M EASUREMENT R ESULTS
are obtained by the procedure described in Appendix. C. Using
The procedure used to analyse measured IV data is de- these plots the barrier energy φOX between EC,Si and EC,OX
scribed in Appendix C. is obtained.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 6
B. Breakdown Voltage
Breakdown voltages of different wafers is shown in Fig. 13
The following parameters were extracted by IV and CV
measurements and they are summarised in Tab. V-B.
A PPENDIX A
A NALYSIS OF CV M EASUREMENTS
The procedure used to analyse the measured data of the
MOS capacitor is detailed here [4, Brews], [10, taur]. . The Fig. 9: Variation of Dit for different values of ψs (for G2W1
algorithm was implemented in Matlab to analyse the data and above and G2W2 below). The figure shows that Dit,min of
obtain the plots. n-type wafer is more than p-type because n-type wafers are
not annealed in inert ambient.
A. Determination of NA,D
1) The capacitance of the measured CV curve is normalised
for area.
5) Using the above value of Wdep,max , Equ. 4 is solved
2) The maximum value of capacitance is assigned COX , it
numerically to obtain the doping concentration of the
assumed that Cacc and Cinv is very large compared to
substrate (It is assumed that the substrate is uniformly
COX .
doped).
3) Minimum capacitance (Cmin ) of CV curves is a series
combination of COX and Cdep . Cdep at inversion can √
be obtained using Equ. 2 with Cg = Cmin . 4Si ln(NA,D /ni )φt
−1 −1
Wdep,max = (4)
Cg = (COX + Cdep,min )−1 (2) qNA,D
4) Wdep is obtained by Equ. 3.
Si Equ. 4 is valid beyond inversion and without deep
Wdep,max = (3) depletion.
Cdep
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 7
0 1
Cacc = 2 + COX (14)
ω 2 COX Rleak
Equ. 14 shows that the measured capacitance C’ is
higher than COX and this value reduces with increase
Fig. 14: (a) and (b) Model of MOS capacitor (c) Components in frequency. This necessitates correction of maximum
resolved by LCR meter capacitance from C-V curve to obtain COX . If the oxide
thickness is small then the leakage is large which implies
that R’ will be smaller. This means that the dependence
1) For each value of Cg at Vit from the measured data, of C’ with frequency increases for lower oxide thickness.
Cdep is obtained using Equ. 2. Surface potential ψs is 2) Inversion : CSi → Cdep since Cinv,dep → 0 and Rleak
calculated using Equ. 9. is large since the minority carriers do not respond to the
√ small signal variation. Equ. 13 can be approximated as.
2Si ψs
Wdep = (9) Cdep COX
qNA,D 0
Cinv = (15)
Cdep + COX
Where Wdep = Si /Wdep .
The Equ. 15 is independent of Rleak .
2) The ideal value of gate voltage is obtained from Equ. 10
using ψs from Equ. 9.
A PPENDIX C
qNA,D Wdep
Vg,ideal = φM S + ψs + (10) A NALYSIS OF IV M EASUREMENTS
COX
The IV measurements are used to determine the break down
3) The difference ∆Vit = Vg,ideal − Vit is the contribution voltage and the barrier of the dielectric. Since the dielectric
of Qit given in Equ. 11. thickness for all the wafers is greater than 10 nm, The IV plots
Qf = COX ∆Vit (11) are analysed for Fowler-Nordheim (F-N) Tunneling. When F-
N tunneling occurs, the current density is given by Equ. 16.
4) A plot of Qit vs ψs and Dit vs ψs is obtained. Where ( √ )
3/2
qDit = dQit /dψs . q 3 EOX
2
4 2m∗φOX
JF N = exp − (16)
8πhφOX 3h̄qEOX
A PPENDIX B Where
VARIATION OF ACCUMULATION CAPACITANCE WITH
VG − VF B − ψs,acc
FREQUENCY EOX = (17)
tOX
The measured capacitance varies with frequency of mea- ψs,acc,p−type = −Eg /2 + φB (18)
surement. This can be explained as follows. The LCR meter
ψs,acc,n−type = Eg /2 − φB (19)
will apply a voltage and determine the current, this current
is resolved into in phase and out of phase components. The 2
A plot of log(J√F N /EOX ) vs 1/EOX gives a straight line
3/2
in phase and out of phase capacitance will be resolved into 4 2m∗φOX
with slope = − 3h̄q [7, Lenzlinger], using which φOX
resistance and capacitance respectively as shown in Fig. 14.
can be determined.
The leakage resistance of the dielectric can be modeled as a
resistor in parallel to COX . The value of resistor depends on
the region of operation of the MOS capacitor. C ONCLUSION
From the models in Fig. 14(b) and Fig. 14(c), the following MOS capacitors were fabricated using SiO2 and Eu2 O3 as
relations can be derived. dielectric materials. The capacitor uses Si substrate with Al
as another terminal. The following conclusion are drawn from
Rleak
R 0 = RC + 2 2 R2 (12) the measurements.
1+ ω COX leak 1) The wafer doping concentration obtained by CV mea-
CSi (1 + ω 2 COX
2 2
Rleak ) surements are comparable to resistivity measurements.
C0 = 2 2 (13) 2) The oxide thickness of SiO2 conforms with the FTP
1 + ω COX Rleak (COX + CSi )
measurement described in Sec. III-B, while the thickness
Here, ω is the angular frequency of measurement, CSi is of Eu2 O3 is higher than the predicted deposited value
the capacitance of the silicon substrate, RC is the contact of 10 nm.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 9
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