A Multi-Level QAM Demodulator LSI

with Wideband Carrier Recovery and Dual Equalizing Mode

Kazuya Yamana ka, Sumita ka Takeuc hi, Shuji Muraka mi,
Masayu ki Koyama , Michir u Hori, Nobuhi ro Miyosh i,
Keisuk e Okada and Tadash i Sumi

System LSI Labora tory, Mitsub ishi Electr ic Corpor ation

4-1 Mizuha ra, Itami, Hyogo, Japan
e-mail : kyaman ak@lsi.m elco.co.jp

Abs tra ct -- A 4-/16- /64-/256-QAM demodul ator LSI with an all-di gital
carrie r-recovery loop includ ing a novel phase detect or and a fracti onally-/
symbol -spaced equali zer is descri bed. The phase detect or, decidi ng the
transm itted symbol from receiv ed signal power, detect s the phase error up
to +/-45 degree s and enable s the loop to intern ally elimin ate the +/-80 KHz
carrie r-frequenc y offset . The fracti onally-spa ced equali zer is implem ented at
the same clock rate as the symbol -spaced equali zer by only increa sing the
select ors and flip-f lops, though the former theore tically requir es a two times
faster operat ion than the latter . An LSI operating at a symbol rate up to 8
MBaud is succes sfully implem ented.

1. Introd uction
Digita l cable servic es such as intera ctive TV and modem system s are now ready for launch .
The quadra ture amplit ude modula tion (QAM) techni que is a establ ished modula tion scheme
for these servic es becaus e of its high bandwi dth effici ency [1]. QAM demodu lator LSIs are
desire d so as to realiz e low-co st cable system s [2-4]. For robust cable system s, the follow ing
two QAM demodu lator LSI functi ons must be improv ed. One is to elimin ate the carrie r-
freque ncy offset mainly due to the inaccu racy of analog front- end circui ts such as a tuner. The
other is to equali ze multi- path distor tion caused by reflec tions in the cable channe l.
This paper presen ts a 4-/16- /64-/256-QAM demodu lator LSI with an all-di gital carrie r-
recove ry loop includ ing a novel phase detect or and a fracti onally(T/2 )-/symbol( T)-spaced
equali zer. The LSI elimin ates a carrie r-frequ ency offset up to +/-80 KHz in an 8-MHz
bandwi dth, while conven tional LSIs empiri cally elimin ate an offset less than +/-10 KHz. The
advanc e lies in a newly- developed phase detect or which detect s phase errors up to +/-45
degree s. The T/2-sp aced mode is suppor ted in the LSI as well as the conven tional T-spac ed
mode, withou t increa sing the clock rate. The T/2-sp aced mode operat ion is achiev ed by
adding select ors and negati ve edge trigge red flip-f lops to the T-spac ed circui try. The two
modes are contro lled via a serial -bus interf ace. A softwa re verifi cation strate gy result s in a
very high degree of design certai nty, so that the comple te functi onality of the LSI can be
guaran teed.

2. S ys tem Des cri ption

Figure 1 shows a block diagra m of the QAM demodu lator LSI. The chip has two carrie r-
recove ry circui ts and a decisi on-feedbac k equali zer (DFE). The auto freque ncy contro l (AFC)
loop and the auto phase contro l (APC) loop constr uct the outer and inner carrie r-recovery
circui ts respec tively. The AFC loop-f ilter output is fed back to the analog tuner to coarse ly
elimin ate the carrie r-frequenc y offset . The intern ally-close d APC loop remove s the remain ing
freque ncy offset and phase jitter .

3. Wideba nd Carrie r Recove ry

As the AFC loop does not finely elimin ate the carrier -frequency offset , the APC loop has
an import ant role in carrie r recove ry. The novel phase detect or, which detect s a phase error up
to +/-45 degree s, is the key compon ent of the APC loop.
A block diagra m of the phase detect or is shown in Figure 2. First, transm itted symbol s
having simila r power to the receiv ed signal (Xi, Xq) are predic ted. Maxima lly four symbol s
(S1 to S4) are predic ted for every receiv ed signal in the case of the 256 QAM. Then tangen ts
of the phase error theta betwee n the receiv ed signal and the predic ted symbol s are calcul ated
(E1 to E4). The absolu te values of the tangen ts are limite d to less than 1. Thus, the detect able
range of theta is bounde d to +/-45 degree s. Each calcul ated error is assign ed to one of 16
region s. A phase error is detect ed when the same region is assign ed by four consec utively
receiv ed signal s.
In conven tional phase detect ion the transm itted symbol is determ ined as that neares t to the
receiv ed signal , as shown in Figure 3a. Thus, the detect able phase- error range depend s on the
QAM level. The range is as small as 7.7 degree s for 64 QAM or 3.4 degree s for 256 QAM.
The propos ed phase detect or does not depend on the QAM level, becaus e it uses the receiv ed
signal power as shown Figure 3b.
The detect able phase range decisi vely influe nces the APC-lo op perfor mance. The bounda ry
of the pull-i n range of the presen t APC loop is up to +/-80 KHz, while it is empiri cally less
than +/-10 KHz using conven tional circui ts.

4. Dual Equali zing Mode

The DFE has 8 feedfo rward taps and 16 feedba ck taps, where T/2-sp aced mode is applie d
to the feedfo rward taps. The T/2-sp aced equali zer perfor ms better than the T-spac ed one
becaus e of its wide bandwi dth [5]. Some previo us equali zer LSIs [3,4], howeve r, do not
suppor t T/2-sp aced mode because the mode theore tically requir es circui ts operat ing twice as
fast as those of the T-spac ed mode.
Figure 4 shows a block diagra m of the presen t equali zer. In T/2-sp aced mode, every other
input data are loaded to the even-t ap circui t at the positi ve clock edge. The remain ing data is
loaded to the odd-ta p circui t at the negati ve clock edge. Each circui t acquir es the data at half
the rate of the input data, theref ore the T/2-sp aced mode equali zer operat es at the same clock
rate as the T-spac ed mode equali zer. The two modes are contro lled via a serial -bus interf ace.

5. Res ult s
A Signal Proces sing Worksy stem (SPW;T M) hardwa re design model was used to verify
the LSI functi ons. The pull-i n time of the APC loop is shown Figure 5. In the cases of 10
KHz and 80 KHz the carrie r-frequenc y offset errors are elimin ated in 7 msec and 64 msec
respec tively. Figure 6 shows the I-phas e output signal , Q-phas e output signal , and APC
loop-f ilter output . A breadb oard was fabric ated based on the hardwa re design model and its
real time functi on was succes sfully confir med.
 Figure 7 shows a layout of the QAM demodu lator LSI. The chip integr ates 880,00 0
transi stors in a die size of (12.87 mm*12.49 mm) using 0.5 micron CMOS 3-meta l
techno logy. The supply voltag e is 3.3V. The LSI is packed in a 128-pi n QFP.

6. Conclu s ions
A multi- level QAM demodu lator LSI with wideba nd carrie r recove ry and dual equali zing
mode was presen ted. The chip has a novel phase detect or circui t that uses the receiv ed signal
power. The signal which has a +/-80 KHz carrier-f requency offset is fully recove red in 64
msec. The T/2-sp aced mode is suppor ted in the LSI as well as the conven tional T-spac ed
mode withou t increa sing the clock rate. The T/2-sp aced equali zing mode is achiev ed by
adding select ors and negati ve edge trigger ed flip-f lops to the T-spac ed circui try. The
techni ques of the QAM demodu lator LSI presen ted will decrea se the cost of digita l
transm ission system s.

Refere nces
[1] "Europ ean Teleco mmunicatio n Standa rd DRAFT prETS 300 429," 1994.
[2] E. De Man, M. Schulz and R. Schmid maier, "A 1.0-um CMOS 60-MBa ud single -chip
QAM proces sor for digita l radio applic ations," in Proc. CICC, pp.55- 58, May 1994.
[3] Y. Ishiza wa, Y. Yanai and I. Nakaya ma, "64/25 6 QAM Chip-S et for Digita l CATV
Applic ation," in Dig. Tech. Pap. ICCE, pp.36- 37, June 1995.
[4] S. Brand and W. Welter sbach, "A QAM Demodu lation Concep t for Digita l Video Cable
Transm ission," in Dig. Tech. Pap. ICCE, pp.38- 39, June 1995.
[5] J. G. Proaki s, Digital Commun ications, Second Editio n, McGraw -Hill, 1989.

QAM Demodulator LSI

Square-root
Derotator
Phase
Carrier

I OUT
Decoder
Differential
Equalizer
Feedback
Decision

Nyquist
Analog IN Filter ( I )
RF ADC
COS
SIN
Input Tuner Square-root
Nyquist
Filter (Q) Q OUT
SIN

(APC Loop) COS AGC OUT

AGC
Numerically APC
Controlled Loop Phase
Oscillator Filter Detector Clock CLOCK OUT
Recovery

AFC
Loop Serial CLOCK
LPF Loop
AFC OUT Filter Select Bus
I/F DATA

Figure 1. Block diagram of QAM Demodulator LSI.

 AAA
Q Q
Transmitted
Power Symbol

AAA
Calculation Prediction
S2 Transmitted

S4
S1

S3 symbol point

AAA
Transmitted
symbol point
Xi
Phase Error I (θ I
Angle Calculation Received Signal Received Signal
Xq (Xi, Xq)
(Xi, Xq)
Error
Decision
E2

E4
E1

E3

Phase
Error
Selection

Figure 2. Block diagram of

EOUT

(a) Conventional Phase Detection AAA

Detectable Range
(b) Present Phase Detection

Figure 3. Comparison of Phase Detection (16 QAM).

Present Phase Detector.
8 tap (T, T/2) Pull-in Time (msec)
1: T-Spaced
4 tap (T)
0: T/2-Spaced
60
M0 Z-1
M1 IN
U
Z-1 Z-1 Z-1 X Z-1 Z-1 Z-1 U 50
1 X Z-1 Z-1
0
40
Latched by negative edge of clock
30
+ Z-1 + Z-1 OUT
20
Even-tap(T/2) Odd-tap(T/2)
10
Carrier-
0 Frequency
1 5 10 50 70 80 Offset (KHz)

Conventional limitation

Figure 4. Block diagram of Present Equalizer. Figure 5. Pull-in Time of the APC Loop (64 QAM).

I-phase
Output

Q-phase
Output

APC
Loop Filter
Output

Figure 6. Simulated Waveform of APC Loop

Figure 7. Layout of the QAM Demodulator LSI.
(64 QAM, Carrier-Frequency Offset = 80 KHz).