LIBRARY ieee;

USE iee.std_logic_1164.ALL;

ENTITY alu IS
PORT(a : IN std_logic_vector(7 DOWNTO 0);--entrada 2
b : IN std_logic_vector(7 DOWNTO 0);--entrada 1
proceso : IN std_logic_vector(3 DOWNTO 0);--que hara la alu
c : OUT std_logic_vector(15 DOWNTO 0));
END alu;

ARCHITECTURE synth OF alu IS

BEGIN
PROCESS (a, b, proceso)
BEGIN
CASE proceso IS
WHEN "0000" => c <= "0000000" & (a + b);
WHEN "0001" =>
IF a < b THEN
c <= "1000000" & (b - a);
ELSE
c <= "00000000" & (a - b);
END IF;
WHEN "0010" =>
........
WHEN OTHERS => null;
END CASE;
END PROCESS;
END synth;