LOVELY PROFESSIONAL UNIVERSITY

MODEL HOME WORK: #1

Course No. CSE 262 Course Title: Computer System

Architecture
School: LHAT-A
Department: CSE/IT

Name of the faculty member: Harjeet Kaur

Class: BTech (Hons) CSE/IT Term: 4 Section:

A1901 Batch: 2009

Max. Marks: HW:5 Test: 15 DOA: 25/1/2011

DOS: 1/2/2011

Part A

Q1. Enable bit plays an important role in decoder expansions. How is this
justified in designing
(a) 3X8 line decoder using two 2X4 line decoders

A decoder is used to determine the ordinal value of a particular bit pattern. In other
words, it decodes the number represented by a stream of binary digits.

The 3-to-8 line decoder is so named because it takes three input signals and converts
them into the correct output signal, choosing from the eight possible values.

If the number is given to the decoder as [A2, A1, A0] (that is, with the most
significant bit being A2), then the decoder will set the AND gate coded with that
binary number to on.

If the decoder is fed 101 (the binary for 5), the decoder performs the following tasks:
A0 is on, so all AND gates with the negation of A0 cannot turn on. This leaves gates
D1, D3, D5, and D7 as possible output gates. A1 is off, so all gates without the
negation of A1 cannot turn on. (This turns off D3 and D7.) A2 is on, and the only gate
that could be turned on is therefore D5 (since D1 could only be activated if A2 were
off).

The reason that the decoder can convert numbers from binary to discrete values is that
it brute-forces the result. That is, it tests for every possible combination of bits.
Although this allows the system to "know" the bit patterns that make up different
numbers, in effect, it can be somewhat slow because every possible combination has
to be tried. The only thing which prevents this circuit from being horrifically slow is
that all of the tests are run in parallel, so the length of time that the circuit takes to
complete is no more than the amount of time it takes current to flow through a NOT
gate and an AND gate (the longest path from the inputs to the outputs).

The enable line is present so that then entire subsystem can be turned off (all gates set
to false) if so desired. This becomes important later (see below).

The truth table for this circuit is below

Often, it is easier to use multiple decoders together, rather than build them yourself. It
is much cheaper to buy chips with two 2x4 decoders on them than to buy chips with
AND gates and NOT gates on them. The picture to the right demonstrates how to
connect two 2x4 decoders together to create a 3x8 decoder.

3x4 decoder using 2x4 decoder

 (b)5X32 line decoder using four 3X8 and one 2X4 line decoders

Q2. How can a JK flip flop be converted to

(a) T Flip Flop

a JK flip-flop with its J and K inputs connected to a logic 1 will operate as a T flip-
flop. Converting an RS flip-flop involves a bit more, as shown to the right.
However, the simple feedback connections shown will ensure that the S and R
inputs will always tell the flip-flop to change state at each clock pulse.

Converting a D flip-flop to T operation is quite similar; the Q' output is connected

back to the D input.

(b)D Flip Flop

to convert an RS flip-flop to D operation. This change eliminates the possibility of

an illegal input condition, which could otherwise cause spurious results in some
applications.

A much more complicated circuit, shown to the right, is the gating structure needed
to convert a D flip-flop to JK operation. This circuit implements the logical truth
that D = JQ' + K'Q.

This input circuit is actually used more frequently than you might think. CMOS
flip-flops are typically constructed as D types because of the nature of their internal
operation. Commercial CMOS JK flip-flops, such as the 4013, then add this circuit
to the input in order to get JK operation.

This approach eliminates the internal latching effect, or "ones catching," that occurs
with the general JK master-slave flip-flop. The J and K input signals must be
present at the time the clock signal falls to logic 0, in order to affect the new output
state.

In this case, we do need to add an inverter to supply the R input signal, as shown to
the left.

Q3. Identify at least two application areas (discuss their roles also) for
(a) Encoder/Decoder

Encoder and decoder applications

The radio frequency spectrum is filled with noise and other signals, especially
those frequencies where unlicensed transmitter operation under FCC part 15
rules is allowed. When using a wireless remote control system it is desirable
to have a way of filtering out or ignoring those unwanted signals to prevent
false data from being received.

A simple way to accomplish this is to use an encoder IC at the transmitter and

a decoder IC at the receiver. The encoder generates serial codes that are
automatically sent three times and must be received at least twice before data
is accepted as valid by the decoder circuit.

In the early days of "radio control", before these coding ICs were available,
radio controlled garage doors sometimes opened themselves when they
received transmissions from a plane passing overhead or a two-way radio
operating in the area. Encoding and decoding is now used in most wireless
control systems to prevent this type of interference.

A GL-104 IC in an 18 pin DIP package available from Glolab can be used as

an either an encoder or decoder just by changing the connection to one pin.
These devices also offer more flexibility than the usual encoder and decoder
ICs. One GL-104 that is configured as an encoder is needed for each
transmitter and one that is configured as a decoder for each receiver. You will
also need one 4 MHz ceramic resonator (CR) and one voltage detector/reset
(VDR) device for use with each GL-104. The GL-104 will be used in the
following application examples. These devices have four data channels.

(b)Multiplexers/De multiplexer
Applications of Multiplexer circuits:

These circuits use mostly find in numerous and varied applications in digital
systems of all types such as data selection, data routing, operation
sequencing, parallel-to-serial conversion, waveform generation and
logic-function generation.

Application of Demultiplexer Circuits:

They find use in Clock demultiplexer,Security monitoring

system,Synchronous data transmission system

(c) Flip Flops

Racer, abinary storage registor , transition pulse generator ,stable oscillator etc are
application of flip flops….

Q4. Discuss the basic logic behind counters i.e. how will you obtain 1000(8)
from 0111(7)? How will you implement the same? How many flip flops will be
complemented in a 10 bit binary counter to reach the next count after
1001100111?
Q5. What will happen if buffer gate in the clock input of the register is
removed? What is the role of clear and load signals in designing register with
parallel load?

Part B

Q6. The content of a four bit register is initially 1101. The register is shifted
six times to the right with the serial input being 101101. What is the content
of the register after each shift?

Q7. Perform the arithmetic operations (+42) + (-13) and (-42) – (-13) in
binary using signed 2’s complement representation for negative number.

Q8. Represent the number (+46.5)10 as a floating point binary number with
24 bits. The normalized fraction mantissa has 16 bits and exponent has 8
bits.