Speeding PrimeTime's reports analysis.

Yossi Rindner
Ohad Meshulam

ASICServe ltd.
Hamanofim st. 11
Herzlia 46120
Israel

yossir@asicserve.com
ohadm@asicserve.com
www.asicserve.com

ABSTRACT

Taping out a chip requires substantial usage of PrimeTime which in turn generates very large
amount of reports. Analyzing these reports is error prune, time consuming and resulting in
schedule bottle neck. This paper describes an efficient and systematic method of managing and
speeding PrimeTime's reports analysis.
 Table of Contents

1. Introduction – STA (Static Timing Analysis) loop. ............................................................. 4

2. STA panel – Top level view. ............................................................................................... 6
2.1 STA panel header. ................................................................................................................ 7
2.2 STA panel none-linked columns. ......................................................................................... 7
2.3 STA panel linked columns. .................................................................................................. 7
3. STA panel – Detailed description. ....................................................................................... 9
3.1 Clock groups – Column A. ................................................................................................ 10
3.2 # Violating endpoints – Column B. ................................................................................... 10
3.3 WNS – Column C. ............................................................................................................. 10
3.4 Slack only – Column D. ..................................................................................................... 11
3.5 Intraclk – Column E. .......................................................................................................... 13
3.6 Toclk – Column F. ............................................................................................................. 14
3.7 Intraclk / Toclk columns inferred information. .................................................................. 15
3.8 Globals – Column G. ......................................................................................................... 16
3.8.1 Clocks. ............................................................................................................................ 16
3.8.2 Inputs. ............................................................................................................................. 18
3.8.3 Outputs. .......................................................................................................................... 20
3.8.4 Case analysis. ................................................................................................................. 22
3.8.5 Exceptions considered. ................................................................................................... 23
3.8.6 Exceptions ignored. ........................................................................................................ 24
3.8.7 Check timing. ................................................................................................................. 25
3.8.8 Specifics. ........................................................................................................................ 26
3.8.9 Cross clocks.................................................................................................................... 27
3.8.10 Regs per clock. ............................................................................................................... 28
3.9 Non timing related reports. ................................................................................................ 29
3.9.1 Deep area. ....................................................................................................................... 29
3.9.2 Memories. ....................................................................................................................... 30
3.9.3 Black boxes. ................................................................................................................... 31
3.9.4 Hierarchy. ....................................................................................................................... 32
3.9.5 Multi Modes (MM) data management. .......................................................................... 33
3.9.6 Multi Modes Multi Corners (MMMC) data management. ............................................ 34
4. Summary. ........................................................................................................................... 35
5. Future developments. ......................................................................................................... 35
5.1 SDC Interface. .................................................................................................................... 35
5.2 PrimeTime IPO. ................................................................................................................. 35
6. Acknowledgements. ........................................................................................................... 35
7. References. ......................................................................................................................... 35

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 Table of Figures

Figure 1 – STA loop ....................................................................................................................... 4

Figure 2 – STA panel. ..................................................................................................................... 6
Figure 3 – STA panel, max and min timing, with marked differences. .................................. 9
Figure 4 – Links from STA panel to 'Slack only' endpoints. ........................................................ 11
Figure 5 – Links from 'Slack only' specific endpoint to its verbose description. .......................... 12
Figure 6 – Links from Intraclk to short representation and to verbose description. ..................... 13
Figure 7 – Links from Toclk to to short representation and to verbose description. .................... 14
Figure 8 – Intraclk / Toclk inferred information. .......................................................................... 15
Figure 9 – Link from STA panel to comprehensive clock report. ................................................ 16
Figure 10 – "Genealogically" related clocks format. .................................................................... 17
Figure 11 – Inputs definition with max and min waveforms. ....................................................... 18
Figure 12 – Inputs verbose report and max waveforms. ............................................................... 19
Figure 13 – Inputs verbose report and min waveforms................................................................. 19
Figure 14 – Outputs definition with max and min waveforms. .................................................... 20
Figure 15 – Outputs verbose report and max waveforms. ............................................................ 21
Figure 16 – Outputs verbose report and min waveforms. ............................................................. 21
Figure 17 – 'Case analysis' related links........................................................................................ 22
Figure 18 – 'Exceptions considered', 1st level representation with all related links. ..................... 23
Figure 19 – 'Exceptions considered', 2nd level representation....................................................... 24
Figure 20 – 'Check timing' with all related links. ......................................................................... 25
Figure 21 – Specifics with related links. ....................................................................................... 26
Figure 22 – 'Cross clocks' with related links. ................................................................................ 27
Figure 23 – 'Regs per clock' with related links. ............................................................................ 28
Figure 24 – 'Deep area' with related links. .................................................................................... 29
Figure 25 – Memories with related links. ..................................................................................... 30
Figure 26 – 'Black boxes' with related links. ................................................................................ 31
Figure 27 – Hierarchy with related links....................................................................................... 32
Figure 28 – MM (Multi Mode) panel............................................................................................ 33
Figure 29 – MMMC (Multi Mode Multi Corner) panel. .............................................................. 34

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1. Introduction – STA (Static Timing Analysis) loop.
In a typical ASIC design flow, the following loop is inevitable:

Receiving netlist + SDF (SPEF) from

layout.

Running PrimeTime and generating reports.

(…many reports…)

Analyzing reports

RTL modification ECOed netlist. Fixed timing

and re-synthesis. constraints.

Figure 1 – STA loop

One of the most time consuming parts is "Analyzing reports" stage as:

• Many reports need to be analyzed.

• Correct course of actions needs to be decided upon.

Most of STA sessions require reviewing reports related to the following topics:

• Clocks definitions.
• Check timing.
• Case analysis.
• Inter clocks slacks.
• Intra clocks slacks.
• IO definitions.
• IO slack.
• Asynchronous default slacks.
• Clock gating slacks.
• Exceptions considered.
• Exceptions ignored.
• Cross clocks paths.
• Specific paths.

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Following actions will affect many of the mentioned reports:

• Fixed timing constraints.

• ECOed netlist.
• RTL modification and re-synthesis.

Since the reports are closely related, any of the above actions will affect many of the reports,
which in turn will result in reviewing the reports all over again.

Being able to access the reports in an efficient way, while maintaining effective links between all
of them is crucial for:

• Analysis of timing violations.

• Conclusions for correct course of actions.

In an effort of having PrimeTime's reports manageable and easily accessed, a comprehensive

STA platform was designed and implemented.

For implementation of such platform, Microsoft XL and VBA programming language were
chosen as they have many built in features that made such choice only natural, as follows:

• Tabulation.
• Links.
• Sorting.
• Summation.
• Graphs.

Following paragraphs describe the rules and guidelines based on which such STA platform is
designed.
Implementation of the STA platform is not described as it is out-of-scope for this paper.

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2. STA panel – Top level view.
The main purpose of any STA run is to see what and where are the timing violations.
To receive this big picture, one needs to see all clock groups.
Below figure depicts XL STA panel which provides such top level view.
This STA panel has the following three main sections:

• Header
• None-linked columns (A,B,C)
• Linked columns (D,E,F,G)

Figure 2 – STA panel.

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2.1 STA panel header.
To monitor progress of STA sessions, the following items were selected to appear in STA panel's
header:
• Project name.
• Revision of STA session, each STA session is tagged with revision number.
• STA analysis mode, meaningful name that represent chip's unique mission mode.
Typically there are several mission modes which are additional factors that increase
the amount of reports being generated.
• Delay type, max (setup) or min (hold).
• PVT (Process, Voltage, Temperature) corner.

2.2 STA panel none-linked columns.

Following columns depicts the big picture of all violations.

• Column A - All clock groups.

• Column B - Amount of violating endpoints per each clock group.
• Column C - WNS (Worst Negative Slack) in each clock group.

2.3 STA panel linked columns.

To maintain fast access to all reports, the following links are integrated in the STA panel
(activated by double-click):

• Column D - Slack only violations for each clock group.

• Column E - Intra clock violations in each clock group.
• Column F - WNS from any clock to each clock group, inclusive.

Since analyzing violations requires, in most cases, reviewing of STA definitions, thus following
links to all definitions are integrated into STA panel:

• Column G:
o Clocks.
o Inputs.
o Outputs.
o Case analysis.
o Exceptions considered.
o Exceptions ignored.

PrimeTime's warnings are of most importance to realize that each STA session has all relevant
timing constraints correctly defined, for that reason access to check_timing information is
integrated into STA panel:

• Column G:
o Check timing.

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Additional flexibility was built into the STA panel to allow analysis of special timing reports:

• Column G:
o Specifics.
o Cross clocks.
o Regs per clock.

To complete the full STA picture, selected, non-timing related reports were added:

• Column G:
o Deep area.
o Memories.
o Black boxes.
o Hierarchy.

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3. STA panel – Detailed description.
In following paragraphs each column of the STA panel will be described in details and
accompanied by examples. Throughout this document max timing STA panel will be used as
reference. Anywhere a difference between max and min timing STA panels exists, both cases are
covered.
Following two snapshots depict the differences between max and min timing STA panels:

• Timing type.
• Asynchronous default.
• Clock gating default.

Figure 3 – STA panel, max and min timing, with marked differences.

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3.1 Clock groups – Column A.
Column A includes all clock groups as defined per STA session and has the following three sub-
groups:

• Async defaults:
o Recovery – setup analysis on asynchronous set/reset pins of flops.
o Removal – hold analysis on asynchronous set/reset pins of flops.

• Clock gating:
o Max – setup analysis between a clock and its enable signal.
o Min – hold analysis between a clock and its enable signal.

• Any other clock, either master or generated.

3.2 # Violating endpoints – Column B.

Column B shows total of violating endpoints per clock group mentioned in paragraph 3.1.

3.3 WNS – Column C.

Column C shows the worst negative slack in each clock group mentioned in paragraph 3.1.
WNS slack is relative to 0.

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3.4 Slack only – Column D.
Slack only column allows access to short presentation of all violating endpoints per each clock
group.
Special links are embedded into each and every 'Slack only' XL cells and redirect to proper
location in the short representation of each violating endpoint per clock group.
Following set of figures depicts chain-of-links implemented for quick access and analysis of
timing violations.

Figure 4 – Links from STA panel to 'Slack only' endpoints.

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Farther link from each endpoint XL cell to verbose report allows an efficient debug of specific
violation.

Figure 5 – Links from 'Slack only' specific endpoint to its verbose description.

Just in case that the nature of Start/End point clocks is "forgotten", a double click on any of the
highlighted clocks redirects to comprehensive report clock for "memory refreshment".

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3.5 Intraclk – Column E.
Intraclk column shows large amount (but not necessarily all) of violations which are internal to
each clock group.
Special links are embedded into each and every Intraclk XL cell and redirect to short format
representation of only Start/End points with their slack.
Double click on any of the Start/End points in the short format redirects to proper location in
verbose report.

Figure 6 – Links from Intraclk to short representation and to verbose description.

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3.6 Toclk – Column F.
Toclk column shows large amount (but not necessarily all) of WNS which begin at any clock and
end at specific clock group, inclusive.
Special links are embedded into each and every Toclk XL cell and redirect to short format
representation of only Start/End points with their slack.
Double click on any of the Start/End points in the short format redirects to proper location in
verbose report.

Figure 7 – Links from Toclk to to short representation and to verbose description.

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3.7 Intraclk / Toclk columns inferred information.
One of the reasons that Intraclk and Toclk columns were selected to be shown in the STA panel
is that very important information can be depicted quickly just from looking at both
simultaneously, as follows:
• Violation + Intraclk none-linked + Toclk linked:
o The violations are external to the clock group.
• Violation + Intraclk linked + Toclk linked:
o Some of the violations are internal to the clock group.
o There might be also violations which are external to the clock group.

Figure 8 – Intraclk / Toclk inferred information.

Intraclk violations have precedence over interclk, thus fixing the former will result in "clean"
Intraclk column and will allow focusing on Toclk violations which are coming from different
clocks and thus most likely can be handled by modifying timing constraints rather than
modifying the RTL or netlist.

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3.8 Globals – Column G.
Column G is dedicated to access all timing definitions and all warnings that PrimeTime generates
while running STA.

3.8.1 Clocks.
PrimeTime's original report_clock includes two sections, 1st section with all clocks and 2nd
section with only generated clocks. A rather comprehensive presentation of such report would be
combined into a single section with related duty cycle and uncertainty parameters as shown in
figure below.

Figure 9 – Link from STA panel to comprehensive clock report.

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Since PrimeTime clock's report shows always all clocks, more effective usage of such clocks
information is when seeing only the "genealogically" related clocks, thus special feature is
integrated into the STA panel so double click on any clock shows just its masters:

Figure 10 – "Genealogically" related clocks format.

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3.8.2 Inputs.
Inputs analysis takes a special part in any STA as launching side of the timing path is explicitly defined.
Due to complexity of IO analysis a rather pictorial approach is desired and such feature is built into the
STA panel.
Once the 'Inputs' XL cell is double clicked, timing definition report pops and depicts the definition
summary per each input.
Followed double click on either max or min XL cells, corresponding waveform pops up with
representation of timing definition in context of launching clock which elaborates input definition
effectively.

Figure 11 – Inputs definition with max and min waveforms.

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To allow comprehensive observation on inputs definitions in context of internal sampling flops,
additional level of waveforms are added as follows.

Figure 12 – Inputs verbose report and max waveforms.

Figure 13 – Inputs verbose report and min waveforms.

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3.8.3 Outputs.
Outputs analysis takes a special part in any STA as capturing side of the timing path is explicitly defined.
Once the 'Outputs' XL cell is double clicked, timing definition report pops and depicts the definition
summary per each output.
Followed double click on either max or min XL cells, corresponding waveform pops up with
representation of timing definition in context of capturing clock which elaborates output definition
effectively.

Figure 14 – Outputs definition with max and min waveforms.

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To allow comprehensive observation on outputs definitions in context of internal driving flops, additional
level of waveforms are added as follows.

Figure 15 – Outputs verbose report and max waveforms.

Figure 16 – Outputs verbose report and min waveforms.

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3.8.4 Case analysis.
'Case analysis' indicates all signals that are forced during specific STA session.
Typically, setting case analysis distinguishes different mission modes and such information is very important for any
STA analysis.

Figure 17 – 'Case analysis' related links.

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3.8.5 Exceptions considered.
'Exceptions considered' are those exceptions that PrimeTime honores. This is very important
source of information to verify that PrimeTime indeed "understood" the exceptions placed. Main
issue with the exceptions is the size of the start, through and endpoints lists that are accumulated
during STA session which makes them very difficult to manage and review. Special method was
implemented in STA panel to overcome this obstacle. Double click on 'Exceptions considered'
XL cell opens new XL in which all exceptions honored by PrimeTime shows while the lists are
shown in short format, i.e. only the 1st element in each list is shown.

Figure 18 – 'Exceptions considered', 1st level representation with all related links.

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Double click on any "…" opens dedicated XL which shows specific list in expanded format.

Figure 19 – 'Exceptions considered', 2nd level representation.

3.8.6 Exceptions ignored.

'Exceptions ignored' are those exceptions that are ignored by PrimeTime for several reasons and
are important to analyze as they indicate misplaced constraints or even design bugs. Similar
access method is used as in 'Exceptions considered'.

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3.8.7 Check timing.
One of the most important warnings sources while running PrimeTime is the check_timing
report, reviewing this report carefully will result in many STA issues that can be uncovered.
Additional pull-down menu is integrated inside the check_timing report for a quick access to all
possible warnings.

Figure 20 – 'Check timing' with all related links.

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3.8.8 Specifics.
In many cases, PrimeTime's original reports are not enough to get all timing information of a
chip, as different timing paths need to be analyzes specifically.
For this purpose, dedicated links were embedded into the STA panel to support such need, as
follows:
• 1st link is from 'Specifics' XL cell to list of reports that are specifically generated.
• 2nd link is from one of the selected reports to a short format which includes at least one of
the following:
o Startpoint.
o Several through points.
o Endpoint.
rd
• 3 link redirects to verbose representation of selected timing point.

Figure 21 – Specifics with related links.

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3.8.9 Cross clocks.
Asynchronous paths are very important for analysis as identifying them in early stages of the
project might result in improved timing constraints which yields smaller silicon. Following three
steps allow access to all async paths in the chip.

Figure 22 – 'Cross clocks' with related links.

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3.8.10 Regs per clock.
Detailed full path of each flop, latch and memory in every clock domain is accessed in two
stages. In 1st stage, list of files for each clock domain are presented. In 2nd stage each file can be
access and detail hierarchies are shown. At the bottom of each file total number of registers per
clock domain is shown.

Figure 23 – 'Regs per clock' with related links.

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3.9 Non timing related reports.
Remaining paragraphs are non-timing related but were included in the STA panel as they are
reviewed quite often during STA analysis.

3.9.1 Deep area.

Detailed list of each hierarchical instance and its area size, including of all sub-hierarchies for
each instance, is accessed via 'Deep area' XL cell. At the bottom of this file, total area number is
presented.

Figure 24 – 'Deep area' with related links.

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3.9.2 Memories.
Detailed list of each memory instance and related reference is accessed via Memories XL cell.

Figure 25 – Memories with related links.

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3.9.3 Black boxes.
Detailed list of each empty instance is accessed via 'Black boxes' XL cell.

Figure 26 – 'Black boxes' with related links.

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3.9.4 Hierarchy.
Detailed list of each hierarchical instance is accessed via Hierarchy XL cell.

Figure 27 – Hierarchy with related links.

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3.9.5 Multi Modes (MM) data management.
Once the data base for a single mode, single corner is established a higher level statistics can be
extracted.
Below XL shows full chip MM (Multi Mode) table for pre-layout analysis.
Each Single Mode Single Corner can be accessed by a double clock from WNS max or WNS
min cells.

Figure 28 – MM (Multi Mode) panel.

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3.9.6 Multi Modes Multi Corners (MMMC) data management.
Once the data base for a single mode, single corner is established a higher level statistics can be
extracted.
Below XL shows full chip MMMC (Multi Mode Multi Corner) table for post-layout analysis.
Each SMSC (Single Mode Single Corner) sheet can be accessed by double clock on: wc,tc, bc…

Figure 29 – MMMC (Multi Mode Multi Corner) panel.

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4. Summary.
The method described in this paper was developed over the last 2 years.
The method proved as very successful while being used to TOed 2 chips in the last 8 months.
In the chip that was more complicated from timing constraints/reports point of view, saving was
more significant as more "navigation" between the reports was required if such method wouldn't
exist.
Time spent to analyze PrimeTime reports was slashed by more than 50%.
Overall project schedule was reduced by more than 10%.

5. Future developments.
5.1 SDC Interface.
In case of large timing exceptions, it's not possible to see them all via PrimeTime reports and the best
method is to check the SDC, having link between the Excel data base and SDC files would be of
added value.
The method described in this paper is planned to be extended into interface between PrimeTime
reports and SDC.

5.2 PrimeTime IPO.

PrimeTime is capable of performing local IPOs to close timing. Having the capability of generating
automatic set of PrimeTime IPO commands span over several modes and corners based on the Excel
data base will save timing during TO.
The method described in this paper is planned to be extended and allow such interface to PrimeTime.

6. Acknowledgements.

My first acknowledgement goes to Synopsys Israeli office, mainly to Zohar Zolty and Moshe
Ashkenazi, for constructive feedbacks during preparation of this paper.

My second acknowledgement goes to following persons:

1. Steve Golson
2. Paul Zimmer

I used their SNUG papers as masters and resource of great examples on how to write SNUG
paper.

My last, but not least, acknowledgement goes to my customers and competitors

(anonymous…☺) who've been using the methods described in this paper and provided me with a
great encouragement to proceed and reach higher levels of product maturity every time.

7. References.
SOLD (Synopsys On Line Documentation)

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