Design and development of a

3GPP-LTE Testbed (Transmitter End)

A progress report submitted for partial evaluation of the requirements for the
degree of

Bachelor of Technology (Honors)

in

Electronics & Electrical Communication Engineering

by

Praveen Kumar Sharma

07EC1045

supervised by

Dr. Indrajit Chakrabarti

co-supervised by

Dr. Suvra Sekhar Das

Department of Electronics & Electrical Communication Engineering

Indian Institute of Technology, Kharagpur
November, 2010

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Department of Electronics & Electrical Communication Engineering
Indian Institute of Technology, Kharagpur

Certificate
This is to certify that the project entitled “Design and development of a 3GPP-
LTE Testbed on FPGA” being carried out by Praveen Kumar Sharma (07EC1045) in
the Department of Electronics & Electrical Communication Engineering is a bonafide
record of research work performed by him under my supervision and guidance.

Dr. Indrajit Chakrabarti

Associate Professor
Department of Electronics & Electrical Communication Engineering
IIT Kharagpur
November 2010

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Abstract
With growing exchange of data between today’s consumers and the growing need of mo-
bility, the bandwidth requirements of users has increased exponentially in the past few
years. Mobile service providers have been coming up with various solutions to increase
the data rates. 3GPP Long Term Evolution (LTE), is the latest standard in the mo-
bile network technology tree that produced the GSM/EDGE (2G) and UMTS/HSxPA
(3G) network technologies. It is the contender of the IEEE WiMAX standard for 4G
services. In this project we have aimed to build a transceiver with the specifications
listed by the LTE standard, and investigate the practical challenges encountered while
doing so. Since this project is being jointly done by two students, we have shared the
roles. I have concentrated on the designing of the transmitter end.

List of Figures
1. Transceiver block diagram.
2. Constellation diagram for QPSK.
3. Block diagram for QPSK Mapper.
4. Constellation diagram for 16-QAM.
5. Block diagram for 16-QAM Mapper.
6. Constellation diagram for 64-QAM.
7. Block diagram for 64-QAM Mapper.
8. Waveform for QPSK mapper.
9. Waveform for 16-QAM mapper.
10. Waveform for 64-QAM mapper.

List of Tables
1. Specifications of LTE Standard.
2. Mapping table for QPSK.
3. Mapping table for 16-QAM.
4. Mapping table for 64-QAM.

Abbreviations used
3GPP - 3rd Generation Partnership Project
LTE - Long Term Evolution
OFDMA - Orthogonal Frequency Division Multiple Access
OFDM – Orthogonal Frequency Division Multiplexing
SCFDMA - Single Carrier Frequency Division Multiple Access

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Contents
i. Abstract
ii. List of Figures
iii. List of Tables
iv. Abbreviations used
1. Introduction
2. LTE
3. Work Time-line
4. Symbol Mapper
5. Observations and Results
6. Conclusion
7. Bibliography

1 Introduction
LTE is the natural evolution of 3GPP GSM and WCDMA networks. It is also an
evolution candidate for 3GPP2 CDMA networks. It is a new paradigm in access, with
a new modulation technique, OFDM (Orthogonal Frequency Division Multiplex), and
antenna technology, MIMO (Multiple Input Multiple Output).
OFDM splits the information into multiple narrow-band sub-carriers, allowing each
of them to carry a portion of the information at a lower bit rate, which makes OFDM
a very robust modulation, particularly in multipath scenarios, like urban areas.
MIMO technology creates several spatial paths on the air interface between the
network and the subscriber; so these paths can carry the same or different streams of
information, allows an increase in either the coverage (due to higher Signal to Noise
Ratio (SNR) at the receiver) or the user data throughput.
LTE, combining OFDM and MIMO, provides a much greater spectral efficiency
than the most advanced 3G networks, reducing the cost per bit and allowing better
economics for operators and end users.
Since we are using a bottom-up approach towards designing the modem, we attempt
to design a SISO system first, and then extending it to MIMO systems.

2 LTE
The key highlights about 3GPP LTE are listed below:

• Reduced delays for both connection establishment and transmission latency.

• Increased user data rates.

• Increased cell-edge bitrate (uniformity of service provision).

• Reduced cost per bit (improved spectral efficiency).

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 • Greater flexibility of spectrum usage, in both new and pre-existing bands.

• Simplified Network Architecture.

• Seamless mobility, for different radio access technologies as well.

• Reasonable power consumption at the mobile terminal.

Table 1 lists the specific requirements of various parameters.

Table 1: Specifications of LTE Standard.

3 Work Time-line
The final transceiver to be design is shown in figure 1.

Figure 1: Transceiver block diagram (courtesy Fairchild Semiconductors) .

To modularize the design on the modem, we have decided to split the development
into multiple stages.

1. Symbol Mapper/De-mappers

2. ITTF/FFT Blocks

3. Cyclic Prefix addition/removal

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 4. Channel estimation

5. Channel equalization

6. Time synchronization

7. Carrier synchronization

8. Encoder and Interleaver introduction

9. Clock synchronization

4 Symbol Mapper
The first stage was development of the symbol mapper. As the LTE specification
requires a variable data rate and accordingly the use of the three modulations schemes
namely: QPSK, 16QAM and 64QAM.
The constellation points are mapped into 16bit I and Q values. The accepted
standard is 3+13 notation for fixed point representation. The constellation points
normalized in the mapping stage itself.
Since the LTE specifications only list out the requirements and not the implemen-
tation details, we have to design our own mapping algorithms. Here we discuss the
algorithms and architectures employed in our implementation.
The convention followed is

• Input Stream consists of the binary bitstream

• Output Stream is a dual channel I and Q stream, which are 16 bit and are
generated serially. ( LSB first)

4.1 QPSK
QPSK, which stands for Quadrature Phase Shift Keying, is a type of phase modulation
algorithm where two incoming bits are mapped to one constellation point, creating 4
possible points(states). These four states also refer to four phases wherein a particular
carrier is sent to QPSK. These states consist of 45, 135, 225, and 315 degrees.
Table 2 shows the mapping table for QPSK.

Table 2: Mapping Table for QPSK.

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Figure 2 shows the constellation diagram of QPSK.

Figure 2: Constellation Diagram for QPSK.

Mapping Algorithm

QPSK Mapper:

• Inputs to module : incoming bit stream, a clock at which the output is expected.

• Outputs from module : Dual channel serialized 16 bit streams for I-channel and
Q-channel (LSB sent out first)

• Idea used for mapping:

– I-channel and Q-channel values differ only in the first bit for the 4 different
cases.
– The MSB of the two bits decides the sign for I-channel and the LSB decides
the sign of Q-channel.
– At the output clock, a counter counts from 0 to 15 and depending upon the
counter value, the corresponding I-channel and Q-channel bits are sent out
serially.
– For first 15 clock cycles, the last 15 bits of the value corresponding to
complex constellation are hardwired with LSB sent out first. At the 15th
clock, the incoming value is retained.
– In 16th clock cycle, the I-channel outputs the incoming bit stream and the
Q channel outputs the temporary value latched at the previous clock.
– The output clock has to be 8 times faster than the rate at which the input
bit stream is coming and on hardware this is taken care of by proper clock
division and routing.

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 Figure 3 shows the block diagram for the architecture of the mapper.

Figure 3: Block Diagram of QPSK Mapper.

4.2 16-QAM
16-QAM, is a type of phase modulation and amplitude modulation algorithm where
four incoming bits are mapped to one constellation point, creating 16 possible points(states).
These 16 states which map in a rectangular structure determine the amplitude and
phase of the in-phase and quadrature phase components of the carrier.
Table 3 shows the mapping table for 16-QAM.

Table 3: Mapping Table for 16-QAM.

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Figure 4 shows the constellation diagram of 16-QAM.

Figure 4: Constellation Diagram for 16-QAM.

Interpretation of bits in 16-QAM

• The four bits read from left to right, signify the following:

– MSB (bit 3) decides sign of I-channel.

– MSB-1 (bit2) decides sign of Q-channel.
– The next bit denotes the magnitude of the I channel, 0 stands for 1, while
1 stands for 3
– The final bit denotes the magnitude of the Q channel, 0 stands for 1, while
1 stands for 3

Mapping Algorithm

16-QAM Mapper:

• Inputs to module : serial bit-stream, clock at which output is needed (a related

clock value is used for clocking the input stream)

• Outputs from module : Dual channel serialized 16 bit streams for I-channel and
Q-channel (LSB sent out first)

• Idea used for mapping:

– The incoming stream is stored in a 4 bit shift register. This buffer is fed to
mapper module which makes use of the above given interpretation.
– The 4 bit pattern is then changed into corresponding stored fixed point
representation value for both I-channel and Q-channel.
– The 16 bit values are serialized and sent out.

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 Figure 5 shows the block diagram for the architecture of the mapper.

Figure 5: Block Diagram of 16-QAM Mapper.

4.3 64-QAM
64-QAM, is a type of phase modulation and amplitude modulation algorithm where six
incoming bits are mapped to one constellation point, creating 64 possible points(states).
These 64 states which map in a rectangular structure determine the amplitude and
phase of the in-phase and quadrature phase components of the carrier.
Table 4 shows the mapping table for 64-QAM.

Table 4: Mapping Table for 64-QAM.

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Figure 6 shows the constellation diagram of 64-QAM.

Figure 6: Constellation Diagram for 64-QAM.

Interpretation of bits in 64-QAM

• The six bits read from left to right, signify the following:

– MSB (bit 5) decides sign of I-channel.

– MSB-1 (bit 4) decides sign of Q-channel.
– For next four bits, the following pattern of bits gives the following corre-
sponding coefficients
∗ 00 -¿ 3
∗ 01 -¿ 1
∗ 10 -¿5
∗ 11 -¿7
– In I-channel the coefficient magnitude comes from sequence formed by using
bits 3 and 1.
– In Q-channel the coefficient magnitude comes from sequence formed by
using bits 2 and 0.

Mapping Algorithm

64-QAM Mapper:

• Inputs to module : serial bit-stream, clock at which output is needed (a related

clock value is used for clocking the input stream)

• Outputs from module : Dual channel serialized 16 bit streams for I-channel and
Q-channel (LSB sent out first)

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 • Idea used for mapping:

– The incoming stream is stored in a 6 bit shift register. This buffer is fed to
mapper module which exploits the above given features and deduces a 4 bit
pattern for I-channel and Q-channel.
– The 4 bit pattern is then changed into corresponding stored fixed point
representation value for both I-channel and Q-channel.
– The 16 bit values are serialized and sent out.

Figure 7 shows the block diagram for the architecture of the mapper.

Figure 7: Block Diagram of 64-QAM Mapper.

5 Observations and Results

Test-benches were written for the mappers to check their working. The statistics for
the mappers are.

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• QPSK mapper

– First two bits aquired at first instant.

– First output from 32nd time unit (16 clocks)

Figure 8: Waveform of QPSK mapper.

• 16-QAM Mapper

– First complete 4bit value latched at 32nd time unit (16th clock)
– First output from 64th time unit (32nd clock)

Figure 9: Waveform of 16-QAM mapper.

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 • 64-QAM Mapper

– First complete bit input buffered in 192 units

– First correct output from 384 units

Figure 10: Waveform of 64-QAM mapper.

6 Conclusion and Future work

In the given project we have aimed to build an LTE-Testbed. We have started off by
implementing a simple OFDM transceiver first. At the heart of the transmitter lies the
symbol mapper. We have successfully implemented the three symbol mapper required
by the design and tested then for behavioral accuracy.
Xilinx test-beds have been develop to test the mapping algorithm and it was found
to be correct. However the noise performance due to the fixed point conversion needs
to be tested. A MATLAB test-bed for simulating a large number of bits is being
created, to generate BER plots for varying leles of noise introduced in the channel.
In the future we will be adding more blocks to the transceiver to achieve the tragets
specifications. If the target is not achieved then architectural level optimizations will
be performed.

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Bibliography
.
[1]: 3GPP TS 36.211 V9.1.0 (2010-03) by 3gpp.org.
[2]: LTE: The UMTS Long Term Evolution From Theory to Practice, by Stefansia
Sesia, Issam Toufik and Matthew Baker, John Wiley and Sons.
[3]: 3GPP LTE: Introducing Single-Carrier FDMA whitepaper by Agilent.
[4]: Overview of the 3GPP Long Term Evolution Physical Layer by Jim Zyren,
Whitepaper Freescale Semiconductors.
[5]: LTE for UMTS OFDMA and SCFDMA based radio access- H Holma and A
Toskala, John Wiley and Sons.

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