Dap-Final Report

DIGITAL AUDIO PROCESSOR USING AT89C51
1. BACKGROUND
This report presents an infrared (IR) remote-controlled digital audio processor.
It is based on a microcontroller and can be used with any NEC-compatible full function
IR remote-control. This audio processor has enhanced features and can be easily customized
to meet individual requirements as it is programmable.
Its main features are:
1. Full remote control using any NEC-compatible IR remote control handset.
2. Provision for four stereo input channels and one stereo output.
3. Individual gain control for each input channel to handle different sources.
4. Bass, midrange, treble, mute and attenuation control.
5. 80-step control for volume and 15-step control for bass, midrange and treble
6. Settings displayed on two 7-segment light-emitting diode (LED) displays and eight
individual LEDs.
7. Stereo VU level indication on 10-LED bar display.
8. Full-function keys on-board for audio amplifier control.
9. All settings stored on the EEPROM.
10. Standby mode for amplifier power control.
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2. MICROCONTROLLER
2.1 Definition of A Microcontroller:
Microcontroller, as the name suggests, are small controllers. They are like single chip computers
that are often embedded into other systems to function as processing/controlling unit. For
example, the remote control you are using probably has microcontrollers inside that do decoding
and other controlling functions. They are also used in automobiles, washing machines,
microwave ovens, toys ... etc, where automation is needed.
The key features of microcontrollers include:
 High Integration of Functionality

 Microcontrollers sometimes are called single-chip computers because they have on-chip
memory and I/O circuitry and other circuitries that enable them to function as small
standalone computers without other supporting circuitry.
 Field Programmability, Flexibility
 Microcontrollers often use EEPROM or EPROM as their storage device to allow field
programmability so they are flexible to use. Once the program is tested to be correct then
large quantities of microcontrollers can be programmed to be used in embedded systems.
 Easy to Use
Assembly language is often used in microcontrollers and since they usually follow RISC
architecture, the instruction set is small. The development package of microcontrollers
often includes an assembler, a simulator, a programmer to "burn" the chip and a
demonstration board. Some packages include a high level language compiler such as a C
compiler and more sophisticated libraries.
Most microcontrollers will also combine other devices such as:
 A Timer module to allow the microcontroller to perform tasks for certain time periods.
 A serial I/O port to allow data to flow between the microcontroller and other devices such
as a PC or another microcontroller.
 An ADC to allow the microcontroller to accept analogue input data for processing.
The heart of the microcontroller is the CPU core. In the past this has traditionally been based on
an 8-bit microprocessor unit.
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Figure 2.1: Showing a typical microcontroller device and its different subunits
Fig 2.2 Block Diagram of Microcontroller
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2.2 Pin Description:
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order address/data bus during accesses
to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives
the code bytes during Flash programming, and outputs the code bytes during program
verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order
address bytes during Flash programming and verification.
Port 2
low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external data memory
that uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @
RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-
order address bits and some control signals during Flash programming and verification.
Port 3
low will source current (IIL) because of the pull-ups. Port 3 also receives some control signals for
Flash programming and verification. Port 3 also serves the functions of various special features of
the AT89C51 as listed below:
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Table 1
Table 1:Port 3 Alternate Functions
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to
external memory. This pin is also the program pulse input (PROG) during Flash programming. In
normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes.
PSEN
Program Store Enable is the read strobe to external program memory. When the AT89C51 is
executing code from external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code
from external program memory locations starting at 0000H up to FFFFH. Note, however, that if
lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC
for internal program executions. This pin also receives the 12-volt programming enable voltage
(VPP) during Flash programming, for parts that require 12-volt VPP.
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XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
2.3 Microcontrollers versus Microprocessors:

Microcontroller differs from a microprocessor in many ways. First and the most important is its
functionality. In order for a microprocessor to be used, other components such as memory, or
components for receiving and sending data must be added to it. In short that means that
microprocessor is the very heart of the computer. On the other hand, microcontroller is designed
to be all of that in one. No other external components are needed for its application because all
necessary peripherals are already built into it. Thus, we save the time and space needed to
construct devices.
2.4 Memory unit:

Memory is part of the microcontroller whose function is to store data.
The easiest way to explain it is to describe it as one big closet with lots of drawers. If we suppose
that we marked the drawers in such a way that they can not be confused, any of their contents will
then be easily accessible. It is enough to know the designation of the drawer and so its contents
will be known to us for sure.
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Figure2.2: Simplified model of a memory unit
Memory components are exactly like that. For a certain input we get the contents of a certain
addressed memory location and that's all. Two new concepts are brought to us: addressing and
memory location. Memory consists of all memory locations, and addressing is nothing but
selecting one of them. This means that we need to select the desired memory location on one
hand, and on the other hand we need to wait for the contents of that location. Besides reading
from a memory location, memory must also provide for writing onto it. This is done by supplying
an additional line called control line. We will designate this line as R/W (read/write). Control line
is used in the following way: if r/w=1, reading is done, and if opposite is true then writing is done
on the memory location. Memory is the first element, and we need a few operation of our
microcontroller.
The amount of memory contained within a microcontroller varies between different

microcontrollers. Some may not even have any integrated memory (e.g. Hitachi 6503, now
discontinued). However, most modern microcontrollers will have integrated memory. The
memory will be divided up into ROM and RAM, with typically more ROM than RAM.
Typically, the amount of ROM type memory will vary between around 512 bytes and 4096 bytes,
although some 16 bit microcontrollers such as the Hitachi H8/3048 can have as much as 128
Kbytes of ROM type memory.
ROM type memory, as has already been mentioned, is used to store the program code. ROM
memory can be ROM (as in One Time Programmable memory), EPROM, or EEPROM.
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The amount of RAM memory is usually somewhat smaller, typically ranging between 25 bytes to
4 Kbytes.
RAM is used for data storage and stack management tasks. It is also used for register stacks (as
in the microchip PIC range of microcontrollers).
2.5 Central Processing Unit:

Let add 3 more memory locations to a specific block that will have a built in capability to
multiply, divide, subtract, and move its contents from one memory location onto another. The
part we just added in is called "central processing unit" (CPU). Its memory locations are called
registers.
Figure2.3: Simplified central processing unit with three registers
Registers are therefore memory locations whose role is to help with performing various
mathematical operations or any other operations with data wherever data can be found. Look at
the current situation. We have two independent entities (memory and CPU) which are
interconnected, and thus any exchange of data is hindered, as well as its functionality. If, for
example, we wish to add the contents of two memory locations and return the result again back to
memory, we would need a connection between memory and CPU. Simply stated, we must have
some "way" through data goes from one block to another.
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2.6 Bus:
That "way" is called "bus". Physically, it represents a group of 8, 16, or more wires.
There are two types of buses: address and data bus. The first one consists of as many lines as the
amount of memory we wish to address and the other one is as wide as data, in our case 8 bits or
the connection line. First one serves to transmit address from CPU memory, and the second to
connect all blocks inside the microcontroller.
Figure2.4: Showing connection between memory and central unit using buses
As far as functionality, the situation has improved, but a new problem has also appeared: we have
a unit that's capable of working by itself, but which does not have any contact with the outside
world, or with us! In order to remove this deficiency, let's add a block which contains several
memory locations whose one end is connected to the data bus, and the other has connection with
the output lines on the microcontroller which can be seen as pins on the electronic component.
2.7 Input-output unit:

Those locations we've just added are called "ports". There are several types of ports: input, output
or bidirectional ports. When working with ports, first of all it is necessary to choose which port
we need to work with, and then to send data to, or take it from the port.
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Figure2.5: Simplified input-output unit communicating with external world
When working with it the port acts like a memory location. Something is simply being written
into or read from it, and it could be noticed on the pins of the microcontroller.
2.8 Serial communication:

Beside stated above we've added to the already existing unit the possibility of communication
with an outside world. However, this way of communicating has its drawbacks. One of the basic
drawbacks is the number of lines which need to be used in order to transfer data. What if it is
being transferred to a distance of several kilometers? The number of lines times’ number of
kilometers doesn't promise the economy of the project. It leaves us having to reduce the number
of lines in such a way that we don't lessen its functionality. Suppose we are working with three
lines only, and that one line is used for sending data, other for receiving, and the third one is used
as a reference line for both the input and the output side. In order for this to work, we need to set
the rules of exchange of data. These rules are called protocol. Protocol is therefore defined in
advance so there wouldn't be any misunderstanding between the sides that are communicating
with each other. For example, if one man is speaking in French, and the other in English, it is
highly unlikely that they will quickly and effectively understand each other. Let's suppose we
have the following protocol. The logical unit "1" is set up on the transmitting line until transfer
begins. Once the transfer starts, we lower the transmission line to logical "0" for a period of time
(which we will designate as T), so the receiving side will know that it is receiving data, and so it
will activate its mechanism for reception. Let's go back now to the transmission side and start
putting logic zeros and ones onto the transmitter line in the order from a bit of the lowest value to
a bit of the highest value. Let each bit stay on line for a time period which is equal to T, and in
the end, or after the 8th bit, let us bring the logical unit "1" back on the line which will mark the
end of the transmission of one data. The protocol we've just described is called in professional
literature NRZ (Non-Return to Zero).
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Figure2.6: Serial unit sending data through three lines only
As we have separate lines for receiving and sending, it is possible to receive and send data (info.)
at the same time. So called full-duplex mode block which enables this way of communication is
called a serial communication block. Unlike the parallel transmission, data moves here bit by bit,
or in a series of bits what defines the term serial communication comes from. After the reception
of data we need to read it from the receiving location and store it in memory as opposed to
sending where the process is reversed. Data goes from memory through the bus to the sending
location, and then to the receiving unit according to the protocol.
2.9 Timer unit:

Since we have the serial communication explained, we can receive, send and process data.
Figure2.7: Timer unit generating signals in regular time intervals
However, in order to utilize it in industry we need a few additionally blocks. One of those is the
timer block which is significant to us because it can give us information about time, duration,
protocol etc. The basic unit of the timer is a free-run counter which is in fact a register whose
numeric value increments by one in even intervals, so that by taking its value during periods T1
and T2 and on the basis of their difference we can determine how much time has elapsed. This is
a very important part of the microcontroller whose understanding requires most of our time.
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2.10 Watchdog:
One more thing is requiring our attention is a flawless functioning of the microcontroller
during its run-time. Suppose that as a result of some interference (which often does occur in
industry) our microcontroller stops executing the program, or worse, it starts working incorrectly.
Figure2.8: Watchdog
Of course, when this happens with a computer, we simply reset it and it will keep working.
However, there is no reset button we can push on the microcontroller and thus solve our problem.
To overcome this obstacle, we need to introduce one more block called watchdog. This block is
in fact another free-run counter where our program needs to write a zero in every time it executes
correctly. In case that program gets "stuck", zero will not be written in, and counter alone will
reset the microcontroller upon achieving its maximum value. This will result in executing the
program again, and correctly this time around. That is an important element of every program to
be reliable without man's supervision.
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3. INTRODUCTION TO EEPROM
3.1 EEPROM:
EEPROM means Electrical Erasable Programmable Read Only Memory and also referred to as
E²PROM chip or i2c.
As the name suggest, an EEPROM can be both erased and programmed with electrical pulses
from a programmer kit, burner or the equipment itself. Since it can be both electrically written
into and electrically erased, the EEPROM IC can be quickly programmed and erased in circuit for
reprogramming without taking them out from the main board.
EEPROM IC is also called a non-volatile memory because when the power is switched off, the
stored data (information) in the EEPROM IC will not be erased or corrupt and the data is still
intact. New EEPROM IC have no data (blank) inside and normally have to program it first with a
programmer tools before it can be use on electron IC circuit.
Figure3.1: Showing EEPROM of Atmel
If you just installed a new or blank EEPROM IC into a main board, even though with the same
part number, I can say that the equipment will surely not going to work because the CPU or
microprocessor do not know how to function. Information or data stored in this type of memory
can be retained for many years even without a continuous dc power supply to the IC.
3.2 Application/ Operation of EEPROM:

EEPROMs mainly store user programmable information such as: -
• VCR programming information or data

• CD programming information or data
• Digital satellite receiver control data or information
• User information on various consumer products such as in Television.
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The EEPROM IC in Computer Monitor performs two tasks: -
• When a monitor is turn on it will copies all the data or information from the EEPROM to
the microprocessor or CPU. For instance, the EEPROM will let the CPU know the
frequencies at which the monitor is going to run.
• The EEPROM IC is used to store the current settings of the Monitor. The current settings
of the monitor will not be erased even when the monitor is switched off. Anytime when a
change is made in the monitor settings, the CPU updates the setting in the EEPROM
(store data in EEPROM). When the monitor is switch on again, the stored settings in
EEPROM IC are used to set up the monitor for operation.
Assuming the data file in MONITOR or TV’s EEPROM are corrupted damaged and failure
detected, what would be the display symptoms like?
• There would be no high voltage (no display) because the CPU don’t activate the 12 volt
line supply to the horizontal and vertical oscillator IC.
• The IC will not save (store) the current setting of the equipment
• Some control functions like sound, brightness, horizontal size and contrast control will
not work.
• The On Screen Display (OSD) would not work or the OSD will have a corrupted or
erratic display.
• Equipment high voltage will shut down (EEPROM set wrongly the horizontal frequency
and will lead to a failure of the horizontal output transistor (HOT)).
Typical EEPROM part numbers are: -

2402, 2404, 2408
24C02, 24C04, 24C08, 24C16
24C325, 24C645AT17C65, AT17C128
93C06, 93C46, 93C56, 93C66
25010, 25020, 25040
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4. INTRODUCTION TO AUDIO PROCESSOR
4.1 Pin Diagram:
Fig 4.1 pin diagram
4.2 Features:
■ INPUT MULTIPLEXER
– 4 STEREO INPUTS
– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
■ ONE STEREO OUTPUT
■ TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS
■ VOLUME CONTROL IN 1.0dB STEPS
■ TWO SPEAKER ATTENUATORS:
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
■ ALL FUNCTION ARE PROGRAMMABLE VIA
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SERIAL BUS
4.3 Application Suggestions:

The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of
systems free from any noisy acoustical effect. The TDA7439 audio processor provides 3 bands
tones control.
4.3.1 Bass, Middle Stages:
The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri =
44KΩ typical.
The Middle cell has an internal resistor Ri = 25KΩ typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN
and OUT pins.
Fig. 4.2 T Type Band pass Filter

The fig. refers to basic T Type Band pass Filter starting from the filter component values (R1
internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter
Q factor are computed as follows:
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4.3.2. Treble Stage:

The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected between treble pins and ground.
4.4 I2C Bus Interface:

Data transmission from microprocessor to the TDA7439 and vice versa takes place through the 2
wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
4.4.1 Data Validity
As shown in fig. 13, the data on the SDA line must be stable during the high period of the clock.
The HIGH and LOW state of the data line can only change when the clock signal on the SCL line
is LOW.
4.4.2 Start and Stop Conditions
As shown in fig.14 a start condition is a HIGH to LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.4.3 Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
4.4.4 Acknowledge
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The master (μP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse
(see fig. 15). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the
SDA line during this clock pulse. The audio processor which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH
level during the ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer.
4.4.5 Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends the
new data. This approach of course is less protected from misworking.
4.5 Software Specification:

Interface Protocol:
The interface protocol comprises:
■ A start condition (S)
■ A chip address byte, containing the TDA7439 address
■ A sub address bytes
■ A sequence of data (N byte + acknowledge)
■ A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
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5. INTRODUCTION TO I2C BUS

5.1 Basic Definition:
An Inter-IC bus is often used to communicate across circuit-board distances.
At the low end of the spectrum of communication options for "inside the box" communication is
I2C ("eye-squared-see"). The name I2C is shorthand for a standard Inter-IC (integrated circuit)
bus.
I2C provides good support for communication with various slow, on-board peripheral devices that
are accessed intermittently, while being extremely modest in its hardware resource needs. It is a
simple, low-bandwidth, short-distance protocol. Most available I2C devices operate at speeds up
to 400Kbps, with some venturing up into the low megahertz range. I2C is easy to use to link
multiple devices together since it has a built-in addressing scheme.
Philips originally developed I2C for communication between devices inside of a TV set.
Examples of simple I2C-compatible devices found in embedded systems include EEPROMs,
thermal sensors, and real-time clocks. I2C is also used as a control interface to signal processing
devices that have separate, application-specific data interfaces. For instance, it's commonly used
in multimedia applications, where typical devices include RF tuners, video decoders and
encoders, and audio processors. In all, Philips, National Semiconductor, Xicor, Siemens, and
other manufacturers offer hundreds of I2C-compatible devices.
5.2 Inside the Box :

I2C is appropriate for interfacing to devices on a single board, and can be stretched across
multiple boards inside a closed system, but not much further. An example is a host CPU on a
main embedded board using I2C to communicate with user interface devices located on a separate
front panel board. A second example is SDRAM DIMMs, which can feature an I2C EEPROM
containing parameters needed to correctly configure a memory controller for that module.
I2C is a two-wire serial bus. There's no need for chip select or arbitration logic, making it cheap
and simple to implement in hardware.
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Figure5.1:I2C has two lines in total
The two I2C signals are serial data (SDA) and serial clock (SCL). Together, these signals make it
possible to support serial transmission of 8-bit bytes of data-7-bit device addresses plus control
bits-over the two-wire serial bus. The device that initiates a transaction on the I2C bus is termed
the master. The master normally controls the clock signal. A device being addressed by the
master is called a slave.
In a bind, an I2C slave can hold off the master in the middle of a transaction using what's called
clock stretching (the slave keeps SCL pulled low until it's ready to continue). Most I2C slave
devices don't use this feature, but every master should support it.
The I2C protocol supports multiple masters, but most system designs include only one. There may
be one or more slaves on the bus. Both masters and slaves can receive and transmit data bytes.
Each I2C-compatible hardware slave device comes with a predefined device address, the lower
bits of which may be configurable at the board level. The master transmits the device address of
the intended slave at the beginning of every transaction. Each slave is responsible for monitoring
the bus and responding only to its own address. This addressing scheme limits the number of
identical slave devices that can exist on an I2C bus without contention, with the limit set by the
number of user-configurable address bits (typically two bits, allowing up to four identical
devices).
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5.3 Communication:
As you can see in Figure 2, the master begins the communication by issuing the start condition
(S). The master continues by sending a unique 7-bit slave device address, with the most
significant bit (MSB) first. The eighth bit after the start, read/not-write (), specifies whether the
slave is now to receive (0) or to transmit (1). This is followed by an ACK bit issued by the
receiver, acknowledging receipt of the previous byte. Then the transmitter (slave or master, as
indicated by the bit) transmits a byte of data starting with the MSB. At the end of the byte, the
receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is repeated if more
bytes need to be transmitted.
Figure5.2: I2C communication
In a write transaction (slave receiving), when the master is done transmitting all of the data bytes
it wants to send, it monitors the last ACK and then issues the stop condition (P). In a read
transaction (slave transmitting), the master does not acknowledge the final byte it receives. This
tells the slave that its transmission is done. The master then issues the stop condition.
5.4 A Simple Bus:

As we've seen, the I2C signaling protocol provides device addressing, a read/write flag, and a
simple acknowledgement mechanism. There are a few more elements to the I2C protocol, such as
general call (broadcast) and 10-bit extended addressing. Beyond that, each device defines its own
command interface or address-indexing scheme.
Standard I2C devices operate up to 100Kbps, while fast-mode devices operate at up to 400Kbps.
A 1998 revision of the I2C specification (v. 2.0) added a high-speed mode running at up to
3.4Mbps. Most of the I2C devices available today support 400Kbps operation. Higher-speed
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operation may allow I2C to keep up with the rising demand for bandwidth in multimedia and
other applications.
Most often, the I2C master is the CPU or microcontroller in the system. Some microcontrollers
even feature hardware to implement the I2C protocol. You can also build an all-software
implementation using a pair of general-purpose I/O pins (single master implementations only).
Since the I2C master controls transaction timing, the bus protocol doesn't impose any real-time
constraints on the CPU beyond those of the application. (This is in contrast with other serial
buses that are timeslot-based and, therefore, take their service overhead even when no real
communication is taking place.)
5.5 The Elegance of I2C:

I2C offers good support for communication with on-board devices that are accessed on an
occasional basis. I2C's competitive advantage over other low-speed short-distance communication
schemes is that its cost and complexity don't scale up with the number of devices on the bus. On
the other hand, the complexity of the supporting I2C software components can be significantly
higher than that of several competing schemes (SPI and Micro Wire, to name two) in a very
simple configuration. With its built-in addressing scheme and straightforward means to transfer
strings of bytes, I2C is an elegant, minimalist solution for modest, "inside the box"
communication needs.
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6. PROJECT DESCRIPTION
Figure 6.1 shows the Block Diagram of a remote controlled digital audio processor using 89c51
microcontroller. The system comprises Atmel’s AT89C51 microcontroller (IC1), TDA7439
audio processor from SGS Thomson (IC4) and I2C bus compatible MC24C02 EEPROM (IC5).
The microcontroller chip is programmed to control all the digital processes of the system.
The audio processor controls all the audio amplifier functions and is compatible with I2C bus. All
the commands from the remote control are received through the IR sensor. The audio amplifier
can also be controlled using the on-board keys
Figure 6.1: Block diagram of DAP
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6.1 Microcontroller (AT89C51):
6.1(a) Description:
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of

Flash programmable and erasable read only memory (PEROM). The device is manufactured
using Atmel’s high-density non-volatile memory technology and is compatible with the industry-
standard MCS-51 instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by a

conventional non-volatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-
flexible and cost-effective solution to many embedded control applications.
6.1(b) Features:
• 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
6.1(c) Function Of Microcontroller:
The function of the microcontroller is to receive commands (through port P3.2) from the remote
handset, program audio controls as per the commands and update the EEPROM. A delay in
updating the EEPROM is de-liberately provided because normally the listener will change the
value of a parameter continuously until he is satisfied. The 40-pin AT89C51 microcontroller has
four 8-bit input/output (I/O) ports.
Port 0 is used for indicating through LEDs the various functions selected via the remote/on-board
keys.
Port 1 drives the 7-segment display using 7-segment latch/decoder/driver IC CD4543.
Port 2 is pulled up via resistor network RNW1 and used for manual key control.
Pins P3.0 and P3.1 of the microcontroller are used as serial data (SDA) and serial clock (SCL)
lines for the I2C bus for communicating with the audio processor (TDA7439) and EPROM
(MC24C02). These two lines are connected to pull-up resistors, which are required for I2C bus
devices.
P3.2 receives the remote commands through the IR receiver module.
Pin P3.4 is used for flashing LED9 whenever a remote command is received or any key is
pressed. The microcontroller also checks the functioning of the memory (MC24C02) and the
24
audio processor (TDA7439). If it is not communicating with these two ICs on the I2C bus, it
flashes the volume level on the 7-segment displays.
6.2 The Audio Processor (TDA7439):
IC TDA7439 is a single-chip I2C-bus compatible audio controller that is used to control all the
functions of the audio amplifier. The output from any (up to four) stereo preamplifier is fed to the
audio processor (TDA7439). The microcontroller can control volume, treble, bass, attenuation,
gain and other functions of each channel separately. All these parameters are programmed by the
microcontroller using SCL and SDA lines, which it shares with the memory IC and the audio
processor. Data transmission from the microcontroller to the audio processor(IC TDA7439) and
the memory (MC24C02) and vice versa takes place through the two-wire I2C-bus interface
consisting of SDA and SCL, which are connected to P3.0 (RXD) and P3.1(TXD) of the
microcontroller, respectively. Here, the microcontroller unit acts as the master and the audio
processor and the memory act as slave devices. Any of these three devices can act as the
transmitter or the receiver under the control of the master
6.3 Memory (MC24C02):
IC MC24C02 is an I2C-bus compatible 2k-bit EEPROM organized as 256×8-bit that can retain
data for more than ten years. Various parameters can be stored in it. To obviate the loss of latest
settings in the case of power failure, the microcontroller stores all the audio settings of the user in
the EEPROM. The memory ensures that the microcontroller will read the last saved settings from
the EEPROM when power resumes.
Using SCL and SDA lines, the microcontroller can read and write data for all the parameters. For
more details on I2C bus and memory interface, please refer to the MC24C02 datasheet. Audio
parameters can be set using the remote control handset or the on-board keys as per the details
given under the ‘remote control’ section.
6.4 7-segment decoder/driver (CD4543B):
It is a BCD-to-seven segment latch/decoder/driver designed primarily for liquid-crystal display

(LCD) application. It can also be used for driving light emitting diode (LED), incandescent, gas-
discharge and fluorescent displays. The operating DC supply voltage ranges from -0.5V to +20V
6.5 2-Channel level meter driver: (KA2281):
It is a monolithic integrated circuit consisting of a two channel LED level meter driver which
driver which was designed for use in stereo radio cassette tape recorders and home stereos. Its
operating DC supply voltage ranges from 5V to 14V.
25
6.6 Power Supply:
6.6(a) Block Diagram:
Fig. 6.7: Block diagram of power supply unit
6.6(b) General Description:
.
Figure 6.7 shows the power supply diagram for the remote controlled digital audio processor. The
AC mains are stepped down by transformer X1 to deliver a secondary output of 9V AC at 1A.
The transformer output is rectified by full-wave bridge rectifier BR1 and filtered by capacitor
C42.
Regulators IC8 and IC9 provide regulated 5V and 9V power supplies, respectively. IC10 acts as
the variable power supply regulator. It is set to provide 3V regulated supply by adjusting preset
VR1. Capacitors C39, C40 and C41 bypass any ripple in the regulated outputs. This supply is not
used in the circuit.
However, the readers can use the same for powering devices like a Walkman. As capacitors
above 10 μF are connected to the outputs of regulator ICs, diodes D3 through D5 provide
protection to the regulator ICs, respectively, in case their inputs short to ground.
Relay RL1 is normally energised to provide mains to the power amplifier. In standby mode, it is
de-energised. Switch S2 is the ‘on’/‘off’ switch.
26
6.6(c) Features:
• Output Current up to 1A
• Output Voltages of 5, 6, 8, 9, 12, 15, 18, 24
• Thermal Overload Protection
• Short Circuit Protection
• Output Transistor Safe Operating Area Protection
6.7 Remote control (NEC-Compatible format):
6.7(a) Block Diagram:
Figure 6.5 Block Diagram of remote control
27
6.7(b) Description:
The micro-controller can accept commands from any IR remote that uses NEC transmission
format. These remote controllers are readily available in the market and use μPD6121,PT2221 or
a compatible IC. Here, we’ve used Creative’s remote handset. All the functions of the system can
be controlled fully using the remote or the on-board keys. By default, the display shows the
volume setting and LEDs indicate the channel selected. LED9 glows momentarily whenever a
command from the remote is received or any key is pressed.
Function adjustments are detailed below:
1. Volume: Use Vol+/Vol- key to increase/decrease the volume. The volume settings are shown
on the two digits, 7-segment display. Steps can be varied between ‘1’ and ‘80.’
2. Mute and Standby: Using ‘Mute’ and ‘Standby’ buttons, you can toggle the mute and standby
status, respectively. If ‘Mute’ is pressed, the display will show ‘00.’ In ‘Standby’ mode, the relay
de-energizes to switch off the main amplifier. All the LEDs and displays, except LED9, turn off
to indicate the standby status.
3. Input Select: To select the audio input source, press ‘Channel’ key until the desired channel is
selected. The LED corresponding to the selected channel turns on and the input gain setting for
that channel is displayed for five seconds. Thereafter, the volume level is displayed on the 7-
segment display.
4. Input Gain set: Press ‘Gain’ key. The LED corresponding to the channel will start blinking and
the gain value is displayed. Use Vol+/Vol- key to increase/decrease the gain for that channel.
Note that the gain can be varied from ‘1’ to ‘15.’ If you press ‘Gain’ key once more, and no key
is pressed for five seconds, it will exit the gain setting mode and the volume level is displayed.
5. Audio: Press ‘Audio Set’ (Menu) key to adjust bass, middle, treble and attenuation one by one.
Each time ‘Audio Set’ key is pressed, the LED corresponding to the selected function turns on
and the function value is displayed. Once the required function is selected, use Vol+ and Vol- to
adjust the setting. Bass, middle and treble can be varied from ‘07’ to ‘7.’ Values ‘0’through ‘7’
indicate ‘Boost’ and ‘00’ through ‘07’ indicate ‘Cut.’ Attenuation can be varied from ‘0’ to ‘40.’
6.7 (c) Advantages:
28
An infrared remote offers several advantages:
1. It is a cost-effective signaling system
2. Unlike radio-frequency-based control devices, it is not subject to any stringent regulation and
restriction.
3. It is a line-of-sight system with a range of 5 to 10 meters, hence its radiation stays confined to
a single room in which it is used. It thus prevents interference between units operating in different
rooms even when using identical device address and command code.
4. A relatively broad modulation frequency range is available using inexpensive ASICs and
components.
5. It is generally insensitive to interference from external electrical or magnetic fields.
6. It offers relatively high energy efficiency, which enhances the battery life.
7. Infrared emitters and detectors are inexpensive and readily available
6.7(d) Limitations:
1. Line-of-sight propagation becomes a limitation when you need to control a device from
another room.
2. Infrared is subject to mutual interference from multiple sources in the same room as most
consumer IR transmissions use a wavelength of either 880 or 940 nm (corresponding to the
two commonly available IR-emitting LED types). This limitation can be tackled by using
different sub-carrier frequencies to modulate the light signals coupled with different encoding
schemes to carry the data content.
3. Although largely immune to electrical or magnetic interference, the infrared signal is

somewhat subject to interference from sunlight and other infrared sources as also fluorescent
lights.
7. PROJECT METHODOLOGY
29
7.1 Components:
7.1.1 Digital Audio processor:
Semiconductors:
IC1 - AT89C51 microcontroller

IC2, IC3 - CD4543 7-segment decoder/ driver
IC4 - TDA7439 audio processor
IC5 - MC24C02 I2C EEPROM
IC6 - KA2281 2-channel level meter driver
IC7 - TSOP1238 IR receiver module
IC8 - 7809 9V regulator
IC9 - 7805 5V regulator
IC10 - LM317 variable regulator
T1 - BC558 pnp transistor
T2, T3, T5 - BC547 npn transistor
T4 - BD139 pnp transistor
BR1 - W04M bridge rectifier
D1-D6 - 1N4004 rectifier diode
DIS1, DIS2 - LTS543 7-segment display
DIS3 - 10-LED bargraph display
LED1-LED8 - Red LED
LED9 - Green LED
Resistors (all ¼-watt, ±5% carbon):
R1 - 8.2-kilo-ohm
R2-R24,
R40-R49 - 1-kilo-ohm
R25, R28,
R50, R53 - 10-kilo-ohm
R26, R29,
R30, R34 - 2.7-kilo-ohm
R27 - 100-ohm
R31, R35 - 5.6-kilo-ohm
R32, R33 - 4.7-kilo-ohm
R36-R39 - 22-kilo-ohm
R51 - 220-kilo-ohm
R52 - 2.2-kilo-ohm
Capacitors:
C1, C2 - 33pF ceramic disk
30
C3, C10 - 10μF, 16V electrolytic

C4-C6,
C39-C41 - 100nF ceramic disk
C7 - 4.7μF, 16V electrolytic
C8, C9 - 2.2μF, 16V electrolytic
C11, C20 - 5.6nF polyester
C12, C19 - 18nF polyester
C21-C28 - 0.47μF polyester
C29-C32 - 4.7μF, 25V electrolytic
C33, C34 - 10μF, 25V electrolytic
C35 - 1000μF, 25V electrolytic
C37, C38 - 0.33μF ceramic disk
Miscellaneous:
X1 - 230V AC primary 0 to 12V, 1A secondary transformer

RL1 - 9V, 160Ω, 2 C/O relay
XTAL - 12MHz crystal
S1- S7 - Push-to-on switch
S8 - On/Off switch Remote - Creative’s remote (NEC compatible format)
7.1.2 NEC-Compatible format remote-control:
Semiconductors:
IC1 - CD6121 remote Tx 20-pin SMT

T1 - BC548 npn transistor
IR LED1 - LD271 or equivalent IR LED
LED1 - Red LED
Resistors (all ¼-watt, ±5% carbon):
R1 - 330-ohm
R2 - 1-kilo-ohm
R3 - 2.2-ohm, 0.5W
R4, R5, R6 - (100-kilo-ohm)
Capacitors:
C1, C2 - 220pF ceramic disk

31
Miscellaneous:
K2, K3, K6
K14, K15,
K19, K28 - Tactile switch (10x10mm)
XTAL - 455 kHz (2-pin) ceramic resonator
BAT. - 2x1.5V=3V
- 2-cell battery holder
- PCB, etc
7.2 Softwares used:

1. Kiel uVision3.
2. Metalink’s Assembler.
7.3 Equipments used:

1. Soldering iron, solder, flux.
2. Personal computer.
3. Stereo Power Amplifier.
7.4 Procedure of building the DIGITAL AUDIO PROCESSOR:
Step 1: Clean off dust and dirt from the PCB with paper towel soaked in acetone
Step 2: Before you install the microcontroller, memory and audio processor in their sockets
and solder the IR receiver module, make sure that the supply voltage is correct. All parts,
except the audio processor (TDA7439), require 5V DC supply. The audio processor is
powered by 9V DC.
Step 3: Connect the audio source (such as CD player, computer etc) at the ‘Audio Input’
say, L-IN1 AND R-IN1 for left and right channel inputs in the circuit.
Step 4: Connect the Left (L-OUT) and Right(R-OUT) to the channel input(s) of any audio
amplifier system.
Step 5: Press S1 and S2 for volume control. The position of these keys will be indicated by
the glowing of LEDs in the display module DIS3.
32
Step 6: Press S3 (SEL) to select the enhancement mode such as Bass, treble etc.
Step 7: Press S4 (SOURCE) to select the source input channels (L-IN1 through R-IN4).You
will see the corresponding LED5 through LED8 glow.
Step 8: Press S5 (GAIN) to attenuate or increase the gain.
7.5 Procedure for Software Implementation:

The software was assembled using Metalink’s ASM51 assembler, which is freely available for
download. The source code has been extensively commented for easier understanding. It can be
divided into the following segments in the order of listing:
1. Variable and constant definitions

2. Delay routines
3. IR decoding routines
4. Keyboard routines
5. TDA7439 communication
6. MC24C02 communication
7. I2C bus routines
8. Display routines
9. IR and key command processing
10. Timer 1 interrupt handler
11. Main program
On reset, the microcontroller executes the main program as follows:
1. Initialise the microcontroller’s registers and random-access memory (RAM) locations.

2. Read Standby and Mute status from the EEPROM and initialise TDA7439 accordingly.
3. Read various audio parameters from the EEPROM and initialise the audio processor.
4. Initialise the display and LED port.
5. Loop infinitely as follows, waiting for events:
• Enable the interrupts.
• Check the monitor input for AC power-off. If the power goes off, jump to the power-off
sequence routine.
• Else, if a new key is pressed, call the DO_KEY routine to process the key. For this, check
whether the NEW_KEY bit is set. This bit is cleared after the command is processed.
• Else, if a new IR command is received, call the DO_COM routine to process the remote
command. For this, check whether the NEW_COM (new IR command available) bit is set.
This bit is cleared after the command is processed.
• Jump to the beginning of the loop.
6. Power-off sequence. Save all the settings to the EEPROM, and turn off the display and standby
relay. Since the output of the IR sensor is connected to pin 12 (INT0) of the
33
microcontroller, an external interrupt occurs whenever a code is received. The algorithm for
decoding the IR stream is completely implemented in the ‘external interrupt 0’ handler routine.
This routine sets NEW_COM (02H in bit memory) if a new command is available. The decoded
command byte is stored in ‘Command’ (location 021H in the internal RAM). The main routine
checks for NEW_COM bit continuously in a loop. Timer 0 is exclusively used by this routine to
determine the pulse timings.
Decoding the IR stream involves the following steps:
1. Since every code is transmitted twice, reject the first by introducing a delay of 85 milliseconds
(ms) and start timer 0. The second transmission is detected by checking for no-overflow timer 0.
In all other cases, timer 0 will overflow.
2. For second transmission, check the timer 0 count to determine the length of the leader pulse (9
ms). If the pulse length is between 8.1 ms and 9.7 ms, it will be recognised as valid. Skip the
following 4.5ms silence.
3. To detect the incoming bits, timer 0 is configured to use the strobe signal such that the counter
runs between the interval periods of bits. The value of the counter is then used to determine
whether the incoming bit is ‘0’, ‘1’ or ‘Stop.’ This is implemented in the RECEIVE_BIT routine.
4. If the first bit received is ‘Stop,’ repeat the last command by setting the NEW_COM bit.
5. Else, receive the rest seven bits. Compare the received byte with the custom code (C Code). If
these don’t match, return error.
6. Receive the next byte and compare with the custom code. If these don’t match, return error.
7. Receive the next byte and store in ‘Command.’
8. Receive the next byte and check whether it is complement value of ‘Command.’ Else, return
error.
9. Receive ‘Stop’ bit.
10. Set NEW_COM and return from interrupt.
7.6 Assembly Programming Code:
**************************************************************************
; PROGRAM FOR REMTOE CONTROLLED AUDIO PROCESSOR
34
;**************************************************************************
;**************************************************************************
$MOD51 ; include predefined constants
;$NOPRINT
;**************************************************************************
; Variable & Constant Definitions
;**************************************************************************
STACKBASE EQU 034H ; stack starts at 35H
EEPROM_ADDR EQU 0A0H ; address of 24CXX on I2C bus
AUDIOPROC_ADDR EQU 088H ; address of TDA7439 on I2C bus
C_CODE1 EQU 084H ; CUSTOM CODE for Creative Remote
C_CODE2 EQU 035H ; CUSTOM CODE' for Creative Remote
; keypad /remote command codes
VOL_UP EQU 010H ; REMOTE- VOL +
VOL_DN EQU 014H ; REMOTE- VOL -
SEL EQU 004H ; REMOTE- MENU
SOURCE EQU 008H ; REMOTE- MOUSE
INGAIN EQU 018H ; REMOTE- ZOOM
MUT EQU 00CH ; REMOTE- MUTE
STDBY EQU 016H ; REMOTE- CANCEL
ZDATA EQU R1 ;data register for 24C01/02 functions
ADDR EQU R2 ; address register for 24C01/02 functions
AUDIODATA EQU R3 ; Audio parameter values for audio processor
SUBADDR EQU R4 ; Audio processor function selection byte
SDA BIT P3.0 ; i2c serial data
SCL BIT P3.1 ; i2c serial clock
IR_IN BIT P3.2 ; IR sensor input line, inverted output from sensor
INDICATOR BIT P3.4 ; Status indicator LED
POWER BIT P3.5 ; STANDBY relay control
DISP_LATCH BIT P3.7 ; Latch control of Display port (CD4543B)
MONITOR BIT P2.7 ; Power monitor input
; BIT Variables
; Max bit variables available is 16, as general user RAM starts from 022H
STOP BIT 00H ; stop bit in IR code
RX_BIT BIT 01H ; next received bit in IR stream
NEW_COM BIT 02H ; new IR command available
NEW_KEY BIT 03H ; new key input available
REPEAT BIT 04H ; Repeated Remote command (contineous key press)
STANDBY BIT 05H ; Standby status
MUTE BIT 06H ; Mute status
GAIN_ON BIT 07H ; Bit set if gain function selected
; BYTE Variables
; Max byte variables available is 18, as stack starts at 35H
COMMAND DATA 022H ; Received IR command
KEY DATA 023H ; Keyboard command
CHANNEL DATA 024H ; TDA7439 input channel
VOLUME DATA 025H ; TDA7439 input attenuation
BASS DATA 026H ; TDA7439 bass adj
MIDDLE DATA 027H ; TDA7439 voice adj
TREBLE DATA 028H ; TDA7439 treble adj
R_ATTN DATA 029H ; TDA7439 Right attenuation (volume)
L_ATTN DATA 02AH ; TDA7439 Left attenuation (volume)
GAIN1 DATA 02BH ; TDA7439 input gain of IN1
GAIN2 DATA 02CH ; TDA7439 input gain of IN2
GAIN3 DATA 02DH ; TDA7439 input gain of IN3
35
GAIN4 DATA 02EH ; TDA7439 input gain of IN4

GAIN DATA 02FH ; TDA7439 input gain of active channel
LED_STATUS DATA 030H ; currently loaded value in LED port
;LED_STATUS BITS 0-1-2-3-4-5-6-7 = BASS-MIDDLE-TREBLE-ATTN-IN1-IN2-IN3-IN4
T1_COUNT DATA 031H ;TIMER1 Counter
;**************************************************************************
; PROGRAM STARTS HERE
; RESET VECTOR
ORG 00H ;locate routine at 00H
RESET:
JMP START ;jump to START
;**************************************************************************
; INTERRUPTS (place interrupt routines at appropriate memory locations )
ORG 03H ; external interrupt 0, used by IR Sensor
JMP INTR_EX0
ORG 0BH ; timer 0 interrupt
RETI
ORG 13H ; External interrupt 1
RETI
ORG 1BH ; timer 1 interrupt
JMP INTR_T1
ORG 23H ; serial port interrupt
RETI
ORG 25H ; locate beginning of rest of program
;**************************************************************************
; DELAY ROUTINES
;**************************************************************************
; Delay routine to introduce 6 microSec Delay with 12MHz crystal
;**************************************************************************
BITDLY: ;2cyl (CALL)
NOP ;1 Cyl
NOP ;1 Cyl
RET ;2 Cyl
;**************************************************************************
; Delay routine in miliSecond. (Approximate)
; Entry: R6 = (Delay in mS -0.004)/0.501 OR R6 = Delay in mS * 2
; assuming 12MHz clock, 1 Cyl=1 microSec
; delay in inner loop= R7*2 microSec
; delay in outer loop= R6*(3+R7*2) microSec
; delay in call & ret= 4 microSec
; Total delay = R6*(3+R7*2)+4 microSec
; R7=249(F9H)=>Min delay=0.507 miliSec, Max delay = 127.759 mS
; Destroys R6, R7
;*************************************************************************
DELAYMS: ;2-Cyl
x95: MOV R7,#0F9H ;1-Cyl
DJNZ R7,$ ;2-Cyl
DJNZ R6,x95 ;2-Cyl
RET ;2-Cyl
;*************************************************************************
; Delay routine in Seconds. (Approximate)
; Entry: R5 = Delay in Sec * 10
; Destroys R5, R6, R7
;*************************************************************************
DELAYSEC:
36
x96: MOV R6,#200

ACALL DELAYMS
DJNZ R5,x96
RET
;*************************************************************************
; END OF DELAY ROUTINES
; IR DECODING ROUTINES
;**************************************************************************
; Receives one bit from IR_IN. The received bit is returned in RX_BIT,
; or STOP is set if it is a stop bit. IR_IN should be LOW while calling
; this function. Uses TIMER 0 already set in Mode1, TR0=1 & GATE0=1. EA=0
; DESTROYS PSW->CARRY AND R0
;**************************************************************************
RECEIVE_BIT:
MOV TH0,#0F4H ;TIMER0 RELOAD VALUE, MAX COUNT=65535-62464(F400H)=3071
;BIT WILL BE RECOGNISED AS STOP BIT IF TIMER0 OVERFLOWS
;SINCE TL0 IS IGNORED, OVERFLOW WILL BE ANYWHERE BETWEEN 2816 &
3071
CLR TF0
CLR C
CLR STOP
CLR RX_BIT ;ASSUME BIT=0
JNB IR_IN,$ ;LOOP UNTIL IR_IN GOES HIGH, TIMER0 STARTS AFTER THIS
x60: JB TF0,x62 ;STOP BIT IF TIMER OVERFLOWS
JB IR_IN,x60 ;LOOP TILL TIMER0 IS RUNNING
;TIMER0 STOPS HERE, CHECK PULSE LENGTH
MOV R0,TH0
CJNE R0,#0F8H,x61 ;BIT =0 IF COUNT LESS THAN 1024
x61: JC x63 ;RX_BIT=0
SETB RX_BIT ;RX_BIT=1
AJMP x63
x62: SETB STOP
x63:
RET
;********************************************************************************
;External interrupt 0 handler -> DECODES A NEC FORMAT IR STREAM
;SETS NEW_COM(02H) IF A NEW COMMAND IS AVAILABLE. SHOULD BE CLEARED IF THE
COMMAND IS PROCESSED
;THE COMMAND IS STORED IN THE COMMAND(021H) LOCATION IN INTERNAL RAM
;USES TIMER0
;DESTROYS R0,R2,TMOD0
;********************************************************************************
INTR_EX0:
CLR EX0 ;Disable Int0
PUSH ACC
PUSH PSW
; EVERY KEYCODE IS TRANSMITTED TWICE. THE FIRST TIME IS REJECTED
JNB TF0, IRDECODE ; SECOND & SUBSEQUENT CONTINEOUS TRANSMISSION
MOV R2,#0AAH ;DELAY 85mS TO REJECT THE FIRST TRANSMISSION
DLY85:
MOV R0,#0F9H ;1-Cyl
DJNZ R0,$ ;2-Cyl
DJNZ R2,DLY85 ;2-Cyl
37
AJMP x72
IRDECODE: ; DECODE INCOMING IR COMMAND
ORL TMOD,#01H ;SET MODE1 FOR TIMER0 (16-BIT TIMER )
ANL TMOD,#0F1H ;GATE0=0, CT=0
MOV TH0,#00H ;<-CHECK NECESSATY?
MOV TL0,#00H ;<-CHECK NECESSATY?
SETB TR0 ; START TIMER0
JNB IR_IN,$ ;LOOP UNTIL IR_IN GOES HIGH, END OF START PULSE
CLR TR0 ;STOP TIMER0
;*****check length of start pulse**********************************************************
MOV A,TH0
CJNE A,#020H,x64 ;MIN TIMER0 COUNT = 20OOH = 8192D i.e. 8.1ms START PULSE
AJMP x66
x64: JC x72
CJNE A,#025H,x65 ;MAX TIMER0 COUNT = 25FFH = 9727D i.e. 9.7ms START PULSE
AJMP x66
x65: JNC x72 ;START PULSE LENGTH INVALID
x66: ;START PULSE IDENTIFIED, CONTINUE
JB IR_IN,$ ;LOOP UNTIL IR_IN GOES LOW, SKIP 4.5mS SILENCE
;TODO->AVOID INFINITE LOOP IF ONLY A NOISE START SIGNAL RECEIVED BUT NO STOP BIT
ORL TMOD,#08H ;GATE0=1
SETB TR0 ;START TIMER0
ACALL RECEIVE_BIT ;RECEIVE THE INCOMING 0,1 OR STOP BIT
JB STOP,STOPBIT ;STOP BIT RECEIVED, REPEAT LAST COMMAND
MOV C,RX_BIT
RLC A
MOV R2,#07H ;NUMBER OF BITS IN A BYTE, 7 + 1 ALREADY RECEIVED
x67: ;RECEIVE CUSTOM CODE
JB STOP,x72 ;STOP BIT RECEIVED, ERROR
MOV C,RX_BIT
RLC A
DJNZ R2,x67
CJNE A,#C_CODE1,x72 ;CHECK CUSTOM CODE
MOV R2,#08H ;NUMBER OF BITS IN A BYTE
x68: ;RECEIVE CUSTOM CODE'
MOV C,RX_BIT
RLC A
DJNZ R2,x68
CJNE A,#C_CODE2,x72 ;CHECK CUSTOM CODE'
x69: ;RECEIVE COMMAND BYTE
MOV C,RX_BIT
RLC A
DJNZ R2,x69
MOV COMMAND,A ;MOVE VALUE TO COMMAND BYTE
x70: ;RECEIVE INVERTED COMMAND BYTE
MOV C,RX_BIT
38
RLC A
DJNZ R2,x70
CPL A
CJNE A, COMMAND,x72 ;CHECK INVERTED COMMAND BYTE
ACALL RECEIVE_BIT ; RECEIVE STOP BIT
JNB STOP,x72 ;ERROR
AJMP x71 ;VALID COMMAND
STOPBIT:
SETB NEW_COM ;SHOULD BE CLEARED IF THE COMMAND IS
PROCESSED
SETB REPEAT ;Repeated command<- contionous key press
MOV R2,#0AAH
AJMP DLY85
x71: ;NEW VALID COMMAND
SETB NEW_COM ;SHOULD BE CLEARED IF THE COMMAND IS
PROCESSED
CLR REPEAT
x72: CLR TR0 ;STOP TIMER0
ANL TMOD,#0F7H ;GATE0=0
CLR A
MOV TH0,A
MOV TL0,A
CLR TF0 ;TIMER0 WILL OVERFLOW EXCEPT FOR SECOND TIME OR
SETB TR0 ;CONTINOUS TRANSMISSION
POP PSW
POP ACC
SETB EX0 ;Enable Int0
RETI ;INT0 Return
; END OF IR DECODING ROUTINES
; KEY INPUT PROCESSING ROUTINES

;**************************************************************************
; Checks for key press, sets NEW_KEY & code in KEY if key pressed
; No multiple key presses, no continuous key press
;**************************************************************************
CHECK_KEY:
MOV A,P2
SETB ACC.7
CJNE A,#0FFH,NE_FF_KEY
RET ;no keys pressed
NE_FF_KEY:
PUSH IE
CLR EA ;disable interrupts
PUSH B
MOV B,A
MOV R6,#064H ;50mS delay for key debounce
MOV A,P2
SETB ACC.7
CJNE A,B,END_CHECK_KEY
;key debounced, check for keys one by one, multiple key press not allowed
KEY1:
CJNE A,#0FEH,KEY2
MOV KEY,#VOL_UP
AJMP SET_NEW_KEY
KEY2:
39
CJNE A,#0FDH,KEY3
MOV KEY,#VOL_DN
AJMP SET_NEW_KEY
KEY3:
CJNE A,#0FBH,KEY4
MOV KEY,#SEL
AJMP SET_NEW_KEY
KEY4:
CJNE A,#0F7H,KEY5
MOV KEY,#SOURCE
AJMP SET_NEW_KEY
KEY5:
CJNE A,#0EFH,KEY6
MOV KEY,#INGAIN
AJMP SET_NEW_KEY
KEY6:
CJNE A,#0DFH,KEY7
MOV KEY,#MUT
AJMP SET_NEW_KEY
KEY7:
CJNE A,#0BFH,CONT_KEYPRESS
MOV KEY,#STDBY
SET_NEW_KEY: ;set flag as new key available
SETB NEW_KEY ;cleared by the key processing routine
CONT_KEYPRESS: ;Wait in a loop till key is released
MOV A,P2
SETB ACC.7
CJNE A,#0FFH,CONT_KEYPRESS
MOV R6,#064H ;Key must be released for at least 50mS
CALL DELAYMS
MOV A,P2
SETB ACC.7
CJNE A,#0FFH,CONT_KEYPRESS
END_CHECK_KEY:
POP B
POP IE
RET
; END OF KEY INPUT PROCESSING ROUTINES
; TDA7439 AUDIO PROCESSOR COMMUNICATION ROUTINES

;**************************************************************************
; TDA7439 communication routine with no incremental bus.
; Called with function select byte in SUBADDR(R4) & data in AUDIODATA(R3).
; Returns CY set to indicate that the bus is not available
; or that the addressed device failed to acknowledge.
; Destroys A, R3, R4
;**************************************************************************
SET_AUDIO:
CLR C
CALL I2C_START
JC x56 ; abort if bus not available
MOV A,#AUDIOPROC_ADDR ; setup Device address
CALL I2C_SHOUT ; send device address
JC x55 ; abort if no acknowledge
MOV A,SUBADDR ; send address
40
CLR ACC.4 ; No Incremental Bus

CALL I2C_SHOUT
MOV A,AUDIODATA ; get data
CALL I2C_SHOUT ; send data
CLR C ; clear error flag
x55:
CALL I2C_STOP
x56:
RET
;*************************************************************************
; Initialize TDA7439.
; Send audio parameter values except R_ATTN & L_ATTN to audio processor
; with incremental bus.
; Destroys ACC, CY, B, R0
;*************************************************************************
INIT_AUDIO:
CLR C
MOV B,#05H ; byte count (6-1=5), leave out R_ATTN & L_ATTN
MOV R0,#024H ; RAM pointer
CALL I2C_START
JC INIT_AUDIO ; loop till bus available
MOV A,#AUDIOPROC_ADDR ; setup Device address
JC INITAUDEND ; abort if no acknowledge
MOV A,#00H ; send sub address(function select)
SETB ACC.4 ; Incremental Bus
CALL I2C_SHOUT
INCBUS:
MOV A,@R0 ; get audio parameter value
INC R0 ; increment RAM pointer, sub address auto increase
DJNZ B,INCBUS ; setup next audio parameter
INITAUDEND:
CALL I2C_STOP
RET
; END OF TDA7439 AUDIO PROCESSOR COMMUNICATION ROUTINES
; 24C01/02 COMMUNICATION ROUTINES

;**************************************************************************
; 24Cxx Current Address Read function.
; Returns data in A.
; Destroys A
;**************************************************************************
READ_CURRENT:
CALL I2C_START
MOV A,#EEPROM_addr ; setup address
SETB ACC.0 ; specify read operation
41

CALL I2C_SHIN ; receive data byte
CALL I2C_NAK ; do not acknowledge byte
x42:
CALL I2C_STOP
x43:
RET
;**************************************************************************
; 24C01/02 Random Read function.
; Called with byte address in ADDR
; Returns data in A.
; Destroys A, R1
;**************************************************************************
READ_RANDOM:
CALL I2C_START
MOV A,#EEPROM_addr ; setup address
CLR ACC.0 ; dummy write command to set internal address
MOV A,ADDR ; send address
CALL I2C_SHOUT
CALL READ_CURRENT ; Call Current Address Read function.
AJMP x45 ; exit
x44:
CALL I2C_STOP
x45:
RET
;*************************************************************************
; 24C01/02 Sequential Read function. Initializes audio parameters in RAM
; Read 11 bytes (01H to 0CH) sequentially from 24Cxx and move to
; internal RAM locations 024H to 02FH. Assumes address counter already
; set to 01H on entry (should be preceded by read at 00H)
; destroys ACC, B, CY, R0
;*************************************************************************
INIT_MEM:
CALL I2C_START
JC INITMERR ; abort if bus not available
MOV B,#0BH ; byte count (11 bytes)
MOV R0,#024H ; RAM pointer
MOV A,#EEPROM_ADDR ; setup address
SETB ACC.0 ; specify read operation
JC INITMERR ; abort if no acknowledge
SEQREAD:
CALL I2C_SHIN ; receive data byte
MOV @R0,A ; move byte to internal RAM
INC R0 ; increment RAM pointer
DJNZ B,CONTRX
CALL I2C_NAK ; do not acknowledge byte to end transmission
42
AJMP ENDRX
CONTRX:
CALL I2C_ACK ; acknowledge byte to receive more bytes
AJMP SEQREAD
ENDRX:
CALL I2C_STOP
INITMERR:
CALL BITDLY
RET
;**************************************************************************
; 24C01/02 Byte Write function.
; Called with byte address in register ADDR(R2) & data in register ZDATA(R1)
; Does ACK polling till device responds.
; Does not wait for write cycle to complete.
; Returns CY set to indicate that the addressed device failed to acknowledge.
; Destroys A, R1, R2
;**************************************************************************
BYTEWRITE:
CLR C
CALL BITDLY ; wait min time between Stop & Start on I2C bus
CALL I2C_START
JC BYTEWRITE ; loop until bus available
MOV A,#EEPROM_ADDR ; setup device address & write operation
JC NACKBWR ; loop till device acknowledges (ACK Polling)
MOV A,ADDR ; send address

CALL I2C_SHOUT
JC ENDBWR
MOV A,ZDATA
AJMP ENDBWR
NACKBWR:
CALL I2C_STOP
CALL BITDLY ; wait some time
AJMP BYTEWRITE ;retry
ENDBWR:
CALL I2C_STOP
RET
;*************************************************************************
;save standby status & audio parameters to EEPROM
;Writes 12 Bytes from RAM locations 24H to 2FH & one byte for standby + mute bits
;to EEPROM addresses 00H to 0CH using byte write with ack polling.
;Returns CY set to indicate error.
;Destroys ACC, CY, B, R0, R1, R2
;*************************************************************************
SAVE_STATE:
mov l_attn,r_attn ;REMOVE WHEN BALANCE ADJUSTEMENT IS ADDED?
CLR A
MOV C,MUTE
RLC A ; move standby bit into ACC.0
MOV C,STANDBY
RLC A ; move standby bit into ACC.0, MUTE to ACC.1
MOV ZDATA,A ; load data byte
43
MOV ADDR,#00H ; load address

CALL BYTEWRITE ; write byte
JC END_SAVE_STATE
MOV B,#0BH ; BYTE COUNT
MOV R0,#024H ; RAM Pointer
BWRLOOP:
INC ADDR ; increment address
MOV A,@R0 ; load data
MOV ZDATA,A ; load data
CALL BYTEWRITE ; write byte
JC END_SAVE_STATE
INC R0 ; increment RAM pointer
DJNZ B,BWRLOOP ; decrement byte counter & loop
END_SAVE_STATE:
RET ;END SAVE_STATE
; END OF 24C01/02 COMMUNICATION FUNCTIONS
; I2C BUS FUNCTIONS

;**************************************************************************
; Send START on i2c bus, defined as high-to-low SDA with SCL high.
; Return with SCL, SDA low.
; Returns CY set if bus is not available.
;**************************************************************************
I2C_START:
SETB SDA
SETB SCL
; Verify bus available.
JNB SDA, x46 ; jump if not high
JNB SCL, x46 ; jump if not high
NOP ; enforce setup delay and cycle delay
CLR SDA
CALL BITDLY ; enforce hold delay
CLR SCL
AJMP x47
x46:
SETB C ; set error flag
x47:
RET
;**************************************************************************
; Send STOP, defined as low-to-high SDA with SCL high.
; SCL expected low on entry. Return with SCL, SDA high.
;**************************************************************************
I2C_STOP:
CLR SDA
NOP ; enforce SCL low and data setup
NOP
SETB SCL
CALL BITDLY ; enforce setup delay
SETB SDA
RET
;**************************************************************************
; Shift out a byte to the AT24Cxx, most significant bit first.
; SCL, SDA expected low on entry. Return with SCL low.
; Called with data to send in A.
44
; Returns CY set to indicate failure by slave to acknowledge.

; Destroys A.
;**************************************************************************
I2C_SHOUT:
PUSH B
MOV B,#08H ; bit counter
x48:
RLC A ; move bit into CY
MOV SDA,C ; output bit
SETB SCL ; raise clock
CALL BITDLY ; enforce SCL high
CLR SCL ; drop clock
DJNZ B,x48 ; next bit
SETB SDA ; release SDA for ACK
NOP ; enforce SCL low and tAA
NOP
SETB SCL ; raise ACK clock
MOV C,SDA ; get ACK bit
CLR SCL ; drop ACK clock
POP B
RET
;**************************************************************************
; Shift in a byte from the AT24Cxx, most significant bit first.
; SCL expected low on entry. Return with SCL low.
; Returns received data byte in A.
;**************************************************************************
I2C_SHIN:
SETB SDA ; make SDA an input
PUSH B
MOV B,#08H ; bit count
x49:
CALL BITDLY ; enforce SCL low and data setup
MOV C,SDA ; input bit
RLC A ; move bit into byte
DJNZ B,x49 ; next bit
POP B
RET
;**************************************************************************
; Clock out an acknowledge bit (low).
; SCL expected low on entry. Return with SCL, SDA low.
;**************************************************************************
I2C_ACK:
CLR SDA ; ACK bit
NOP
SETB SCL ;raise clock
RET
;**************************************************************************
45
; Clock out a negative acknowledge bit (high).

; SCL expected low on entry. Return with SCL low, SDA high.
;**************************************************************************
I2C_NAK:
SETB SDA ; NAK bit
NOP
RET
; END OF I2C BUS ROUTINES
; DISPLAY ROUTINES
;*************************************************************************
;loads LED_STATUS byte in LED port.
;*************************************************************************
LOAD_LED:
PUSH ACC
MOV A,LED_STATUS
CPL A
MOV P0,A
POP ACC
RET
;**************************************************************************
; INCREMENT FUNCTION DISPLAY. low nibble of LED_STATUS stores function display
; DESTROYS ACC
;**************************************************************************
; INC_SELD:
MOV A,LED_STATUS
ANL A,#0FH ;Clear high nibble (source display)
JNZ NOTVOL
MOV B,BASS
CALL DISP_AUD
MOV A,#01H ;BASS LED on
AJMP LDFUN
NOTVOL:
JNB ACC.0,NOTBASS
MOV B,MIDDLE
CALL DISP_AUD
MOV A,#02H ;MIDDLE LED on
AJMP LDFUN
NOTBASS:
JNB ACC.1,NOTMIDDLE
MOV B,TREBLE
CALL DISP_AUD
MOV A,#04H ;TREBLE LED on
AJMP LDFUN
NOTMIDDLE:
JNB ACC.2,NOTTREBLE
CALL DISP_ATT
MOV A,#08H ;ATTENUATION LED on
AJMP LDFUN
NOTTREBLE:
JNB ACC.3,NOTATTN
46
CALL DISP_VOL
MOV A,#00H ;All LEDs off(Volume)
AJMP LDFUN
LDFUN:
ANL LED_STATUS,#0F0H ;clear low nibble
ORL LED_STATUS,A ;save function selection display
ACALL LOAD_LED
NOTATTN:
RET
;**************************************************************************
;LOAD SOURCE DISPLAY. high nibble of LED_STATUS stores source display
;Also updates GAIN byte.
;DESTROYS A,B,CY
;**************************************************************************
LOAD_SRCD:
MOV A,CHANNEL
CJNE A,#00H,SRC3
MOV B,#080H ;IN4
MOV GAIN,GAIN4
AJMP LDSRC
SRC3: CJNE A,#01H,SRC2
MOV B,#040H ;IN3
MOV GAIN,GAIN3
AJMP LDSRC
SRC2: CJNE A,#02H,SRC1
MOV B,#020H ;IN2
MOV GAIN,GAIN2
AJMP LDSRC
SRC1: MOV B,#010H ;IN1
MOV GAIN,GAIN1
LDSRC:
MOV LED_STATUS,B;function select = volume & save status to RAM
ACALL LOAD_LED
RET
;**************************************************************************
;BINARY TO BCD CONVERSION ROUTINE
;SEE P313 OF R. S. GAONKAR'S 8085 BOOK FOR ACTUAL LOGIC
;ACCEPTS A BINARY NUMBER BETWEEN 0-99D(63H) IN ACC & CONVERTS TO BCD
;IF ACC>63H(99D) OUTPUTS 00H
;DESTROYS A,CY & B
;**************************************************************************
HEXBCD:
MOV B,#00H
CJNE A,#64H,N100 ;NOT EQUAL 100D
N100: JC LT99
AJMP GT99 ;greater than 99D
LT99: ;less than 99D, continue
SUB10: ;repeatedly subtaract 10D from Acc till reminder less than 10D
CLR C
CJNE A,#0AH,N10 ;NOT EQUAL 10D
N10: JC LT10 ;reminder less than 10D
SUBB A,#0AH
INC B ;loop counter
AJMP SUB10
GT99: CLR A ;output 00 only if greater than 99D
47
LT10: SWAP A ;A contains low BCD nibble & B contains high BCD nibble
ORL A,B
SWAP A
RET
;*************************************************************************
;loads a byte FROM P1 in DISPLAY port.
;*************************************************************************
LOAD_DISP:
SETB DISP_LATCH ;latch the byte in Display latch
NOP
CLR DISP_LATCH
RET
;**************************************************************************
;Displays input gain settings(0 - 15) on LED Display
;destroys A,CY,P1
;**************************************************************************
DISP_GAIN:
MOV A,GAIN
ACALL HEXBCD ;convert to BCD
MOV P1,A
ANL A,#0F0H ;clear low nibble
JNZ LDGAIN
ORL P1,#0F0H ;set illegal BCD to supress leading zero
LDGAIN:
ACALL LOAD_DISP
RET
;**************************************************************************
;Displays volume (1-80)settings on LED Display
;Entry: B=setting value & ACC=max value for the setting(4F/2F)
;destroys A,CY,P1,B
;**************************************************************************
DISP_VOL:
MOV A,#050H
MOV B,R_ATTN
CLR C
SUBB A,B
ACALL HEXBCD
MOV P1,A
JNZ LDVOL
LDVOL:
ACALL LOAD_DISP
RET
;**************************************************************************
;Displays attenuation (0-47)settings on LED Display
;destroys A,P1
;**************************************************************************
DISP_ATT:
MOV A,VOLUME
ACALL HEXBCD
MOV P1,A
JNZ LDATT
48
LDATT:
ACALL LOAD_DISP
RET
;**************************************************************************
;Displays bass/middle/treble settings(07-00-0-7) on LED Display.
;called with bass/middle/treble settings in B register
;destroys A,P1,CY,B
;**************************************************************************
DISP_AUD:
JB B.3,GT8
MOV A,#07H ;if settings less than 8H, subtract from 07H
CLR C
SUBB A,B
ACALL HEXBCD ;do not supress leading zero => CUT
AJMP LDDSPL
GT8: ;if settings greater than 8H, subtract from 0FH
MOV A,#0FH
CLR C
SUBB A,B
ACALL HEXBCD
ORL A,#0F0H ;set illegal BCD to supress leading zero=>BOOST
LDDSPL:
MOV P1,A
ACALL LOAD_DISP
RET
; END OF DISPLAY ROUTINES
; COMMAND & KEY DECODING ROUTINES

;*************************************************************************
; Bass_Middle_Treble Up, used by DO_VOL_UP routine
;*************************************************************************
B_M_T_UP:
CJNE A,#07H,NE7_BMTUP
MOV A,#0FH
RET
NE7_BMTUP:
JNC GT7_BMTUP
INC A
RET
GT7_BMTUP:
CJNE A,#08H,NE8_BMTUP
RET ; Setting already maximum
NE8_BMTUP:
DEC A
RET
;*************************************************************************
; Bass_Middle_Treble Down, used by DO_VOL_DN routine
;*************************************************************************
B_M_T_DN:
JNZ NE0_BMTDN
RET ; Already minimum, do nothing
NE0_BMTDN:
JB ACC.3,GT7_BMTDN
DEC A ; Decrement if less than 7
RET
49
GT7_BMTDN:
CJNE A,#0FH,LT15_BMTDN
MOV A,#07H
RET
LT15_BMTDN:
INC A ; Increment if less than 15
RET
;*************************************************************************
; Process VOL_UP command
;*************************************************************************
DO_VOL_UP:
JNB GAIN_ON,FUN_UP
CALL DO_GAIN_UP
JMP DONE_VUP
FUN_UP:
MOV A,LED_STATUS
ANL A,#0FH ;CLEAR HIGH NIBBLE (LOW NIBBLE = FUNCTION DISPLAY)
CHECK_VOL_UP:
JNZ CHECK_BAS_UP ; Increase VOL IF ACC=0
MOV A,R_ATTN ;PROCESS RIGHT CHANNEL
JZ DONE_VUP ; Attenuation already 0dB, do nothing
DEC A ; Volume UP
MOV AUDIODATA,A
MOV SUBADDR,#06H
CALL SET_AUDIO
JC DONE_VUP
MOV R_ATTN, AUDIODATA
MOV A,L_ATTN ;PROCESS LEFT CHANNEL
JZ DONE_VUP ; Attenuation already 0dB, do nothing
DEC A ; Volume UP
MOV AUDIODATA,A
MOV SUBADDR,#07H
CALL SET_AUDIO
JC DONE_VUP
MOV L_ATTN,AUDIODATA
CALL DISP_VOL ; UPDATE LED DISPLAY
AJMP DONE_VUP
CHECK_BAS_UP: ; Increment BASS
CJNE A,#01H,CHECK_MID_UP
MOV A, BASS
CALL B_M_T_UP
MOV B,A ;used by DISP_AUD
MOV SUBADDR,#03H
MOV AUDIODATA,A
CALL SET_AUDIO ; Change audio settings
JC DONE_VUP
MOV BASS, AUDIODATA ;Update RAM
CALL DISP_AUD ;B-reg already contains display settings
AJMP DONE_VUP
CHECK_MID_UP: ; Increment MIDDLE
CJNE A,#02H,CHECK_TRE_UP
MOV A, MIDDLE
CALL B_M_T_UP
MOV SUBADDR,#04H
50
MOV AUDIODATA,A
CALL SET_AUDIO ;Change audio settings
JC DONE_VUP
MOV MIDDLE,AUDIODATA ;Update RAM
AJMP DONE_VUP
CHECK_TRE_UP: ; Increment TREBLE
CJNE A,#04H,CHECK_ATT_UP
MOV A,TREBLE
CALL B_M_T_UP
MOV SUBADDR,#05H
MOV AUDIODATA,A
JC DONE_VUP
MOV TREBLE,AUDIODATA ;Update RAM
AJMP DONE_VUP
CHECK_ATT_UP:
CJNE A,#08H,DONE_VUP
MOV A,VOLUME
CJNE A,#02FH,NE2FVOL
AJMP DONE_VUP ;Already max attenuation
NE2FVOL:
JNC DONE_VUP ;Already max attenuation/Mute
INC A
MOV AUDIODATA,A
MOV SUBADDR,#02H
CALL SET_AUDIO
JC DONE_VUP ;UPDATE DISPLAY
MOV VOLUME,AUDIODATA
CALL DISP_ATT
DONE_VUP:
RET
;*************************************************************************
; Process VOL_DN command
;*************************************************************************
DO_VOL_DN:
JNB GAIN_ON,FUN_DN
CALL DO_GAIN_DN
JMP DONE_VUP
FUN_DN:
MOV A,LED_STATUS
ANL A,#0FH ;CLEAR HIGH NIBBLE (LOW NIBBLE = FUNCTION DISPLAY)
CHECK_VOL_DN:
JNZ CHECK_BAS_DN ; Decrease VOL IF ACC=0
MOV A,R_ATTN ;PROCESS RIGHT CHANNEL
CJNE A,#04FH,RV_DN
AJMP DONE_VDN ;Attenuation already -79dB, do nothing
RV_DN:
INC A ;Volume DOWN
MOV AUDIODATA,A
MOV SUBADDR,#06H
CALL SET_AUDIO
JC DONE_VDN
51
MOV R_ATTN,AUDIODATA ;Save settings to RAM

MOV A,L_ATTN ;PROCESS LEFT CHANNEL
CJNE A,#04FH,LV_DN
AJMP DONE_VDN ;Attenuation already -79dB, do nothing
LV_DN:
INC A ;Volume DOWN
MOV AUDIODATA,A
MOV SUBADDR,#07H
CALL SET_AUDIO
JC DONE_VDN
MOV L_ATTN,AUDIODATA ;Save settings to RAM
; ;UPDATE LED DISPLAY
CALL DISP_VOL
AJMP DONE_VDN
CHECK_BAS_DN: ; Decrement BASS
CJNE A,#01H,CHECK_MID_DN
MOV A,BASS
CALL B_M_T_DN
MOV SUBADDR,#03H
MOV AUDIODATA,A
JC DONE_VDN
MOV BASS,AUDIODATA ;Update RAM
AJMP DONE_VDN
CHECK_MID_DN: ; Decrement MIDDLE
CJNE A,#02H,CHECK_TRE_DN
MOV A,MIDDLE
CALL B_M_T_DN
MOV SUBADDR,#04H
MOV AUDIODATA,A
JC DONE_VDN
MOV MIDDLE,AUDIODATA ;Update RAM
AJMP DONE_VDN
CHECK_TRE_DN: ; Decrement TREBLE
CJNE A,#04H,CHECK_ATT_DN
MOV A,TREBLE
CALL B_M_T_DN
MOV SUBADDR,#05H
MOV AUDIODATA,A
JC DONE_VDN
MOV TREBLE,AUDIODATA ;Update RAM
AJMP DONE_VDN
CHECK_ATT_DN:
CJNE A,#08H,DONE_VDN
MOV A,VOLUME
JZ DONE_VDN ;Already minimum Attenuation
DEC A
52
MOV AUDIODATA,A
MOV SUBADDR,#02H
CALL SET_AUDIO
JC DONE_VDN ;UPDATE DISPLAY
MOV VOLUME,AUDIODATA
CALL DISP_ATT
DONE_VDN:
RET
;*************************************************************************
;Increment Source
;Destroys A,CY
;*************************************************************************
INC_SOURCE:
MOV A,CHANNEL
INC A
JNB ACC.2,ST_SRC
CLR A
ST_SRC: ;Store source
MOV SUBADDR,#00H ;R4=TDA7439 FUNCTION SELECTION BYTE
MOV AUDIODATA,A ;R3=INPUT CHANNEL
CALL SET_AUDIO ;TDA7439 change channel
JC SRC_ERR
MOV CHANNEL,AUDIODATA ;STORE IN RAM
CALL LOAD_SRCD ;update display & GAIN byte
MOV SUBADDR,#01H ;R4=TDA7439 FUNCTION SELECTION BYTE
MOV AUDIODATA,GAIN ;R3=INPUT GAIN
CALL SET_AUDIO ;TDA7439 change gain settings
SRC_ERR:
RET
;*************************************************************************
; PROCESS GAIN KEY (TOGGLE)
;*************************************************************************
DO_GAIN:
JB GAIN_ON,OFF_GAIN
SETB GAIN_ON
ANL LED_STATUS,#0F0H
CALL LOAD_LED
CALL DISP_GAIN
RET
OFF_GAIN:
CLR GAIN_ON
CALL DISP_VOL
CALL LOAD_LED
RET
;*************************************************************************
; PROCESS GAIN UP
;*************************************************************************
DO_GAIN_UP:
MOV A,GAIN
CJNE A,#0FH,GAIN_INC
RET ;Already maximum
GAIN_INC:
INC A
MOV AUDIODATA,A
MOV SUBADDR,#01H
53
CALL SET_AUDIO
JC END_GAIN_UP
MOV GAIN,AUDIODATA
CALL UPDATE_GAIN
CALL DISP_GAIN
END_GAIN_UP:
RET
;
;*************************************************************************
; PROCESS GAIN DN
;*************************************************************************
DO_GAIN_DN:
MOV A,GAIN
JZ END_GAIN_DN ;Already minimum
DEC A
MOV AUDIODATA,A
MOV SUBADDR,#01H
CALL SET_AUDIO
JC END_GAIN_DN
MOV GAIN,AUDIODATA
CALL UPDATE_GAIN
CALL DISP_GAIN
END_GAIN_DN:
RET
;*************************************************************************
; MOVE GAIN TO GAIN1/GAIN2/GAIN3/GAIN4 depending on active channel
;*************************************************************************
UPDATE_GAIN:
MOV A,LED_STATUS
ANL A,#0F0H
CJNE A,#010H,CH2
MOV GAIN1,GAIN
RET
CH2: CJNE A,#020H,CH3
MOV GAIN2,GAIN
RET
CH3: CJNE A,#040H,CH4
MOV GAIN3,GAIN
RET
CH4: MOV GAIN4,GAIN
RET
;*************************************************************************
; TOGGLE STANDBY STATUS
;*************************************************************************
TOGGLE_STDBY:
JB STANDBY,STANDBY_OFF
CALL SET_MUTE_ON
SETB STANDBY
CALL SAVE_STATE
MOV R5,#05H ;0.5 Sec Delay
CALL DELAYSEC
MOV P0,#0FFH ;Turn off LEDs
SETB POWER ;Active low
CLR INDICATOR ;Turn on Command Indicator LED
RET
54
STANDBY_OFF:
CLR STANDBY
CLR POWER
CALL LOAD_LED
SETB INDICATOR ;Turn off Command Indicator LED
JNB MUTE,MUTE_OFF
MOV P1,#00H
CALL LOAD_DISP
RET
MUTE_OFF:
MOV R5,#0AH ;1 Sec Delay
CALL DELAYSEC
CALL SET_MUTE_OFF
RET
;*************************************************************************
; TOGGLE MUTE STATUS
;*************************************************************************
DO_MUTE:
JB MUTE,DO_MUTE_OFF ;TURN OFF MUTE
CALL SET_MUTE_ON
JC END_MUTE
SETB MUTE
MOV P1,#00H
CALL LOAD_DISP
RET
DO_MUTE_OFF:
CALL SET_MUTE_OFF
JC END_MUTE
CLR MUTE
CALL DISP_VOL
END_MUTE:
RET
;*************************************************************************
SET_MUTE_ON:
MOV AUDIODATA,#078H ;MUTE
MOV SUBADDR,#06H ;RIGHT CHANNEL
CALL SET_AUDIO
JC END_MUTE_ON
MOV SUBADDR,#07H ;LEFT CHANNEL
CALL SET_AUDIO
END_MUTE_ON:
RET
;*************************************************************************
SET_MUTE_OFF:
MOV AUDIODATA,R_ATTN ;RIGHT CHANNEL VOLUME
MOV SUBADDR,#06H ;RIGHT CHANNEL
CALL SET_AUDIO
JC END_MUTE_OFF
MOV AUDIODATA,L_ATTN ;LEFT CHANNEL VOLUME
MOV SUBADDR,#07H ;LEFT CHANNEL
CALL SET_AUDIO
JC END_MUTE_OFF
MOV AUDIODATA,VOLUME ;ATTNEUATION
MOV SUBADDR,#02H
CALL SET_AUDIO
55
END_MUTE_OFF:
RET
;*************************************************************************
; IMPLEMENTS REMOTE COMMANDS
;*************************************************************************
DO_COM:
MOV R0,COMMAND
CALL DO_COMMAND
CLR NEW_COM
RET
;*************************************************************************
; IMPLEMENTS KEYPAD COMMANDS
;*************************************************************************
DO_KEY:
MOV R0,KEY
CALL DO_COMMAND
CLR NEW_KEY
RET
;*************************************************************************
; IMPLEMENTS KEYPAD/REMOTE COMMANDS
;*************************************************************************
DO_COMMAND:
CHECK_STANDBY: ;check if STANDBY pressed
CJNE R0,#STDBY,CHECK_V_UP
JB REPEAT,END_COMMAND ;No contineous-key-press
CALL OFF_GAIN
CALL TOGGLE_STDBY
AJMP END_COMMAND
CHECK_V_UP: ;check if VOL_UP pressed
JB STANDBY,END_COMMAND ;If in standby do nothing
CJNE R0,#VOL_UP,CHECK_V_DN
CALL DO_VOL_UP
AJMP END_COMMAND
CHECK_V_DN: ;check if VOL_DN pressed
CJNE R0,#VOL_DN,CHECK_SEL
CALL DO_VOL_DN
AJMP END_COMMAND
CHECK_SEL: ;check if SEL pressed
CJNE R0,#SEL,CHECK_SOURCE
JB REPEAT,END_COMMAND
CALL OFF_GAIN
CALL INC_SELD ;Increment function selection
AJMP END_COMMAND
CHECK_SOURCE: ;check if SOURCE pressed
CJNE R0,#SOURCE,CHECK_GAIN
CALL OFF_GAIN
CALL INC_SOURCE
AJMP END_COMMAND
CHECK_GAIN: ;check if GAIN pressed
CJNE R0,#INGAIN,CHECK_MUTE
CALL DO_GAIN
AJMP END_COMMAND
CHECK_MUTE: ;check if MUTE pressed
56
CJNE R0,#MUT,END_COMMAND
CALL OFF_GAIN
CALL DO_MUTE
END_COMMAND:
CALL INIT_TIMER1
RET
;*************************************************************************
INIT_TIMER1:
CLR TR1
MOV T1_COUNT,#01H
MOV TH1,#00H
MOV TL1,#00H
SETB TR1
CLR INDICATOR ;Turn on INDICATOR LED
RET
; END OF COMMAND & KEY DECODING ROUTINES
;
TIMER1 INTERRUPT HANDLER ROUTINE
; Volume function (default) selected if T1 is running for 4Sec+.
; Keeps source display flashing if GAIN_ON is set.
INTR_T1:
PUSH IE
CLR EA ;disable interrupts
CLR TR1 ;stop timer temporarily
PUSH ACC
PUSH PSW
MOV A,T1_COUNT
CJNE A,#066H,NE66T1
MOV T1_COUNT,#01H
ANL LED_STATUS,#0F0H ;Function select = Volume
CLR GAIN_ON
CALL DISP_VOL
CALL LOAD_LED
JNB STANDBY,END_INT_T1
MOV P0,#0FFH
AJMP END_INT_T1
NE66T1:
MOV TH1,#015H ;T1 reload value =65535-60000=5535D=159FH
MOV TL1,#09FH ;T1 overflow every 60mS
INC T1_COUNT
SETB TR1
CJNE A,#01H,NE01T1
CLR INDICATOR ;Turn on Command Indicator LED
AJMP FLASH_DISP
NE01T1:
JB STANDBY,FLASH_DISP
SETB INDICATOR ;Turn off Command Indicator LED
FLASH_DISP:
JNB GAIN_ON,END_INT_T1
ANL A,#07H ;Clear A except last 3 bits
JNZ MULTIPLE_4
MOV P0,#0FFH ;Clear display if multiple of 8
AJMP END_INT_T1
MULTIPLE_4:
57
CLR ACC.2
JNZ END_INT_T1
CALL LOAD_LED ;load led display if multiple of 4
END_INT_T1:
POP PSW
POP ACC
POP IE
RETI
; END OF TIMER1 INTERRUPT HANDLER ROUTINE
;
MAIN ENTRY ROUTINE
; START:
;*************************************************************************
; REGISTER INITIALIZATION
;*************************************************************************
MOV SP,#STACKBASE ;stack base address
CLR A
MOV TCON,A
MOV PSW,A
MOV IE,A ;Disable Interrupts
MOV T1_COUNT,A
MOV TMOD,#011H ;T1 & T0 IN 16-bit MODE1, GATEx=0 & CTx=0
CLR TR1
SETB TR0 ;START TIMER TO REJECT FIRST TRANSMISSION
SETB SDA ;I2C Initialize
SETB SCL
SETB POWER ;Standby on (active low)
SETB MONITOR ;Power monitor as input(active low)
CLR REPEAT
CLR NEW_COM
CLR NEW_KEY
CLR DISP_LATCH
CLR GAIN_ON
INIT: ;INITIALIZATION STARTS HERE
CLR C
;*************************************************************************
; STANDBY & MUTE INITIALIZATION
;*************************************************************************
CLR A
MOV ADDR,#00H ;READ STANDBY STATUS
ACALL READ_RANDOM
JC INIT ;RETRY
RRC A ;move LSB into CY bit
MOV STANDBY,C ;store standby status in RAM
RRC A
MOV MUTE,C ;store mute status in RAM
;*************************************************************************
; AUDIO PARAMETERS INITIALIZATION
;*************************************************************************
; Read 8 bytes (01H to 0CH) sequentially from 24Cxx and move to
; internal RAM locations 024H to 02FH
;*************************************************************************
CALL INIT_MEM
JC INIT
;*************************************************************************
58
;Validity check of memory data bytes

;*************************************************************************
VAL_CH: MOV A,CHANNEL
CJNE A,#04H,NE04V
NE04V: JC VAL_G1
MOV CHANNEL,#03H ;Select IN1
VAL_G1: MOV A,GAIN1
CJNE A,#010H,NE10G1
NE10G1: JC VAL_G2
MOV GAIN1,#00H ;GAIN1 = 0
VAL_G2: MOV A,GAIN2
CJNE A,#010H,NE10G2
NE10G2: JC VAL_G3
VAL_G3: MOV A,GAIN3
CJNE A,#010H,NE10G3
NE10G3: JC VAL_G4
VAL_G4: MOV A,GAIN4
CJNE A,#010H,NE10G4
NE10G4: JC VAL_ATT
VAL_ATT: MOV A,VOLUME
CJNE A,#030H,NE30ATT
NE30ATT: JC VAL_BAS
MOV VOLUME,#00H ;ATTN = 0
VAL_BAS: MOV A,BASS
CJNE A,#010H,NE10BAS
NE10BAS: JC VAL_MID
MOV BASS,#07H ;BASS = 0
VAL_MID: MOV A,MIDDLE
CJNE A,#010H,NE10MID
NE10MID: JC VAL_TRE
MOV MIDDLE,#07H ;VOICE = 0
VAL_TRE: MOV A,TREBLE
CJNE A,#010H,NE10TRE
NE10TRE: JC VAL_VOL
MOV TREBLE,#07H ;TRE = 0
VAL_VOL: MOV A,R_ATTN
CJNE A,#050H,NE50VOL
NE50VOL: JC VAL_LEFT
MOV R_ATTN,#04FH ;VOL = 0
VAL_LEFT: MOV L_ATTN,R_ATTN ;Remove if balance adj added
;**************************************************************************
;initialize LED & Display port.
;**************************************************************************
CALL LOAD_SRCD ;display input channel & function selected->volume
CALL DISP_VOL ;Display volume settings
JNB STANDBY,AUDIO_INIT
MOV P0,#0FFH ;Turn off all LEDs
CLR INDICATOR ;Turn on Command Indicator/Standby LED
JNB MUTE,AUDIO_INIT
MOV P1,#00H ;Display 00 if Mute on
CALL LOAD_DISP
;*************************************************************************
59
; Send audio parameter values to audio processor with incremental bus

; except R & L Volume
;*************************************************************************
AUDIO_INIT:
CALL BITDLY
CALL INIT_AUDIO
JC AUDIO_INIT
MOV C,STANDBY ;<- POWER SHOULD BE ACTIVATED ONLY AFTER AUDIO SET
MOV POWER,C
MOV R5,#014H
CALL DELAYSEC ;2SEC Delay
JB MUTE,GO_EVENTS
JB STANDBY,GO_EVENTS
CALL SET_MUTE_OFF ;Initialize volume
GO_EVENTS:
;*************************************************************************
; WAIT-FOR-EVENTS LOOP
;waits for three events -> power off, key press & remote rx
;*************************************************************************
SETB EX0 ;External Int0 for IR Sensor
SETB ET1 ;Timer1 interrupt
SETB EA ;Enable Interrupts
LOOP:
JB MONITOR,POWER_OFF ;If MONITOR high, go to POWER_OFF (active low)
CALL CHECK_KEY
JB NEW_KEY,GO_KEY
JB NEW_COM,GO_COM
AJMP LOOP
GO_KEY:
CLR EX0 ; disable Int0
CALL DO_KEY ; Process Key
SETB EX0 ; Enable Int0
AJMP LOOP
GO_COM:
CLR EX0 ; disable Int0
CALL DO_COM ; Process Command
SETB EX0 ; Enable Int0
AJMP LOOP
;*************************************************************************
; END OF WAIT-FOR-EVENTS LOOP
;*************************************************************************
;*************************************************************************
; POWER OFF SEQUENCE
;*************************************************************************
POWER_OFF:
CLR EA ; DISABLE INTERRUPTS
JB STANDBY,CONT_OFF ; no need to save settings if already in standby
CALL SAVE_STATE ; save settings to EEPROM
MOV R5,#05H
CALL DELAYSEC ;0.5 Sec delay
JNB MONITOR,GO_EVENTS
;**************************************************************************
;Settings saved on EEPROM. MUTE audio & turn off standby relay
;**************************************************************************
60
CONT_OFF:
CALL SET_MUTE_ON
SETB POWER ;turn off relay (active low)
MOV P0,#0FFH ;turn off LEDs
JB MONITOR,$ ;loop till power goes down or comes on
JMP RESET ;reset device
;**************************************************************************
;######################## THE END #####################################
END
7.7 Hardware Schematic:

7.7(a) Power Supply Unit:
61
Figure 7.1 Hardware schematic of power supply unit
7.7(b) Remote Control Unit:
Figure 7.2 Hardware schematic Remote Control unit
7.7(c) Complete DAP system:
62
Figure 7.3 Hardware schematic of complete DAP system

8. APPLICATIONS
63
• It can be used in place of home audio systems by interfacing with personal computer, CD or
DVD player ,MP3 player, IPOD or Mobile Phones
• For audio processing and recording songs and adding sound effects Digital audio processor
can be helpful.
• For Car music system, DJ systems, Party plots, Marriage Functions etc.
9. CONCLUSION
64
• This audio processor has enhanced features and can be easily customized to meet individual
requirements as it is programmable.
• It is based on a microcontroller and can be used with any NEC-compatible full function IR
remote control.
• The circuit can be easily assembled on any PCB with IC base.
10. FUTURE SCOPE
65
• Number of inputs could be increased by using other microcontroller or an 8255 IC.
• It could be interfaced with woofer systems to get the high quality sound effect.
• It could also be interfaced with the personal computer and used for audio processing & sound
recording purposes.
11. REFRENCES AND BIBLOGRAPHY
66
• Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. Mckinlay.

Second edition, “THE 8051 MICROCONTROLLER AND EMBEDDED SYSTEM”
• K. J. Ayala. Third edition, “The 8051 MICROCONTROLLER”
• General information about digital audio processor:
www.efymag.com
www.efymagonline.com
www.electronicsforu.com
www.alldatasheets.com
www.wikipedia.org
www.google.com
www.finalyearprojects.com
• Tutorial on microcontroller:
www.8051projects.net/microcontroller_tutorials/
67

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DIGITAL AUDIO PROCESSOR USING AT89C51

This report presents an infrared (IR) remote-controlled digital audio processor.

Its main features are:

1. Full remote control using any NEC-compatible IR remote control handset.

4. Bass, midrange, treble, mute and attenuation control.

7. Stereo VU level indication on 10-LED bar display.

8. Full-function keys on-board for audio amplifier control.

9. All settings stored on the EEPROM.

10. Standby mode for amplifier power control.

The key features of microcontrollers include:

 High Integration of Functionality

Most microcontrollers will also combine other devices such as:

Fig 2.2 Block Diagram of Microcontroller

2.2 Pin Description:

Table 1:Port 3 Alternate Functions

2.3 Microcontrollers versus Microprocessors:

2.4 Memory unit:

Figure2.2: Simplified model of a memory unit

The amount of memory contained within a microcontroller varies between different

2.5 Central Processing Unit:

Figure2.3: Simplified central processing unit with three registers

2.7 Input-output unit:

Figure2.5: Simplified input-output unit communicating with external world

2.8 Serial communication:

Figure2.6: Serial unit sending data through three lines only

2.9 Timer unit:

Figure2.7: Timer unit generating signals in regular time intervals

Figure3.1: Showing EEPROM of Atmel

3.2 Application/ Operation of EEPROM:

• VCR programming information or data

The EEPROM IC in Computer Monitor performs two tasks: -

Typical EEPROM part numbers are: -

4. INTRODUCTION TO AUDIO PROCESSOR

4.1 Pin Diagram:

Fig 4.1 pin diagram

4.3 Application Suggestions:

4.3.1 Bass, Middle Stages:

Fig. 4.2 T Type Band pass Filter

4.3.2. Treble Stage:

4.4 I2C Bus Interface:

4.4.1 Data Validity

4.4.2 Start and Stop Conditions

4.4.3 Byte Format

4.4.5 Transmission without Acknowledge

4.5 Software Specification:

5. INTRODUCTION TO I2C BUS

5.2 Inside the Box :

Figure5.1:I2C has two lines in total

Figure5.2: I2C communication

5.4 A Simple Bus:

5.5 The Elegance of I2C:

Figure 6.1: Block diagram of DAP

6.1 Microcontroller (AT89C51):

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of

The on-chip Flash allows the program memory to be reprogrammed in-system or by a

• 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles

6.1(c) Function Of Microcontroller:

6.2 The Audio Processor (TDA7439):

6.3 Memory (MC24C02):

6.4 7-segment decoder/driver (CD4543B):

It is a BCD-to-seven segment latch/decoder/driver designed primarily for liquid-crystal display

6.5 2-Channel level meter driver: (KA2281):