ECE 474A/57A

Computer-Aided Logic Design

Lecture 6
Algorithmic State Machines (ASMs)

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Susan Lysecky

Control and Datapath Interaction

ƒ Binary information in digital system Input data

can be classified into two categories

Control
Signals

ƒ Data Input signal Controller Datapath

(external) (FSM)
ƒ Discrete elements of information Status
manipulated by arithmetic, logic, Signals

shift, and other data processing

ƒ Operations implemented via digital Output
components such as adders, data

decoders, muxes, etc.

ƒ Control
ƒ Provides command signals that
coordinate the execution of various
operations in data section to
accomplish desired task

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Susan Lysecky

What Control Path Implements?

ƒ Sequencing of control signals to execute algorithm implemented by circuit

ƒ Algorithm
ƒ Finite set of instructions/steps to solve a problem
ƒ Terminates in finite time at a known end state
ƒ Many representations

Lamp doesn’t
Ingredients work int fib(int n)
ƒ 1/3 cup unsweetened cocoa {
ƒ 1/4 cup cornstarch if (n < 2)
ƒ 2 tablespoons butter
ƒ 2 2/3 cups skim milk No return n;
Lamp plugged Plug in lamp
else
in?
Steps return fib(n-1) + fib(n-2);
Yes }
1. Combine all ingredients in a small saucepan.
2. Heat over low heat, stirring constantly, until Yes
mixture boils. Boil gently, stirring constantly, Bulb burned Replace bulb
for one minute. out?
3. Pour into serving dishes and chill until No
thickened.
Buy new lamp

Recipe Flowchart Computer Program

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Susan Lysecky

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Flowcharts and Algorithmic State Machines (ASM)

ƒ Flowchart
ƒ Convenient way to graphically specify sequence of procedural steps and decision
paths for algorithm
ƒ Enumerates sequence of operations and conditions necessary for execution

ƒ Algorithmic State Machine (ASM)

ƒ Flowchart defined specifically for digital hardware algorithms

ƒ Flowchart vs. ASM

ƒ Conventional flowchart
ƒ Sequential way of representing procedural steps and decision paths for algorithm
ƒ No time relations incorporated
ƒ ASM chart
ƒ Representation of sequence of events together with timing relations between states of
sequential controller and events occurring while moving between steps

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Susan Lysecky

ASM Chart

ƒ Three basic elements

ƒ State box
ƒ Decision box
ƒ Conditional box
ƒ State and decision boxes used in conventional flowcharts
ƒ Conditional box characteristic to ASM

From exit path of decision box

State name Binary code

Register operations Condition Register operations

Moore-type output signals
Mealy-type output signals
Exit path Exit path
Exit path

State Box Decision Box Conditional Box

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Susan Lysecky

State box

ƒ Used to indicate states in control sequence

ƒ State name and binary code placed on top
State name Binary code

of box Register operations

Moore-type output signals
ƒ Register operations and names of output
signals generated in state placed inside box

ƒ Example
ƒ State name: S_pause
ƒ Binary encoding: 0101
ƒ Register operation: R ← 0 S_pause 0101

ƒ Register R is to be cleared to 0 R←0

Start_OP
ƒ Output signal asserted: Start_OP = 1
ƒ Launches some operation in datapath

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Susan Lysecky

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Decision Box

ƒ Reflects the effect of an input

ƒ external or internal, input or status
Condition

ƒ Diamond shaped box Exit path Exit path

ƒ Condition to be tested inside Exit path

ƒ Two or more outputs represent exit paths

dependant on value tested
ƒ In binary case one path represents true the
other false, represented by 1 and 0
respectively
B
1 0

ƒ Example
ƒ Check B
ƒ If B is true (=1), take path marked 1
ƒ If B is false (=0), take path marked 0

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Susan Lysecky

Conditional Box

ƒ Unique to ASM
From exit path of decision box

ƒ Inputs come from one of exit paths of

decision boxes Register operations

ƒ Register operation or outputs listed inside Mealy-type output signals

box generated during given state

ƒ Generated as Mealy-type signals
ƒ Associated with the state transition

ƒ Example
ƒ Status of input B checked B
1 0
ƒ Conditional operation executed depending
on result coming from decision box
ƒ If B = 1, assert Incr_Reg signal Incr_Reg

ƒ Otherwise Incr_Reg remains unchanged

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Susan Lysecky

ASM Block

Structure consisting of
Reset_b
ƒ
ƒ One state box S_0 001

ƒ All decision and conditional boxes A←A+1

associated with its exit paths
ƒ Block has one entrance and any
E
number of exits paths 0 1

ƒ Each block in ASM dedicated to state 0

F
1 Clear_B

of system during one clock cycle

S_1 010 S_2 011 S_3 100

ƒ Simplifications
ƒ ASM Block not usually drawn because
blocks are well defined
ƒ Can label just the “1” and omit the “0”

ƒ ASM chart consists of one or more

interconnect ASM Blocks
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Susan Lysecky

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Interpretation of Timing Operations

Conventional flowchart, evaluation of

Reset_b
ƒ
each follows one another S_0 001
ƒ Reg A incremented A←A+1

ƒ Condition E evaluated
ƒ If E= 1
E
ƒ clear B 0 1

ƒ Go to state S_3 F Clear_B

0 1

ƒ In ASM the entire block considered as S_1 010 S_2 011 S_3 100

one unit
ƒ All operations within block occurring
during single edge transition
ƒ The next state evaluated during the
same clock
ƒ System enters next state S_1, S_2, or
S_3 during transition of next clock

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Susan Lysecky

ASM Example

ƒ Convert pseudo code to ASM chart S0:

busy = 0;
ones = 0;

ƒ Example if(start == 1)
goto S1
ƒ Want to detect the number of 1’s in a 2- else
bit register called Input goto S0
S1:
ƒ start input indicates when to begin busy = 1;
comparison if(Input[1] == 1)
ƒ busy output indicates when comparison in
ones ++;

progress goto S2
ƒ ones hold count value S2:
busy = 1;
ƒ F outputs result if(Input[0] == 1)
ones ++;

goto S3
S3:
busy = 0;
F = ones;

goto S0

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Susan Lysecky

ASM Example Continued

Reset_b
S0:
busy = 0;
S_0 001 ones = 0;
busy = 0
ones = 0 if(start == 1)
goto S1
start == 1 else
goto S0
1 S1:
S_1 010
busy = 1;
if(Input[1] == 1)
busy = 1
ones ++;

Input[1] == 1
1 goto S2
S2:
ones++ busy = 1;
if(Input[0] == 1)
ones ++;
S_2 011
busy = 1 goto S3
S_3 111 S3:
busy = 0 busy = 0;
1
Input[0] == 1
F = ones
F = ones;
ones++
goto S0

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Susan Lysecky

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 ASM – Mux

ƒ Describe a 4x1 MUX using a ASM

S_0 001
x1 x2 x3 x4 s1 s0 f
0 0 x1
1
s0 0 1 2 3 0 1 x2 s1
s1
1 0 x3
1 1 x4 1 1
s0 s0
f

4x1 mux
F = x4 F = x3 F = x2 F = x1

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Susan Lysecky

ASM – Full Adder

ƒ Describe a 1-bit full adder using

an ASM chart

A B S_0 001

cout FA cin
1
a
F
1 1
b b
a b cin f cout
0 0 0 0 0 1 1 1 1
cin cin cin cin
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
f=1 f=0 f=0 f=1 f=0 f=1 f=1 f=0
1 0 0 1 0
cout = 1 cout = 1 cout = 1 cout = 0 cout = 1 cout = 0 cout = 0 cout = 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Susan Lysecky

Smaller Multiplier

ƒ Multiplier in array style

ƒ Fast, reasonable size for 4-bit: 4*4 = 16 partial product AND terms, 3 adders
ƒ Rather big for 32-bit: 32*32 = 1024 AND terms, and 31 adders

32-bit adder would have 1024 gates here

a3 a2 a1 a0

b0
pp4 pp3 pp2 pp1

b1

0 0

b2
+ (5-bit)
00 a
b3
+ (6-bit)
000

+ (7-bit) ... and 31 adders here (big adders)

p7..p0
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 Smaller Multiplier -- Sequential (Add-and-Shift) Style

ƒ Smaller multiplier: Basic idea

ƒ Don’t compute all partial products simultaneously
ƒ Rather, compute one at a time (similar to by hand), maintain running sum

Step 1 Step 2 Step 3 Step 4

0110 0110 0110 0110
+ 0 0 11 + 0 01 1 + 00 1 1 + 0011
(running sum) 0000 00110 010010 0010010
(partial product) + 0 1 1 0 +0 1 1 0 + 0000 + 0000
a
(new running sum) 0 0 1 1 0 010010 0010010 00010010

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Susan Lysecky

Smaller Multiplier -- Sequential (Add-and-Shift) Style

multiplier multiplicand
ƒ Design circuit that computes one
start
partial product at a time, adds to multiplicand
running sum mdld
load
register (4)

ƒ Note that shifting running sum

right (relative to partial product)
after each step ensures partial
product added to correct running
sum bits multiplier
controller

mrld register (4)

load
mr3 4-bit adder
mr2
mr1
mr0

rsload
load
rsclear clear running sum
rsshr shr register (8)

Step 1 Step 2 Step 3 Step 4

0110 0110 0110 0110
+ 001 1 + 0011 + 0011 + 0011
0000 00110 010010 0010010 (running sum)
+ 0110 +0110 + 0000 + 0000 (partial product)
product
00110 010010 0010010 0 0 0 1 0 0 1 0 (new running sum)

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Susan Lysecky

Smaller Multiplier -- Sequential (Add-and-Shift) Style

multiplier multiplicand
Step 0
• Set running sum to 0 start
multiplicand
• Load values mdld register (4)
load 0110
Step 1
• Check multiplier bit 0 (mr0)
• mr0=1, add multiplicand to running sum
• Shift running sum right 1 position
multiplier
controller

mrld
load 0011
register (4)
Step 2
mr3 4-bit adder
• Check multiplier bit 1 (mr1)
• mr0=1, add multiplicand to running sum mr2
mr1
• Shift running sum right 1 position mr0

rsload
Step 3 load
rsclear running sum
clear
• Check multiplier bit 2 (mr2) rsshr
• Shift running sum right 1 position
shr 00000000
00010010
00100100
01001000
10010000
00110000
01100000
register (8)

Step 4
• Check multiplier bit 3 (mr3)
• Shift running sum right 1 position
product

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Susan Lysecky

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ASM – Sequential Multiplier
multiplier multiplicand
Reset_b start
multiplicand
mdld register (4)
load
S_0

start multiplier

controller
1
mr1 mrld register (4)
1 load
rsload = 1 mr3 4-bit adder
S_1 mr2
S_4 mr1
mdld = 1 mr0
rsshr = 1
mrld = 1
rsclear = 1 rsload load
1 rsclear clear running sum
mr2 rsshr shr register (8)
S_2
rsload = 1

S_5

mr0
1 rsshr = 1

rsload = 1 product
1
mr3
S_3
rsload = 1
rsshr = 1
S_6
rsshr = 1

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Susan Lysecky

ASMs to FSMDs

ƒ Able to convert between formats

ƒ Once we have a FSMD, we’ve already seen how to implement in hardware
Reset_b
S_pause 0101 A1 0101
S_0 001
R←0
A←A+1
Start_OP

1 B 0
0 E 1
Incr_Reg F Clear_B
0 1
S_1 010 S_2 011 S_3 100

S_0 A=A+1
S_pause A1 E’F’
E / Clear_B = 1
R=0 E’F
B B’ / Incr_Reg = 1
Start_OP = 1
S_1 S_2 S_3

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Susan Lysecky

Not Used Much, But …

ƒ There are commerical ASM Editors

ƒ Mentor Graphics
ƒ Summit Design, Inc.
ƒ Others…

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Susan Lysecky