INT. J. ELECTRONICS, 1998, VOL. 85, NO.

1, 55± 60

A class AB CMOS square-rooting circuit

VANCHAI RIEWRUJA² , KONGSAK ANUNTAHIRUNRAT² and

WANLOP SURAKAMPONTORN²

An integrable CMOS square-rooting circuit based on a class AB con® guration is

described. The circuit achieves a wide dynamic range and a wide-band capability.
The accuracy of the circuit is also high over the entire dynamic range. Simulation
and experimental results demonstrating the characteristic of the proposed circuit
are also included.

1. Introduction
A square-rooting circuit is a useful circuit building block used in analogue mea-
surement and instrumentation. For example, it can be used to linearize a signal from
a di€ erential pressure ¯ ow metre, or to calculate the r.m.s. value of an arbitrary
waveform (Doebelin 1990). Usually, one fundamental approach to realize a square-
root function is based on the use of an operational ampli® er (op.-amp. ) attached to a
bipolar transistor to form a log and antilog ampli® er (Millman and Grabel 1992).
This approach provides the logarithmic principle to realize a square-root function.
However, the frequency performance achieved by this circuit is limited by the narrow
bandwidth of an op.-amp. topology. Alternatively, an approach based on the char-
acteristic of the translinear con® guration of bipolar junction transistors, which is
suitable for implementing in monolithic integrated circuit form, has been shown to
realize a square-root function (Toumazou et al. 1990). The advantage of this tech-
nique is a wide bandwidth due to the circuit operating in current mode. In addition,
two approaches have been reported on the realization of a square-root function
using MOS transistors. The ® rst approach is based on the use of weak inverted
MOS transistors (van der Gevel and Kuenen 1994). This approach obtains low
power consumption and low voltage operation. In contrast, the accuracy and the
frequency performance are limited by the small transconductance value of the weak
inverted MOS transistors restriction (Gray and Meyer 1993). The second approach is
based on the use of the second generation current conveyor (CCII) connected with
non-saturated MOS transistors and op.-amp. (Liu 1995). The high-frequency limita-
tion of this approach is due to the ® nite gain bandwidth product of the op.-amp. and
parasitic capacitances of the non-saturated MOS transistors. The purpose of this
paper is to propose a CMOS integrated circuit technique for the realization of a
square-rooting circuit. The circuit consists of a CMOS class AB con® guration, cur-
rent mirrors and current sources. The resulting performances of the circuit have high
accuracy, wide-band capability and wide dynamic range.

Received 28 April 1997: accepted 8 October 1997.

The Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang,
²
Ladkrabang, Bangkok 10520, Thailand.
0020± 7217/98 $12.00 Ñ 1998 Taylor & Francis Ltd.
56 V. Riewruja et al.

2. Circuit description

2.1. Basic principle

Figure 1 shows a CMOS class AB con® guration formed by transistors M1 ± M4 .
The constant current source IB provides the bias current for the circuit. Ideally, it is
required that the transistors M1 and M2 , as well as M3 and M4 , are closely matched
and all the transistors operate in their saturation region. If the input signal current Iin
is applied to the circuit, then the relationship of the current ID2 , ID4 and Iin , since the
currents ID2 and ID4 have the same magnitude, can be expressed as

()
1 /2
ID2 = - ID4 = Iin +4 IB + IB
2
1 2
Iin/ ( 1)

where ID2 and ID4 are the drain currents of the transistors M2 and M4 , respectively.

2.2. Square-rooting circuit

The proposed circuit diagram is shown in ® gure 2. Groups of transistors M5 ± M8
function as a current-mode full-wave recti® er (Wang 1990). If the input signal

Figure 1. CMOS class AB con® guration.

Figure 2. The proposed square rooting circuit.

 Class AB CMOS square-rooting circuit 57

current Iin > 0, the current Iin turns M6 `on’ and’ M5 `o€ ’, thus ID5 = 0 and
ID6 = Iin . For the input signal current Iin < 0, the current Iin will turn M5 `on’ and
M6 `o€ ’, therefore ID5 = Iin and ID6 = 0. The unity gain current mirror M7 ± M8
re¯ ects the current ID5 in order to add to the current ID6 . Thus the current ID9 ,
the sum of ID5 and ID6 , is full-wave recti® ed. The current mirror M9 and M11 re¯ ects
the current |Iin | to the current mirror M12 ± M14 . The current mirrors M9 ± M10 and
M12 ± M13 , which have current gain equal to 4, force the current |4Iin | into the tran-
sistor M3 of a class AB stage and the current source I1 and I2 , which are set equal to
4IB , provide the bias current. The current ID4 can be written as

ID4 = IB + |Iin | + IB / |Iin |

1 2 1 /2
( 2)

where ID4 is the drain current of M4 . The unity gain current mirrors M9 , M11 , M12 ,
M14 and M15 ± M16 re¯ ect the current ID9 = |Iin | and ID4 , respectively, into an output
node, and the current source I3 = IB provides an elimination of the output current
o€ set. Then the output current Iout becomes

Iout = IB / |Iin |
1 2 1 /2
( 3)

which means that the output current Iout is a square-root of the input signal current
1 /2
Iin , with the current gain equal to IB .

3. Circuit performance
In practical realization, the device mismatch between n and p channel MOS
transistors of a class AB circuit is the major factor that contributes to the errors
from the ideal performance. The error e 1 of the output current Iout is due to the
cancelling remainder current of the signal current Iin and the current ID16 . The
percentage of error e 1 can be expressed as

( b n b p IB ) 1 /2
e 1 = ´ 100% ( 4)
2( b n + 2( b n b p ) / - 3b p )
1 2

where b n and b p are the transconductance parameters of n and p channel MOS

transistors, respectively, and IB is the bias current of the class AB circuit. If
b n = 4. 919 ´ 10- 4 A V- 2 , b p = 1. 73 ´ 10- 4 A V- 2 and IB = 25 m A, then the result-
ing error e 1 is equal to 0.13%.
For high-frequency response, the ® rst major high-frequency limitation is due to
the device capacitance of a class AB circuit (M1 ± M4 ). The single dominant pole PAB
of a class AB circuit can be approximately given by
1
PAB = ( 5)
[ 1+
C1 s
gm 1 ]
where gm 1 and C1 are the MOSFET transconductance and the gate-to-source
capacitance of the transistor M1 , respectively. If C1 = 0. 2 pF, gm 1 = 2. 21 ´ 10-
4

A/V, then this pole will be located at 175.86 MHz. The second dominant pole Pm
is due to the bandwidth of the negative current mirror M12 ± M14 , which can be
58 V. Riewruja et al.

written as

1
Pm = ( 6)
[ 1+
C12 s
gm 12 ]
where gm 12 and C12 are the MOSFET transconductance and the gate-to-source
capacitance of the transistor M12 , respectively. For C12 = 1. 5 pF and gm 12 =
2. 68 ´ 10- A/V, then the cut-o€ frequency of this pole is located at about 28.43
4

MHz. This pole should be the high-frequency limitation of the circuit.

4. Experimental and simulation results

The circuit in ® gure 2 has been constructed using CD4007 devices for experi-
mental purposes, where the bias current I1 = I2 = 4IB and the current source I3 = IB
are set to 100 m A and 25 m A, respectively, and V DD = 7 V. Figure 3 shows the mea-
sured DC transfer characteristic for the input current Iin which is varied from - 1 mA
to 1 mA. Figure 4 shows the output current waveform for a 20 kHz triangular wave
input waveform of peak amplitude 1 mA. It is evident that the performance of the
experimental circuit is in close agreement with the expected value.
The high-frequency response of the proposed circuit was observed using the
PSPICE analogue simulation program. The MOSIS 2.0 m m CMOS process para-
meters were used for the circuit simulation. The ratio of channel widths and lengths
( W / L ) of the devices used are as follows: W 5 / L 5 = W 6 / L 6 = 2 m m/2 m m,
W 10 / L 10 = W 13 / L 13 = 80 m m/2 m m, W 1 / L 1 = W 2 / L 2 = W 3 / L 3 = W 4 / L 4 = 10 m m/
2 m m and the other devices are set identical to 20 m m/2 m m. The simulated frequency
response of the proposed circuit is shown in ® gure 5. It should be noted that the
bandwidth about 32 MHz is observed.

Figure 3. Measured DC transfer characteristic.

 Class AB CMOS square-rooting circuit 59

Figure 4. Triangular wave response of circuit in ® gure 2. Upper trace input: 500 m A div;
lower trace, output: 100 m A div- 1 ; time base 10 m s div- 1 .

Figure 5. Simulated for high-frequency response.

5. Conclusion
A current-controlled square-rooting circuit has been presented in this paper. The
realization method is based on the principle of class AB con® guration and is suitable
for implementation in CMOS integrated circuit form. The experimental results and
the simulation results have shown that the circuit performance is highly accurate and
has wide-band capability.

ACKNOWLEDGMENTS
The authors would like to express sincere gratitude to the National Science and
Technology Development Agency (NASTDA), Thailand, for the ® nancial support
of this work.
60 Class AB CMOS square-rooting circuit

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