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6. Why do we need both PMOS and NMOS transistors to implement a pass gate?
12. Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
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15. While using logic design, explain the various steps that r followed to obtain the desirable
20. For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
23. A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW
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28. Implement a function with both ratioed and domino logic and merits and demerits of
each logic?
29. Given a circuit and asked to tell the output voltages of that circuit?
30. How can you construct both PMOS and NMOS on a single substrate?
34. What is pipelining and how can we increase throughput using pipelining?
35. Explain about stuck at fault models, scan design, BIST and IDDQ testing?
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40. Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and
42. If the current thru the poly is 20nA and the contact can take a max current of 10nA how
47. Differences between Signals and Variables in VHDL? If the same code is written using
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56. Explain the various Capacitances associated with a transistor and which one of them is the
most prominent?
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66. What r the phenomenon which come into play when the devices are scaled to the sub-
micron lengths?
71. If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
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73. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
74. Which gate is normally preferred while implementing circuits using CMOS logic, NAND or
NOR? Why?
78. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per
stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this
machine ?
80. For a single computer processor computer system, what is the purpose of a processor cache
and describe its operation?
81. Explain the operation considering a two processor computer system with a cache for each
processor.
82. What are the main issues associated with multiprocessor caches and how might you solve
them?
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83. Explain the difference between write through and write back cache.
86. Describe a finite state machine that will detect three consecutive coin tosses (of one coin)
that results in heads.
87. In what cases do you need to double clock a signal before presenting it to a synchronous
state machine?
88. You have a driver that drives a long signal & connects to an input device. At the input device
there is either overshoot, undershoot or signal threshold violations, what can be done to correct
this problem?
89. What are the total number of lines written by you in C/C++? What is the most
complicated/valuable program written in C/C++?
93. What types of CMOS memories have you designed? What were their size? Speed?
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94. What work have you done on full chip Clock and Power distribution? What process
technology and budgets were used?
95. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage
requirements?
96. Process technology? What package was used and how did you model the package/system?
What parasitic effects were considered?
97. What types of high speed CMOS circuits have you designed?
98. What transistor level design tools are you proficient with? What types of designs were they
used on?
99. What products have you designed which have entered high volume production?
100. What was your role in the silicon evaluation/product ramp? What tools did you use?
101. If not into production, how far did you follow the design and why did not you see it into
production?
# Draw Vds-Ids curve for an MOSFET. How it varies with a) increasing Vgs b)
# What is body effect? Write mathematical expression? Is it due to parallel or serial connection
of MOSFETs?
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# What is latch-up in CMOS design and what are the ways to prevent it?
# Give the various techniques you know to minimize power consumption for CMOS logic?
# What happens when the PMOS and NMOS are interchanged with one another in an inverter?
# How do you size NMOS and PMOS transistors to increase the threshold voltage?
# What are the limitations in increasing the power supply to reduce delay?
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# How does Resistance of the metal lines vary with increasing thickness and increasing length?
# What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?
# Why do we gradually increase the size of inverters in buffer design? Why not give the output
of a circuit to one large inverter?
# What is metastability? When/why it will occur? What are the different ways to avoid this?
# In the I-V characteristics curve, why is the saturation curve flat or constant?
# What happens if a resistor is added in series with the drain in a CMOS transistor?
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# What are the effects of the output characteristics for a change in the beta (β) value?
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# Can both PMOS and NMOS transistors pass good 1 and good 0? Explain.
# What are the different methodologies used to reduce the charge sharing in dynamic logic?
# What are setup and hold time violations? How can they be eliminated?
# Which ones take more time in SRAM: Read operation or Write operation? Why?
# If given a choice between NAND and NOR gates, which one would you pick? Explain.
# Explain the origin of the various capacitances in the CMOS transistor and the physical
reasoning behind it.
# Why should the number of CMOS transistors that are connected in series be reduced?
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# Draw an XOR gate with using minimum number of transistors and explain the operation.
# What are the advantages of depletion mode devices over the enhancement mode devices?
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# What are the substrates of PMOS and NMOS transistors connected to and explain the results if
the connections are interchanged with the other.
# What is the effect of delay, rise and fall times with increase in load capacitance?
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* Give insights of a 2 input NOR gate. Draw Layout. Explain the working.
# Give insights of a 2 input NAND gate. Draw layout. Explain the working?
# Why do we need both PMOS and NMOS transistors to implement a pass gate?
# What is a D-latch?
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# How can you construct both PMOS and NMOS on a single substrate?
# What is SPICE?
# What r the phenomenon which come into play when the devices are scaled to the sub-micron
lengths?
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# Which gate is normally preferred while implementing circuits using CMOS logic, NAND or
NOR? Why?
# Draw the Differential Sense Amplifier and explain its working. How to size this circuit?
# How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAM’s
performance?
# Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock
signal?
# Give a big picture of the entire SRAM layout showing placements of SRAM cells, row decoders,
column decoders, read circuit, write circuit and buffers.
# In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
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Ans:Pinch off
2. In the I-V characteristics curve, why is the saturation curve flat or constant?
3. What happens if a resistor is added in series with the drain in a mos transistor?
5. What are the effects of the output characteristics for a change in the beta (β) value?
11. What is the effect of temperature on mobility? What is the effect of gate voltage on
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mobility?
16. Can both pmos and nmos transistors pass good 1 and good 0? Explain.
18. What are the different methodologies used to reduce the charge sharing in dynamic logic?
19. What are setup and hold time violations? How can they be eliminated?
21. Of Read and Write operations, which ones take more time? Explain.
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24. If given a choice between NAND and NOR gates, which one would you pick?
Explain.
27. What is meant by noise margin in an inverter? How can you overcome it?
28. Why is size of pmos transistor chosen to be close to three times of an nmos transistor?
29. Explain the origin of the various capacitances in the mos transistor and the physical
reasoning behind it.
30. Why should the number of CMOS transistors that are connected in series be reduced?
33. Two inverters are connected in series. The widths of pmos and nmos transistors of the
second inverter are 100 and 50 respectively. If the fan-out is assumed to be 3, what would be
the widths of the transistors in the first inverter?
34. In the above situation, what would be the widths of the transistors if the first inverter is
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35. What is the difference between a latch and flip-flop? Give examples of the applications of
each.
38. Draw an XOR gate with using minimal number of transistors and explain the operation.
42. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs?
43. What are the advantages of depletion mode devices over the enhancement mode devices?
44. How can the rise and fall times in an inverter be equated?
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50. What are the substrates of pmos and nmos transistors connected to and explain the results if
the connections are interchanged with the other.
53. What is meant by negative biased instability and how can it be avoided?
57. What are the various factors that need to be considered while choosing a technology library
for a design?
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59. When stated as 0.13μm CMOS technology, what does 0.13 represent?
61. What are the various limitations in changing the voltage for less delay?
63. While trying to drive a huge load, driver circuits are designed with number of stages with a
gradual increase in sizes. Why is this done so? What not use just one big driver gate?
64. What is the effect of increase in the number of contacts and vias in the interconnect layers?
65. How does the resistance of the metal layer vary with increasing thickness and increasing
length?
66. What is the effect of delay, rise and fall times with increase in load capacitance?
67. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an nmos and if
the nmos in the Pull-Down Network is replaced by a pmos transistor, will the design work as an
non-inverting buffer? Justify your answer.
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What parameters (or aspects) differentiate Chip Design & Block level design??
Which is more complicated when u have a 48 MHz and 500 MHz clock design?
What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire length?
How will you decide the Pin location in block level design?
If the routing congestion exists between two macros, then what will you do?
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If lengthy metal layer is connected to diffusion and poly, then which one will affect by
antenna problem?
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead
of using 7LM?
In your project what is die size, number of metal layers, technology, foundry, number of
clocks?
How to calculate core ring width, macro ring width and strap or trunk width?
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If in your design 10000 and more numbers of problems come, then what you will do?
If in your design has reset pin, then it’ll affect input pin or output pin or both?
During power analysis, if you are facing IR drop problem, then how did u avoid?
How delays vary with different PVT conditions? Show the graph.
Explain the flow of physical design and inputs and outputs for each step in flow.
What are delay models and what is the difference between them?
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Why higher metal layers are preferred for Vdd and Vss?
What is core and how u will decide w/h ratio for core?
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How the width of metal and number of straps calculated for power and ground?
What is congestion?
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How slow and fast transition at inputs effect timing for gates?
What is the difference between core filler cells and metal fillers?
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What is LEF?
What is DEF?
* What are the steps that you have done in the design flow?
* How much aspect ratio should be kept (or have you kept) and what is the utilization?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup and hold violates?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps.
Then what is the maximum operating frequency?
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* What is ESD?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns
insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
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