Lect 2

VHDL Basics
Teemu Pitkänen
Teemu.pitkanen@tut.fi
TH318
(03) 3115 4778
TKT-1210 Digitaldesign II, Lect 2 1 Tampere University of Technology

© Teemu Pitkänen (teemu.pitkanen.tut.fi) Institute of Digital and Computer Systems
Outline
Motivation
Design environment
Design units
Design description styles
Processes
Signals, variables
Types
Attributes
Statements
Subprograms and packages

Why (V)HDL?
Interoperability
Technology independence
Design reuse
Several levels of abstraction
Readability
Standard language
Widely supported
• ...
=> Improved productivity

What is VHDL?
VHDL = VHSIC Hardware Description Language
(VHSIC = Very High-Speed IC)
Design specification language

Design entry language
Design simulation language
Design documentation language
An alternative to schematics

A Brief History
Was developed in the early 1980s for managing
design problems that involved large circuits and
multiple teams of engineers.
Funded by U.S. Department of Defence.
The first publicly available version was released in
1985.
In 1986 IEEE (Institute of Electrical and Electronics
Engineers, Inc.) was presented with a proposal to
standardize the VHDL.
In 1987 standardization => IEEE 1076-1987
An improved version of the language was relased in
1994 => IEEE standard 1076-1993.

Related Standards
IEEE 1076 doesn’t support simulation conditions
such as unknown and high-impedance.
Soon after IEEE 1076-1987 was released, simulator
companies began using their own, non-standard
types => VHDL was becoming a nonstandard.
IEEE 1164 standard was developed by an IEEE.
IEEE 1164 contains definitions for a nine-valued data
type, std_logic.
IEEE 1076.3 (Numeric or Synthesis Standard) defines
data types as they relate to actual hardware.
Defines, e.g., two numeric types: signed and
unsigned.

VHDL Environment

When not Use VHDL?
No time to learn?
– VHDL is large and quite complex language.
– But, there is no need to learn all of its features at the
start.
No money for tools?
– The most popular tools are still quite expensive.
EDA tools have no common standard.
– Results can vary when a simulator or a synthesis tool is
changed.

Design Units
Segments of VHDL code that can be compiled
separately and stored in a library.

Entities
A black box with interface definition.
Defines the inputs/outputs of a component (define
pins)
A way to represent modularity in VHDL.
Similar to symbol in schematic.
Entity declaration describes entity.
entity Comparator is
port ( A, B : in std_logic_vector(7 downto 0);
EQ : out std_logic);
end Comparator;

Ports
Provide channels of communication between the
component and its environment.
Each port must have a name, direction and a type.
An entity may have NO port declaration
Port directions:
– in: A value of a port can be read inside the component,
but cannot be assigned. Multiple reads of port are
allowed.
– out: Assignments can be made to a port, but data from
a port cannot be read. Multiple assignments are
allowed.
– inout: Bi-directional, assignments can be made and
data can be read. Multiple assignments are allowed.
– buffer: An out port with read capability. May have at
most one assignment. (are not recommended)
Architectures
architecture Comparator1 of Comparator is
begin
EQ <= ’1’ when (A=B) else ’0’;
end Comparator1;

Architectures
Every entity has at least one architecture.
One entity can have several architectures.
Architectures can describe design using:
– Behaviour
– Structure
– Dataflow
Architectures can describe design on many levels
– Gate level
– RTL (Register Transfer Level)
– Behavioural level
Configuration declaration links architecture to entity.

Configurations
Links entity declaration and architecture body
together.
Concept of default configuration is a bit messy in
VHDL ‘87.
– Last architecture analyzed links to entity?
Can be used to change simulation behaviour without
re-analyzign the VHDL source.
Complex configuration declarations are ignored in
synthesis.
Some entities can have, e.g., gate level architecture
and behavioral architecture.
Are always optional.

Packages
Packages contain information common to many
design units.
1. Package declaration
– constant declarations
– type and subtype declarations
– function and procedure declarations
– global signal declarations
– file declarations
– component declarations
2. Package body
– is not necessary needed
– function bodies
– procedure bodies

Packages
package PackageExample is
constant ExampleConstant : std_logic := ’1’;
function IntegerToVector (Size : integer; Number :
integer)
return std_logic_vector;
end PackageExample;
package body PackageExample is

function IntegerToVector (Size : integer; Number :
integer)
return std_logic_vector is
end IntegerToVector;
end PackageExample;
Packages
Packages are meant for encapsuling data which can
be shared globally among several design units.
Consists of declaration part and optional body part.
Package declaration can contain:
– subprograms
– constants, alias declarations
– global signal declarations
– component declarations
Package body consists of
– subprogram declarations and bodies
– deferred constants
Packages
The second package declaration example:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package IoPkg is
CONSTANT AddWidth: NATURAL := 16;
CONSTANT DataWidth: NATURAL := 16;
CONSTANT Stat : NATURAL := 1;
CONSTANT TotalOut: NATURAL := 10;
TYPE OBitsArray is array (0 to TotalOut) of NATURAL;
function INMUX(
Data : STD_LOGIC_VECTOR(TotalWidth-1 downto 0);
sel : NATURAL)
return STD_LOGIC_VECTOR;
end IoPkg;

Libraries
Collection of VHDL design units (database).
– 1. Packages
• package declaration
• package body
– 2. Entities (entity declaration)
– 3. Architectures (architecture body)
– 4. Configurations (configuration declarations)
Usually directory in Unix file system.
Can be also any other kind of database.

Block Statement
Partitioning mechanism that allows design to group
logically areas of design
architecture behav of CPU is

begin
ALU:block
begin
statements
end block ALU;
REGS:block
begin
statements
end block REGS;
end behav;

Guarded Block
A block containing boolean expression which can
enable and disable driver inside block
architecture behav of guarded_latch is

begin
atch:block(clk = ‘1’)
begin
q <= guarded d after 3ns;
qn <= guarded not(d) after 5;
end block latch;
end guarded_latch
Not synthesizable.

Levels of Abstraction
VHDL supports many possible styles of design
description, which differ primarily in how closely they
relate to the HW.
It is possible to describe a circuit in a number of
ways.
Structural
Dataflow Higher level of abstraction
Behavioral

Structural VHDL description
Circuit is described in terms of its components.
From a low-level description (e.g., transistor-level
description) to a highlevel description (e.g., block
diagram).
For large circuits, a low-level descriptions quickly
become impractical.
An example:
entity AndGate is
port(A, B, C, D : in std_logic;
Y : out std_logic);
end AndGate;
entity Tff is
port(Rst, Clk, T : in std_logic;
Q : out std_logic);
end Tff;
Structural VHDL description
entity TCount is
port(Rst, Clk : in std_logic;
Count : out std_logic_vector(4 downto 0));
end TCount;
architecture Structural of TCount is

begin
component Tff
port(Rst, Clk, T : in std_logic;
Q : out std_logic);
end component;
component AndGate
port(A, B, C, D : in std_logic;
Y : out std_logic);
end component;
...
end Structural;

Dataflow VHDL Description
Circuit is described in terms of how data moves
through the system.
In the dataflow style you describe how information
flows between registers in the system.
The combinational logic is described at a relatively
high level, the placement and operation of registers
is specified quite precisely.
The behaviour of the system over the time is defined

by registers.
Dataflow VHDL Description
There are no build-in registers in VHDL-language.
– Either lower level description
– or behavioral description of sequential elements is
needed.
The lower level register descriptions must be created
or obtained.
If there is no 3rd party models for registers => you
must write the behavioral description of registers.
The behavioral description can be provided in the
form of subprograms (functions or procedures)

Behavioral VHDL Description
Circuit is described in terms of its operation over
time.
Representation might include, e.g., state diagrams,
timing diagrams and algorithmic descriptions.
The concept of time may be expressed precisely
using delays (e.g., A <= B after 10 ns)
If no actual delays is used, order of sequential
operations is defined.
In the lower levels of abstraction (e.g., RTL) synthesis
tools ignore detailed timing specifications.
The actual timing results depend on implementation
technology and efficiency of synthesis tool.
There are a few tools for behavioral synthesis.

Behavioral VHDL Description
case CurrentState is
when WaitForStart =>
if SerEna = ’1’ then
NextOut <= (others => ’0’);
NextState <= ReadBits;
end if;
when ReadBits =>
if CurrentBitPos = OutWidth then
NextState <= OutputReady;
ParReady <= ’1’;
else
NextOut(CurrentBitPos) <= Serial;
NextBitPos <= CurrentBitPos+1;
end if;
when OutputReady =>
NextState <= WaitForStart;
ParReady <= ’1’;
end case;
Concurrent vs. Sequential VHDL

Concurrent vs. Sequential VHDL
architecture ConcurrentAndSequential of Rotate is
signal QReg : std_logic_vector(7 downto 0);
begin
Reg : process(Rst, Clk)
begin
if (Rst = ’1’) then
QReg <= "00000000";
Concurrent elsif (Clk = ’1’ and Clk’event) then
if (Load = ’1’) then
Sequential
QReg <= Data;
else
QReg <= QReg(6 downto 0) & QReg(0);
end if;
end if;
end process;
Q <= QReg;
end ConcurrentAndSequential;
Processes
Basic simulation concept in VHDL.
VHDL description can always be broken up to
interconnected processes.
Quite similar to Unix process.
Process keyword in VHDL.

Processes
Process statement is concurrent statement.
Statements inside process statements are sequential
statements.
Process must contain either sensitivity list or wait
statement(s), but NOT both.
Sensitivity list or wait statement(s) contains signals
which wakes process up.
General format:
process[(sensitivity_list)]
process_declarative_part
begin
process_statements
[wait_statement]
end process;

Processes
Process with sensitivity list:
process(a,b)
begin
c <= a and b after 5 ns;
end process;
Process with wait statement:
process
begin
c <= a and b after 5 ns;
wait on a,b;
end process;
Process with incomplete sensitivity list:
process(a)
begin
c <= a and b;
end process;
Processes
Sequential signal assigment in a process.
entity Pitfall1 is
end Pitfall1;
architecture Ups of Pitfall1 is
signal A, B, C : std_logic;
begin -- Ups
A <= ’1’ after 5 ns,
’0’ after 15 ns,
’1’ after 25 ns;
B <= ’1’ after 0 ns,
’0’ after 10 ns,
’1’ after 20 ns;
process (A, B)
begin -- process
C <= A;
C <= B;
end process;
end Ups;
Delays
Inertial delay
– intended to model the delay
through a gate
– minimum pulse length that must
maintained before an event is
propagated
c <= a after 5 ns;
Transport delay
– models the delay on a wire
– pulses of any width are
propagated
c <= transport a after 5 ns;

Delays
Delta delay
– A simulation cycle, which occurs in zero simulated time
(the start and end time of the delta cycle are the same
entity rsff is
port (s, r: in bit; q, qn: out bit );
end rsff;
architecture beh of rsff is
begin
q <= s nand qn;-- Executed once in t
qn <= r nand q;-- Executed twice in t
end beh;


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VHDL Basics

TKT-1210 Digitaldesign II, Lect 2 1 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 2 Tampere University of Technology

=> Improved productivity

TKT-1210 Digitaldesign II, Lect 2 3 Tampere University of Technology

 Design specification language

TKT-1210 Digitaldesign II, Lect 2 4 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 5 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 6 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 7 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 8 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 9 Tampere University of Technology

 Similar to symbol in schematic.

 Entity declaration describes entity.

TKT-1210 Digitaldesign II, Lect 2 10 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 12 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 13 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 14 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 15 Tampere University of Technology

package body PackageExample is

TKT-1210 Digitaldesign II, Lect 2 18 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 19 Tampere University of Technology

architecture behav of CPU is

TKT-1210 Digitaldesign II, Lect 2 20 Tampere University of Technology

architecture behav of guarded_latch is

TKT-1210 Digitaldesign II, Lect 2 21 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 22 Tampere University of Technology

architecture Structural of TCount is

TKT-1210 Digitaldesign II, Lect 2 24 Tampere University of Technology

 The behaviour of the system over the time is defined

TKT-1210 Digitaldesign II, Lect 2 26 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 27 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 29 Tampere University of Technology

 Process keyword in VHDL.

TKT-1210 Digitaldesign II, Lect 2 31 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 32 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 35 Tampere University of Technology

TKT-1210 Digitaldesign II, Lect 2 36 Tampere University of Technology

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Design specification language

Similar to symbol in schematic.

Entity declaration describes entity.

The behaviour of the system over the time is defined

Process keyword in VHDL.