Professional Documents
Culture Documents
87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC
*See Table 1 for Proliferation Options
Y High Performance CHMOS Y 32 Programmable I/O Lines
EPROM/ROM/CPU Y 7 Interrupt Sources
Y 12/24/33 MHz Operation Y Four Level Interrupt Priority
Y Three 16-Bit Timer/Counters Y Programmable Serial Channel with:
Y Programmable Counter Array with: Ð Framing Error Detection
Ð High Speed Output, Ð Automatic Address Recognition
Ð Compare/Capture, Y TTL Compatible Logic Levels
Ð Pulse Width Modulator,
Ð Watchdog Timer Capabilities Y 64K External Program Memory Space
Y Up/Down Timer/Counter Y 64K External Data Memory Space
Y Three Level Program Lock System Y MCSÉ 51 Controller Compatible
Instruction Set
Y 8K/16K/32K On-Chip Program Memory
Y Power Saving Idle and Power Down
Y 256 Bytes of On-Chip Data RAM Modes
Y Improved Quick Pulse Programming Y ONCE (On-Circuit Emulation) Mode
Algorithm
Y Extended Temperature Range Except
Y Boolean Processor for 33 MHz Offering ( b 40§ C to a 85§ C)
MEMORY ORGANIZATION
ROM/
ROM EPROM ROMLESS EPROM RAM
Device Version Version Bytes Bytes
For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX,
unless information applies to a specific device.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1996 April 1996 Order Number: 272322-004
8XC51FX
NOTES:
*1 3.5 MHz to 12 MHz; 5V g 20%
-1 3.5 MHz to 16 MHz; 5V g 20%
-2 0.5 MHz to 12 MHz; 5V g 20%
-24 3.5 MHz to 24 MHz; 5V g 20%
-33 3.5 MHz to 33 MHz; 5V g 10%
272322 – 1
2
8XC51FX
272322 – 23
PLCC
272322 – 2
DIP
272322 – 24
*Do not connect Reserved Pins.
QFP
3
8XC51FX
4
8XC51FX
Port 3 also serves the functions of various special When the 8XC51FX is executing code from external
features of the MCS-51 Family, as listed below: Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
Port Pin Alternate Function skipped during each access to external Data Memo-
ry.
P3.0 RXD (serial input port)
P3.1 TXD (serial output port) EA/VPP: External Access enable. EA must be
P3.2 INT0 (external interrupt 0) strapped to VSS in order to enable the device to
P3.3 INT1 (external interrupt 1) fetch code from external Program Memory locations
P3.4 T0 (Timer 0 external input) 0000H to 0FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be inter-
P3.5 T1 (Timer 1 external input)
nally latched on reset.
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe) EA should be strapped to VCC for internal program
executions.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de- This pin also receives the programming supply volt-
vice. The port pins will be driven to their reset condi- age (VPP) during EPROM programming.
tion when a minimum VIH1 voltage is applied wheth-
er the oscillator is running or not. An internal pull- XTAL1: Input to the inverting oscillator amplifier.
down resistor permits a power-on reset with only a
capacitor connected to VCC. XTAL2: Output from the inverting oscillator amplifi-
er.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory. This pin (ALE/PROG) is also the OSCILLATOR CHARACTERISTICS
program pulse input during EPROM programming for
the 87C51FX. XTAL1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
In normal operation ALE is emitted at a constant ured for use as an on-chip oscillator, as shown in
rate of (/6 the oscillator frequency, and may be used Figure 3. Either a quartz crystal or ceramic resonator
for external timing or clocking purposes. Note, how- may be used. More detailed information concerning
ever, that one ALE pulse is skipped during each ac- the use of the on-chip oscillator is available in Appli-
cess to external Data Memory. cation Note AP-155, ‘‘Oscillators for Microcontrol-
lers.’’
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is To drive the device from an external clock source,
weakly pulled high. However, the ALE disable fea- XTAL1 should be driven, while XTAL2 floats, as
ture will be suspended during a MOVX or MOVC in- shown in Figure 4. There are no requirements on the
struction, idle mode, power down mode and ICE duty cycle of the external clock signal, since the in-
mode. The ALE disable feature will be terminated by put to the internal clocking circuitry is through a
reset. When the ALE disable feature is suspended or divide-by-two flip-flop, but minimum and maximum
terminated, the ALE pin will no longer be pulled up high and low times specified on the data sheet must
weakly. Setting the ALE-disable bit has no affect if be observed.
the microcontroller is in external execution mode.
An external oscillator may encounter as much as a
Throughout the remainder of this data sheet, ALE 100 pF load at XTAL1 when it starts up. This is due
will refer to the signal coming out of the ALE/PROG to interaction between the amplifier and its feedback
pin, and the pin will be referred to as the ALE/PROG capacitance. Once the external signal meets the VIL
pin. and VIH specifications the capacitance will not ex-
ceed 20 pF.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
5
8XC51FX
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), ‘‘Designing with the 80C51BH.’’
6
8XC51FX
NOTE:
Contact distributor or local sales office to match EXPRESS prefix with proper device.
EXAMPLES:
P87C51FC indicates 87C51FC in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51FC indicates 87C51FC in a cerdip package and specified for extended temperature range with burn-in.
7
8XC51FX
ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
Ambient Temperature Under Bias À b 40§ C to a 85§ C the devices indicated in the revision history. The
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C specifications are subject to change without notice.
Voltage on EA/VPP Pin to VSS ÀÀÀÀÀÀÀ0V to a 13.0V *WARNING: Stressing the device beyond the ‘‘Absolute
Voltage on Any Other Pin to VSS ÀÀ b 0.5V to a 6.5V Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA ‘‘Operating Conditions’’ is not recommended and ex-
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W tended exposure beyond the ‘‘Operating Conditions’’
(based on PACKAGE heat transfer limitations, not may affect device reliability.
device power consumption)
OPERATING CONDITIONS
Symbol Description Min Max Units
TA Ambient Temperature Under Bias
Commercial 0 a 70
Express b 40 a 85 §C
8
8XC51FX
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may
exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port -
Port 0: 26 mA
Ports 1, 2, and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
272322 – 5
Note:
ICC max at 33 MHz is at 5V g 10% VCC, while ICC max at 24 MHz and below is at 5V g 20% VCC.
9
8XC51FX
272322 – 6 272322 – 7
All other pins disconnected All other pins disconnected
TCLCH e TCHCL e 5 ns TCLCH e TCHCL e 5 ns
Figure 6. ICC Test Condition, Active Mode Figure 7. ICC Test Condition Idle Mode
272322 – 8
All other pins disconnected
272322 – 19
Figure 9. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH e TCHCL e 5 ns.
10
8XC51FX
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF)
11
8XC51FX
12
8XC51FX
272322 – 9
272322 – 10
272322 – 11
13
8XC51FX
272322 – 12
14
8XC51FX
272322 – 13
272322 – 14 272322 – 15
AC Inputs during testing are driven at VCC b 0.5V for a Logic ‘‘1’’ For timing purposes a port pin is no longer floating when a
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at VIH 100 mV change from load voltage occurs, and begins to float
min for a Logic ‘‘1’’ and VOL max for a Logic ‘‘0’’. when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH e g 20 mA.
15
8XC51FX
PROGRAMMING THE EPROM/OTP Normally EA/VPP is held at logic high until just be-
fore ALE/PROG is to be pulsed. Then EA/VPP is
To be programmed, the part must be running with a raised to VPP, ALE/PROG is pulsed low, and then
4 to 6 MHz oscillator. (The reason the oscillator EA/VPP is returned to a valid high voltage. The volt-
needs to be running is that the internal bus is being age on the EA/VPP pin must be at the valid EA/VPP
used to transfer address and program data to appro- high level before a verify is attempted. Waveforms
priate internal EPROM locations.) The address of an and detailed timing specifications are shown in later
EPROM location to be programmed is applied to sections of this data sheet.
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied NOTE:
to Port 0. The other Port 2 and 3 pins, RST PSEN, # EA/VPP pin must not be allowed to go above the
and EA/VPP should be held at the ‘‘Program’’ levels maximum specified VPP level for any amount of
indicated in Table 4. ALE/PROG is pulsed low to time. Even a narrow glitch above that voltage lev-
program the code byte into the addressed EPROM el can cause permanent damage to the device.
location. The setup is shown in Figure 10. The VPP source should be well regulated and free
of glitches.
272322 – 20
*See Table 4 for proper input on these pins
16
8XC51FX
272322 – 21
ROM and EPROM Lock System lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
The 87C51FX program lock system, when pro- the lock bit. For the lock bit to be programmed, the
grammed, protects the onboard program against user must submit an encryption table. The 83C51FA
software piracy. does not have protection features.
The 83C51FX has a one-level program lock system The 87C51FX has a 3-level program lock system
and a 64-byte encryption table. See line 2 of Table and a 64-byte encryption array. Since this is an
5. If program protection is desired, the user submits EPROM device, all locations are user-programma-
the encryption table with their code, and both the ble. See Table 5.
17
8XC51FX
Encryption Array bytes in locations 30H and 31H. To read these bytes
follow the procedure for EPROM verify, but activate
Within the EPROM array are 64 bytes of Encryption the control lines provided in Table 4 for Read Signa-
Array that are initially unprogrammed (all 1’s). Every ture Byte.
time that a byte is addressed during a verify, 6 ad-
dress lines are used to select a byte of the Encryp- Location Device Contents
tion Array. This byte is then exclusive-NOR’ed 30H All 89H
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un- 31H All 58H
programmed state (all 1’s), will return the code in its 60H 83C51FA 7AH/FAH
original, unmodified form. For programming the En-
cryption Array, refer to Table 4 (Programming the 87C51FA FAH
EPROM).
83C51FB 7BH/FBH
When using the encryption array, one important fac- 87C51FB FBH
tor needs to be considered. If a code byte has the
value 0FFH, verifying the byte will produce the en- 83C51FC 7CH/FCH
cryption byte value. lf a large block ( l 64 bytes) of 87C51FC FCH
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH, and not Erasure Characteristics (Windowed
all of them the same value. This will ensure maxi- Packages Only)
mum program protection.
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
Program Lock Bits fluorescent lighting have wavelengths in this range,
The 87C51FX has 3 programmable lock bits that exposure to these light sources over an extended
when programmed according to Table 5 will provide time (about 1 week in sunlight, or 3 years in room-
different levels of protection for the on-chip code level fluorescent lighting) could cause inadvertent
and data. erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque la-
Erasing the EPROM also erases the encryption ar- bel be placed over the window.
ray and the program lock bits, returning the part to
full functionality. The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 mW/cm rat-
Reading the Signature Bytes ing for 30 minutes, at a distance of about 1 inch,
The 87C51FX has 3 signature bytes in locations should be sufficient.
30H, 31H, and 60H. The 83C51FA has 2 signature
Erasure leaves all the EPROM Cells in a 1’s state.
18
8XC51FX
272322 – 18
NOTE:
*5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
19
8XC51FX
The following differences exist between this datasheet (272322-003) and the previous version (272322-002):
1. Removed 8XC51FX-3 and 8XC51FX-20, replaced with 8XC51FX-24.
2. Included 8XC51FX-24 and 8XC51FX-33 devices.
3. 80C51FA and 83C51FA now have the same features as 87C51FA, 8XC51FB and 8XC51FC; same DC spec
used for all devices.
The following differences exist between the ‘‘-002’’ and ‘‘-001’’ version of 8XC51FX datasheet:
87C51FA/83C51FA/80C51FA 270258-007
83C51FA/80C51FA EXPRESS 270620-001
87C51FA EXPRESS 270619-001
87C51FA-20/-3 272081-002
87C51FB/83C51FB 270563-005
87C51FB-20/-3 83C51FB-20/-3 272080-002
87C51FB/83C51FB EXPRESS 270767-002
87C51FC/83C51FC 270789-004
87C51FC/83C51FC EXPRESS 270903-001
87C51FC-20/-3 83C51FC-20/-3 272028-002
20