Code No: R059210504 Set No.

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II B.Tech I Semester Supplimentary Examinations, February 2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from
memory. What was the original 8-bit data word that was written in to memory if
12-bit words read out is as follows? [4×4]

(a) 001111101010
(b) 101110010110
(c) 101110110100
(d) 110011010111.

2. (a) Explain in detail, the various levels of integration in ICs.

(b) Obtain the Dual of the following Boolean expressions.
i. AB + A(B + C) + B’(B + D)
ii. A + B + A’B’C.
(c) Obtain the complement of the following Boolean expressions. [8+4+4]
i. A’B + A’BC’ + A’BCD + A’BC’D’E
ii. ABEF + ABE’F’ + A’B’EF.

3. (a) Draw the multiple level NOR circuit for the following expression:
A (B + C + D) + BCD
(b) Simplify the following functions and implement two level NOR gates: [8+8]
i. f (A, B, C, D) = Σ0, 2, 4, 6, 8, 9, 10, 11, 12
ii. F (w, x, y, z) = Σ5, 6, 9, 11

4. (a) Implement 64 × 1 multiplexer with four 16 × 1 and one 4 ×1 multiplexer.

(Use only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB
F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]

5. (a) Define the following terms related to flip-flops.

i. hold time

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Code No: R059210504 Set No. 1
ii. propagation delay
iii. clock and
iv. direct inputs.
(b) Write an HDL functional description of a D- flip-flop and J-K- flip-flop. [8+8]

6. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagram
and timing diagrams.
(b) Draw the block diagram and explain the operation of serial transfer between
two shift registers and draw its timing diagram. [8+8]

7. (a) Explain the construction of a basic memory cell and also explain with diagram
the construction of a 4 * 4 RAM
(b) Given a 32*8 ROM chip with an enable input, show the external connections
necessary to construct a 128 * 8 ROM with four chips and a decoder. [8+8]

8. (a) Give the implementation procedure for a SR Latch using NOR gates.
(b) An asynchronous sequential circuit is described by the excitation and output
functions.
Y = x1 x′2 + (x1 + x′2 )y
Z=y
Implement the circuit defined above with a NOR SR latch. Repeat with a
NAND SR latch. [6+10]

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Code No: R059210504 Set No. 2
II B.Tech I Semester Supplimentary Examinations, February 2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Octal.

(a) 2A716
(b) 1BB 16
(c) 101101112
(d) 110110102
(e) 38710
(f) 67710 [3+3+3+3+2+2]

2. (a) Simplify the following Boolean functions.

i. x”yz + x’yz’ + xy’z’ + xy’z
ii. x’yz + xy’z’ + xyz + xyz’
iii. x’z + x’y + xy’z + yz
iv. x’y’z’ + x’yz’ + xy’z’ + xy’z + xyz’.
(b) Obtain the complement of the following Boolean expressions. [8+8]
i. A’C’ + ABC + AC’
ii. (x’y’ + z)’ + z + xy + wz
iii. A’B(D’ + C’D) + B(A +A’CD)
iv. (A’ + C)(A’ + C’)(A + B + C’D).

3. (a) Obtain minimal SOP expression for the given Boolean expression and hence
draw the circuit using NOR gates.
F (A, B, C, D) = BC + ABD + A BD + ABCD
(b) Draw NOR-logic diagram that implements the following function:
f (A, B, C, D) = Π0, 1, 2, 3, 4, 8, 9, 12 [8+8]

4. (a) Implement 64 × 1 multiplexer with four 16 × 1 and one 4 ×1 multiplexer.

(Use only block diagram).
(b) A combinational logic circuit is defined by the following Boolean functions.
F1 = ABC + AC
F2 = ABC + AB
F3 = ABC + AB
Design the circuit with a decoder and external gates. [8+8]

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Code No: R059210504 Set No. 2
5. (a) Convert the following
i. J-K flip-flop to T- flip-flop
ii. R-S flip-flop to D-flip-flop.
(b) Draw the circuit diagram of positive edge triggered J-K flip-flop with NAND
gates and explain its operation using truth table. How race around condition
is eliminated. [8+8]

6. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagram
and timing diagrams.
(b) Draw the block diagram and explain the operation of serial transfer between
two shift registers and draw its timing diagram. [8+8]

7. (a) Give the HDL code for a memory read, write operations if the memory size is
64 words of 4 bits each. Also explain the code.
(b) A 16K * 4 memory uses coincident decoding by splitting the internal decoder
into X-selection and Y-selection. [8+8]
i. What is the size of each decoder and how many AND gates are required
for decoding the address?
ii. Determine the X and Y selection lines that are enabled when the input
address is the binary equivalent of 6,000.

8. (a) Give the implementation procedure for a SR Latch using NOR gates.
(b) An asynchronous sequential circuit is described by the excitation and output
functions.
Y = x1 x′2 + (x1 + x′2 )y
Z=y
Implement the circuit defined above with a NOR SR latch. Repeat with a
NAND SR latch. [6+10]

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Code No: R059210504 Set No. 3
II B.Tech I Semester Supplimentary Examinations, February 2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) List the first 20 numbers in base12. Use the letters A and B to represent the
last two digits. [4]
(b) Convert the following numbers with the given radix to decimal.
i. 44335
ii. 119912
iii. 56547
iv. 6128 [3+3+3+3]
2. (a) Reduce the following Boolean expressions.
i. AB’ (C + BD) + A’B’
ii. A’B’C + (A + B + C’)’ + A’B’C’D
iii. ABCD + AB(CD)’ + (AB)’CD
iv. (A + A’)(AB + ABC’).
(b) Obtain the complement of the following Boolean expressions. [8+8]
i. ABC + A’B + ABC’
ii. (BC’ + A’D)(AB’ + CD’)
iii. x’yz + xz
iv. xy + x (wz + wz’).
3. (a) Draw K- map for the given Boolean function: f (A, B, C) = A ⊙ B ⊙ C ⊙
and show that it is equivalent to A ⊕ B ⊕ C.
(b) Obtain minimal SOP expression for the given Boolean function, using K-
map:F (A, B, C, D) = Σ(0,1,4,6,8,9,10,12) + d3,7,13,14,15 And draw the cir-
cuit using 2-input NAND gates. [8+8]
4. (a) Design a combinational logic circuit to compare two-two-bit binary numbers
AB, CD in which A is MSB and D is LSB, to produce an output Z=1 whenever
AB ≥ CD and Z = 0 if AB < CD. Draw the circuit using NAND gates.
(b) Draw the circuit diagram of a Full-subtractor using NOR gates. [8+8]
5. A sequential circuit with two J-K flip-flops A and B has one input X with following
input equations.
JA = B, KA = BX
JB = X, KB = A + X
Obtain logic diagram, state table and state diagram. [16]

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Code No: R059210504 Set No. 3
6. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagram
and timing diagrams.
(b) Draw the block diagram and explain the operation of serial transfer between
two shift registers and draw its timing diagram. [8+8]

7. (a) What is parity checking? Explain its necessity and how is it implemented?
(b) If the Hamming code sequence 1100110 is transmitted & due to error in one
position, is received as 1110110, locate the position of the error bit using parity
checks and give the method for obtaining the correct sequence. [8+8]

8. (a) i. Explain the difference between asynchronous and synchronous sequential

circuits.
ii. Define fundamental-mode operation.
iii. Explain the difference between stable and unstable states.
iv. What is the difference between an internal state and a total state.
(b) Explain critical and non critical races with the help of examples. [8+8]

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Code No: R059210504 Set No. 4
II B.Tech I Semester Supplimentary Examinations, February 2008
DIGITAL LOGIC DESIGN
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Binary and then to gray code. [2+2+2+2+4+4]

(a) 100116
(b) ABEF 16
(c) 76238
(d) 12348
(e) 125710
(f) 223910 .

2. (a) Find the complement of the following and show that F.F’ = 0 and F + F’ =
1.
i. F = xy’ + x’y
ii. F = (x + y’ + z)(x’ + z’)(x + y).
(b) Obtain the Dual of the following Boolean expressions. [8+8]
i.B’C’D + (B + C + D)’ + B’C’D’E
ii.AB + (AC)’ + (AB + C)
iii.A’B’C’ + A’BC’ + AB’C’ + ABC’
iv. AB + (AC)’ + AB’C.
P
3. (a) If F1 (A, B, C, D) =
P (1, 3, 4, 5, 9, 10, 11) + d6, 8 And
F2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression
for F1 ⊕ F2 using K- map and draw the circuit using NAND gates.
(b) Draw the multiple

-level NAND circuit for the following Boolean - expression:
AB + CD E + BC (A + B) [8+8]

4. (a) A combinational logic circuit is defined by the following Boolean function.

F (A, B, C, D) = Π (0, 2, 5, 6, 7, 8, 9, 10)
Design the circuit using 8 × 1 multiplexer and also design with 4 × 1 multi-
plexer with additional logic gates.
(b) A majority circuit is combinational circuit whose output is equal to 1 if the
Input variables have more 1’s than 0’s. The output is ‘0’ otherwise. Design a
4 - input majority circuit and draw the circuit using NAND gates. [8+8]

5. (a) Define the following terms related to filp-flops.

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Code No: R059210504 Set No. 4
i. set-up time
ii. hold time
iii. propagation delay
iv. preset and
v. clear.
(b) Distinguish between combinational logic and sequential logic. [10+6]

6. (a) Draw and explain 4-bit universal shift register.

(b) Explain different types of shift registers. [8+8]

7. (a) Explain the construction of a basic memory cell and also explain with diagram
the construction of a 4 * 4 RAM
(b) Given a 32*8 ROM chip with an enable input, show the external connections
necessary to construct a 128 * 8 ROM with four chips and a decoder. [8+8]

8. (a) Describe the operation of the SR Latch using NAND gate with the help of
truth table, transition table and the circuit.
(b) An asynchronous sequential circuit has two internal states and one output.
The excitation and output functions describing the functions are:
Y1 = x1 x2 + x1 y2′ + x′2 y1
Y2 = x2 + x1 y1′ y2 +x′1 y1
z= x2 + y1 Implement the circuit defined above with NAND SR latches. [8+8]

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