EE271 @ Thuy T.

Le SJSU-EE

EE271
Advanced Digital System Design & Synthesis

Introduction

Let’s start

Chapter 1: Introduction 1

Introduction to
Levels of Abstraction in
Digital Design Methodology
Dramatic Change in the Way Industry Does Hardware
Design – Why?
– Pervasive use of Computer-Aided Design Tools
– De-emphasis on hand design methods
– Emphasis on abstract design representations
– Hardware design begins to look like software design
– Emergence of Rapid Implementation Circuit Technology
– Programmable rather than discrete logic
– Synchronous Designs

Chapter 1: Introduction 2

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Moore’s law in Microprocessors

Transistors
Transistors on
on Microprocessors
Microprocessors double
double every
every 22 years
years

1000

Transistors (MT) 100 2X growth in 1.96 years!

10
P6
Pentium® proc
1 486
386
0.1 286
Courtesy, Intel
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Size: An IC made in 2002 could hold about 15,000 chips
of the logic density from 1981.
Chapter 1: Introduction 3

Frequency

Microprocessors
Microprocessors frequency
frequency doubles
doubles every
every 22 years
years

10000
Doubles every
1000
2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008 Courtesy, Intel
4004
0.1
1970 1980 1990 2000 2010
Year

Chapter 1: Introduction 4

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Gate Length and Delay Trends

Chapter 1: Introduction 5

Power will be a major problem

Microprocessors
Microprocessors power
power continues
continues to
to increase
increase
100000
Courtesy, Intel 18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive
Chapter 1: Introduction 6

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Challenges in Digital Design

“Microscopic Problems” “Macroscopic Issues”

• Ultra-high speed design, • Time-to-Market,
• Interconnect, • Millions of Gates
• Noise, Crosstalk, • High-Level
• Power Dissipation, Abstractions,
• Clock distribution, • Reuse, IP,
• Reliability, Portability,
Manufacturability. • Predictability, etc.

Chapter 1: Introduction 7

Technology Drivers
• Decreasing lithographic feature size, typically measured
by the transistor gate length: 0.35µm, …. 0.18µm,
0.15µm, …etc...., 0.050 µm ….
• Increasing wafer size: 6-inch diameter ….. 8-inch
diameter,….., 12-inche diameter, .....
• Increasing number of metal interconnect layers: 4, ….., 6
….., 8, …
• Approximately constant cost per wafer to manufacture:
About $2,000 - $4,000 per wafer
• Increasing IC yields (better manufacturing)
• For about every two years
– The number of transistors on a CMOS silicon chip doubles
– The clock speed doubles

Chapter 1: Introduction 8

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Why Scaling?
• Technology shrinks by 0.7/generation (average)
• With every generation can integrate 2x more functions per
chip; chip cost does not increase significantly
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population does not double every
two years…
• Hence, a need for more efficient design methods
– Solution: Exploit different levels of abstraction

Chapter 1: Introduction 9

Design Abstraction Levels

SYSTEM

MODULE
+

GATE
CIRCUIT

DEVICE
G
S D
n+ n+

Chapter 1: Introduction 10

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

(from) (Use) Type of (to get) Final Physical

Behavioral Synthesis Structural Objects
Forms Components
Processor - Executable System synthesis - Processors Printed circuit
(system) specification - Controllers boards
- Program - ASICs
- Memory

Register - Algorithms Architecture/ - Adders Microchips

(Module) - Flowcharts behavioral/ - Comparators (processors,
- Instruction sets high-level - Registers controllers, ASICs,
- FSM synthesis - Counters etc.)
- Datapaths, etc.
Gate 1. Boolean eq. 1. Logic synthesis - Gates Modules/units
- Flip-flops (adders,
comparators,
2. FSM 2. Seq. synthesis registers, counters,
etc.)
Transistor - Differential Several different - Transistors Analog and digital
equations type of synthesis - Resistors cells (gates, flip-
- Current-voltage techniques - Capacitors flops, etc.)
diagrams

Chapter 1: Introduction 11

Design Metrics
• How to evaluate performance of a digital circuit (gate,
block, …)?
– Area (yield and packaging cost)
– Speed (latency/delay, cycle-time)
– Power consumption/dissipation
– Throughput (for pipeline applications)
– Reliability
– Scalability

Chapter 1: Introduction 12

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Behavioral and Structural Views

Behavioral Structural view

Synthesis
view is an is an
abstract Architecture level interconnection
function of parts.
Synthesis

Logic level

Gate level
Physical Design

Physical view includes

Physical
view
physical objects with
size and positions

Chapter 1: Introduction 13

HDL

Waveforms
Waveforms Testbench Synthesis
Waveforms
Lib

netlist
rar

Library
y

Logic
Optimization

netlist

RTL Synthesis Flow Physical

Design

Layout
Chapter 1: Introduction 14

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

The Elements of Modern Design

Behaviors Design
Representations
Blocks
Waveforms
Gates
Truth Tables
Boolean Algebra
Rapid Prototyping
Switches Technologies
Simulation, Synthesis PAL, PLA, PLD
CMOS

TTL

Circuit
Technologies
Chapter 1: Introduction 15

ASIC and General Purpose IC

Application Specific Integrated Circuit (ASIC)
• Designed to perform a particular operation as opposed to
General Purpose integrated circuits
• Is NOT software programmable to perform a wide variety
of different tasks
• Often has an embedded CPU to manage tasks

• May be implemented as an FPGA

General Purpose Integrated Circuits:

• Programmable microprocessors (e.g. Intel Pentium Series,
Motorola HC-11)
• Programmable Digital Signal Processors (e.g. TI TMS 320
Series)
• Memory (DRAM, SRAM, etc.)

Chapter 1: Introduction 16

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Full Custom ASICs

• Every transistor is designed and drawn by hand (placing
transistors, sizing transistors, routing wires)
• Typically only way to design analog portions of ASICs

• Gives the highest performance but the longest design time

Gate-Array Based ASICs

• Transistors level masks are fully defined and the designer
can not change them
• The design instead programs the wiring to implement the
desired function
• The designs are slower than cell-based designs but the
implementation time is faster (less time in the factory)
• RTL-based methods and synthesis together with other CAD
tools are often used for gate arrays.
Chapter 1: Introduction 17

Programmable Logic Devices (PLDs)

• Off-the-shelf ICs that can be programmed by the user to
perform various functions (usually just combinational
logic functions)
• There are no custom mask layers so final design
implementation is a few hours instead of a few weeks
• Mostly are used for simple functions

Field Programmable Gate Arrays (FPGAs)

• Off-the-shelf chips that the user programs to perform
simple functions
• Can be quite complex, capable of implementing many
more gates than PLDs
• Some companies call them "complex PLD"

Chapter 1: Introduction 18

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Standard-Cell-Based/Cell Based IC (CBIC)/Semi-custom

• Standard Cells are custom designed and then inserted into
a library. These cells are wired together using ‘place and
route’ CAD tools
• Some standard cells such as RAM and ROM cells, and
some datapath cells (e.g. a multiplier) are tiled together to
create macrocells
• Custom designed blocks (e.g. microprocessors) might be
mixed in a library too (sometimes called megacells or hard
macros.)
• The designs are usually synthesized at RTL level

• Fabrication (and mostly place and route too) are performed

by another company (e.g. VLSI, TSMC, etc.).

Chapter 1: Introduction 19

Summary

ASIC Family Custom masks Custom cells

Full-custom Analog / digital All Some

Semi-custom Cell-based (CBIC) All None

Masked gate array Some None

(MGA)

Programmable Field-programmable None None

gate array (FPGA)

Programmable None None

logic device (PLD)

Chapter 1: Introduction 20

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Cell Libraries
• FPGA has library of logic cells in the form of a design kit
(have no choice)
• MGAs (masked gate array) and CBICs (cell based IC) have
three choices:
o ASIC vendor (company that build ASIC)

o Third-party library vendor

o Build your own cell library

• An ASIC vendor library is normally a phantom library (the

cells are empty boxes)
• Third-party library vendor normally:
• Develops a cell library using information about a process supplied by
an ASIC foundry
• Include the masks (tooling) that are used to manufacture the ASIC.

Chapter 1: Introduction 21

• An ASIC foundry (in contrast to an ASIC vendor) only

provides manufacturing, with no design help
• Each cell in an ASIC cell library must contain the
following information:
o A physical layout
o A behavioral model
o A Verilog/VHDL model
o A detailed timing model
o A test strategy
o A circuit schematic
o A cell icon
o A wire-load model
o A routing model
• Standard Cell designs are usually synthesized from RTL
level of the design

Chapter 1: Introduction 22

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

• ASIC designers also need a detailed timing model for

each cell to determine the performance of the critical
pieces of an ASIC.
• It is too difficult, too time-consuming, and too expensive
to build every cell in silicon and measure the cell delays.
Instead library engineers simulate the delay of each cell, a
process known as characterization.
• The cell schematic (a netlist description) describes each
cell so that the cell designer can perform simulation for
complex cells.
• Detailed cell schematic is not necessary for all cells, but
enough information is needed to compare the cell
schematic with the layout, this called "layout versus
schematic (LVS)" check.
Chapter 1: Introduction 23

• If schematic entry is used then cell icon together with

connector and naming information are needed for each cell
• Logic synthesis makes moving an ASIC between different
cell libraries much easier.
• In order to estimate the parasitic capacitance of wires,
statistical estimate of the capacitance for a net in a given
size circuit block is needed. This usually takes the form of
a look-up table known as a wire-load model.
• Routing model for each cell is necessary but large cells are
too complex for the physical design or layout tools to
handle directly and so there is the need for simpler
representation of the physical layout that still contains all
the necessary information.
• Place and route mostly are performed at fabrication
companies (VLSI, TSMC, etc.) or with their assistance
Chapter 1: Introduction 24

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Combinational vs. Sequential Logic

Combinational logic X1 Z1
• No feedback among inputs X2 Z2
Circuit
and outputs
• Outputs are a pure function Xn Zm
of the inputs

X1 Z1
X2 Z2 • The presence of feedback
Circuit
distinguishes between sequential
Xn Zm and combinational circuits.

Chapter 1: Introduction 25

Sequential logic
Outputs depend on inputs and the entire history of execution!
• Network typically has only a limited number of unique
configurations, these are called states
• Need storage elements to remember the current state
• Output and new state is a function of the inputs and the old
states, i.e., the fed back inputs are the states!

Í Synchronous systems: Period reference signal, the

clock, causes the storage elements to accept new
values and to change state.
Í Asynchronous systems: No single indication of
when to change state

Chapter 1: Introduction 26

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Computer-Aid: Simulations
• Program which dynamically executes an abstract design
description
• Obtain verification of functional correctness and some
timing information before the design is physically
constructed
• Easier to probe and debug a simulation than an
implemented design
• Simulation cannot guarantee that a design will work
− Only as good as the test cases attempted
− Does not check electrical errors
− Abstracts away some of the realities of a real system

Chapter 1: Introduction 27

Two Forms of Simulations

Logic Simulation
• Design described in terms of logic gates
• Values are 0, 1 (plus others to be introduced)
• Good for truth table verification

Timing Simulation – Dynamic Timing Analysis

• Waveform inputs and outputs
• Model of gate delays
• Are the waveform shapes what was expected?
• Identification of performance bottlenecks

Chapter 1: Introduction 28

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Gate-Level (logic-level) Simulation

Simulation Simulation
Netlist
driver monitor
(circuit)
(input vectors) (Waveforms)
Advantages of gate-level simulation:
’ Verifies timing and functionality simultaneously
’ Approach well understood by designers
Disadvantages of gate-level simulation
’ Computationally intensive - only 1 - 10 clock cycles of
100K gate design per 1 CPU second
’ Incomplete - results only as good as your vector set - easy
to overlook incorrect timing/behavior

Chapter 1: Introduction 29

Types of Logic Simulators

Logic Simulators

HDL-based Emulator-based Schematic-based

Event-driven Cycle-based Gate System

’ Emulators: Design is mapped into FPGA hardware for prototype

simulation. Used to perform hardware/software co-simulation.
Chapter 1: Introduction 30

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

’ Schematic-based: Design is entered graphically using a

schematic editor
’ Event-driven (gate/RTL/behavioral) simulations

– Verilog: VCS, Silos, NC-Verilog, Turbo-Verilog, etc.

– VHDL: VSS, MTI, Leapfrog
’ Cycle-based (gate/RTL/behavioral) simulations

– Since most digital designs are largely synchronous, state

elements change value on active edge of clock
– So only boundary nodes are evaluated and internal nodes are
ignored
– Verilog: Frontline, Speedsim
– VHDL: Cyclone

Circuit-level Simulations: Software such as Spice, Advice, etc.

Chapter 1: Introduction 31

Optimization Trade-off
Combinational Circuits
Area
max

’ Multi-criteria
optimization
’ Multiple objectives.

Delay
max

Chapter 1: Introduction 32

Chapter 1: Introduction
EE271 @ Thuy T. Le SJSU-EE

Area Sequential Circuits

max
Area
e
tim
max cle
Area Cy

max

Delay
max

Delay
max

Delay
max
Chapter 1: Introduction 33

Chapter 1: Introduction